bcmstb_spi.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018 Cisco Systems, Inc.
  4. *
  5. * Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
  6. */
  7. #include <asm/io.h>
  8. #include <command.h>
  9. #include <config.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <fdtdec.h>
  13. #include <linux/bitops.h>
  14. #include <linux/delay.h>
  15. #include <log.h>
  16. #include <malloc.h>
  17. #include <spi.h>
  18. #include <time.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #define SPBR_MIN 8
  21. #define BITS_PER_WORD 8
  22. #define NUM_TXRAM 32
  23. #define NUM_RXRAM 32
  24. #define NUM_CDRAM 16
  25. /* hif_mspi register structure. */
  26. struct bcmstb_hif_mspi_regs {
  27. u32 spcr0_lsb; /* 0x000 */
  28. u32 spcr0_msb; /* 0x004 */
  29. u32 spcr1_lsb; /* 0x008 */
  30. u32 spcr1_msb; /* 0x00c */
  31. u32 newqp; /* 0x010 */
  32. u32 endqp; /* 0x014 */
  33. u32 spcr2; /* 0x018 */
  34. u32 reserved0; /* 0x01c */
  35. u32 mspi_status; /* 0x020 */
  36. u32 cptqp; /* 0x024 */
  37. u32 spcr3; /* 0x028 */
  38. u32 revision; /* 0x02c */
  39. u32 reserved1[4]; /* 0x030 */
  40. u32 txram[NUM_TXRAM]; /* 0x040 */
  41. u32 rxram[NUM_RXRAM]; /* 0x0c0 */
  42. u32 cdram[NUM_CDRAM]; /* 0x140 */
  43. u32 write_lock; /* 0x180 */
  44. };
  45. /* hif_mspi masks. */
  46. #define HIF_MSPI_SPCR2_CONT_AFTER_CMD_MASK 0x00000080
  47. #define HIF_MSPI_SPCR2_SPE_MASK 0x00000040
  48. #define HIF_MSPI_SPCR2_SPIFIE_MASK 0x00000020
  49. #define HIF_MSPI_WRITE_LOCK_WRITE_LOCK_MASK 0x00000001
  50. /* bspi offsets. */
  51. #define BSPI_MAST_N_BOOT_CTRL 0x008
  52. /* bspi_raf is not used in this driver. */
  53. /* hif_spi_intr2 offsets and masks. */
  54. #define HIF_SPI_INTR2_CPU_CLEAR 0x08
  55. #define HIF_SPI_INTR2_CPU_MASK_SET 0x10
  56. #define HIF_SPI_INTR2_CPU_MASK_CLEAR 0x14
  57. #define HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK 0x00000020
  58. /* SPI transfer timeout in milliseconds. */
  59. #define HIF_MSPI_WAIT 10
  60. enum bcmstb_base_type {
  61. HIF_MSPI,
  62. BSPI,
  63. HIF_SPI_INTR2,
  64. CS_REG,
  65. BASE_LAST,
  66. };
  67. struct bcmstb_spi_platdata {
  68. void *base[4];
  69. };
  70. struct bcmstb_spi_priv {
  71. struct bcmstb_hif_mspi_regs *regs;
  72. void *bspi;
  73. void *hif_spi_intr2;
  74. void *cs_reg;
  75. int default_cs;
  76. int curr_cs;
  77. uint tx_slot;
  78. uint rx_slot;
  79. u8 saved_cmd[NUM_CDRAM];
  80. uint saved_cmd_len;
  81. void *saved_din_addr;
  82. };
  83. static int bcmstb_spi_ofdata_to_platdata(struct udevice *bus)
  84. {
  85. struct bcmstb_spi_platdata *plat = dev_get_platdata(bus);
  86. const void *fdt = gd->fdt_blob;
  87. int node = dev_of_offset(bus);
  88. int ret = 0;
  89. int i = 0;
  90. struct fdt_resource resource = { 0 };
  91. char *names[BASE_LAST] = { "hif_mspi", "bspi", "hif_spi_intr2",
  92. "cs_reg" };
  93. const phys_addr_t defaults[BASE_LAST] = { BCMSTB_HIF_MSPI_BASE,
  94. BCMSTB_BSPI_BASE,
  95. BCMSTB_HIF_SPI_INTR2,
  96. BCMSTB_CS_REG };
  97. for (i = 0; i < BASE_LAST; i++) {
  98. plat->base[i] = (void *)defaults[i];
  99. ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
  100. names[i], &resource);
  101. if (ret) {
  102. printf("%s: Assuming BCMSTB SPI %s address 0x0x%p\n",
  103. __func__, names[i], (void *)defaults[i]);
  104. } else {
  105. plat->base[i] = (void *)resource.start;
  106. debug("BCMSTB SPI %s address: 0x0x%p\n",
  107. names[i], (void *)plat->base[i]);
  108. }
  109. }
  110. return 0;
  111. }
  112. static void bcmstb_spi_hw_set_parms(struct bcmstb_spi_priv *priv)
  113. {
  114. writel(SPBR_MIN, &priv->regs->spcr0_lsb);
  115. writel(BITS_PER_WORD << 2 | SPI_MODE_3, &priv->regs->spcr0_msb);
  116. }
  117. static void bcmstb_spi_enable_interrupt(void *base, u32 mask)
  118. {
  119. void *reg = base + HIF_SPI_INTR2_CPU_MASK_CLEAR;
  120. writel(readl(reg) | mask, reg);
  121. readl(reg);
  122. }
  123. static void bcmstb_spi_disable_interrupt(void *base, u32 mask)
  124. {
  125. void *reg = base + HIF_SPI_INTR2_CPU_MASK_SET;
  126. writel(readl(reg) | mask, reg);
  127. readl(reg);
  128. }
  129. static void bcmstb_spi_clear_interrupt(void *base, u32 mask)
  130. {
  131. void *reg = base + HIF_SPI_INTR2_CPU_CLEAR;
  132. writel(readl(reg) | mask, reg);
  133. readl(reg);
  134. }
  135. static int bcmstb_spi_probe(struct udevice *bus)
  136. {
  137. struct bcmstb_spi_platdata *plat = dev_get_platdata(bus);
  138. struct bcmstb_spi_priv *priv = dev_get_priv(bus);
  139. priv->regs = plat->base[HIF_MSPI];
  140. priv->bspi = plat->base[BSPI];
  141. priv->hif_spi_intr2 = plat->base[HIF_SPI_INTR2];
  142. priv->cs_reg = plat->base[CS_REG];
  143. priv->default_cs = 0;
  144. priv->curr_cs = -1;
  145. priv->tx_slot = 0;
  146. priv->rx_slot = 0;
  147. memset(priv->saved_cmd, 0, NUM_CDRAM);
  148. priv->saved_cmd_len = 0;
  149. priv->saved_din_addr = NULL;
  150. debug("spi_xfer: tx regs: 0x%p\n", &priv->regs->txram[0]);
  151. debug("spi_xfer: rx regs: 0x%p\n", &priv->regs->rxram[0]);
  152. /* Disable BSPI. */
  153. writel(1, priv->bspi + BSPI_MAST_N_BOOT_CTRL);
  154. readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL);
  155. /* Set up interrupts. */
  156. bcmstb_spi_disable_interrupt(priv->hif_spi_intr2, 0xffffffff);
  157. bcmstb_spi_clear_interrupt(priv->hif_spi_intr2, 0xffffffff);
  158. bcmstb_spi_enable_interrupt(priv->hif_spi_intr2,
  159. HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK);
  160. /* Set up control registers. */
  161. writel(0, &priv->regs->spcr1_lsb);
  162. writel(0, &priv->regs->spcr1_msb);
  163. writel(0, &priv->regs->newqp);
  164. writel(0, &priv->regs->endqp);
  165. writel(HIF_MSPI_SPCR2_SPIFIE_MASK, &priv->regs->spcr2);
  166. writel(0, &priv->regs->spcr3);
  167. bcmstb_spi_hw_set_parms(priv);
  168. return 0;
  169. }
  170. static void bcmstb_spi_submit(struct bcmstb_spi_priv *priv, bool done)
  171. {
  172. debug("WR NEWQP: %d\n", 0);
  173. writel(0, &priv->regs->newqp);
  174. debug("WR ENDQP: %d\n", priv->tx_slot - 1);
  175. writel(priv->tx_slot - 1, &priv->regs->endqp);
  176. if (done) {
  177. debug("WR CDRAM[%d]: %02x\n", priv->tx_slot - 1,
  178. readl(&priv->regs->cdram[priv->tx_slot - 1]) & ~0x80);
  179. writel(readl(&priv->regs->cdram[priv->tx_slot - 1]) & ~0x80,
  180. &priv->regs->cdram[priv->tx_slot - 1]);
  181. }
  182. /* Force chip select first time. */
  183. if (priv->curr_cs != priv->default_cs) {
  184. debug("spi_xfer: switching chip select to %d\n",
  185. priv->default_cs);
  186. writel((readl(priv->cs_reg) & ~0xff) | (1 << priv->default_cs),
  187. priv->cs_reg);
  188. readl(priv->cs_reg);
  189. udelay(10);
  190. priv->curr_cs = priv->default_cs;
  191. }
  192. debug("WR WRITE_LOCK: %02x\n", 1);
  193. writel((readl(&priv->regs->write_lock) &
  194. ~HIF_MSPI_WRITE_LOCK_WRITE_LOCK_MASK) | 1,
  195. &priv->regs->write_lock);
  196. readl(&priv->regs->write_lock);
  197. debug("WR SPCR2: %02x\n",
  198. HIF_MSPI_SPCR2_SPIFIE_MASK |
  199. HIF_MSPI_SPCR2_SPE_MASK |
  200. HIF_MSPI_SPCR2_CONT_AFTER_CMD_MASK);
  201. writel(HIF_MSPI_SPCR2_SPIFIE_MASK |
  202. HIF_MSPI_SPCR2_SPE_MASK |
  203. HIF_MSPI_SPCR2_CONT_AFTER_CMD_MASK,
  204. &priv->regs->spcr2);
  205. }
  206. static int bcmstb_spi_wait(struct bcmstb_spi_priv *priv)
  207. {
  208. u32 start_time = get_timer(0);
  209. u32 status = readl(&priv->regs->mspi_status);
  210. while (!(status & 1)) {
  211. if (get_timer(start_time) > HIF_MSPI_WAIT)
  212. return -ETIMEDOUT;
  213. status = readl(&priv->regs->mspi_status);
  214. }
  215. writel(readl(&priv->regs->mspi_status) & ~1, &priv->regs->mspi_status);
  216. bcmstb_spi_clear_interrupt(priv->hif_spi_intr2,
  217. HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK);
  218. return 0;
  219. }
  220. static int bcmstb_spi_xfer(struct udevice *dev, unsigned int bitlen,
  221. const void *dout, void *din, unsigned long flags)
  222. {
  223. uint len = bitlen / 8;
  224. uint tx_len = len;
  225. uint rx_len = len;
  226. const u8 *out_bytes = (u8 *)dout;
  227. u8 *in_bytes = (u8 *)din;
  228. struct udevice *bus = dev_get_parent(dev);
  229. struct bcmstb_spi_priv *priv = dev_get_priv(bus);
  230. struct bcmstb_hif_mspi_regs *regs = priv->regs;
  231. debug("spi_xfer: %d, t: 0x%p, r: 0x%p, f: %lx\n",
  232. len, dout, din, flags);
  233. debug("spi_xfer: chip select: %x\n", readl(priv->cs_reg) & 0xff);
  234. debug("spi_xfer: tx addr: 0x%p\n", &regs->txram[0]);
  235. debug("spi_xfer: rx addr: 0x%p\n", &regs->rxram[0]);
  236. debug("spi_xfer: cd addr: 0x%p\n", &regs->cdram[0]);
  237. if (flags & SPI_XFER_END) {
  238. debug("spi_xfer: clearing saved din address: 0x%p\n",
  239. priv->saved_din_addr);
  240. priv->saved_din_addr = NULL;
  241. priv->saved_cmd_len = 0;
  242. memset(priv->saved_cmd, 0, NUM_CDRAM);
  243. }
  244. if (bitlen == 0)
  245. return 0;
  246. if (bitlen % 8) {
  247. printf("%s: Non-byte-aligned transfer\n", __func__);
  248. return -EOPNOTSUPP;
  249. }
  250. if (flags & ~(SPI_XFER_BEGIN | SPI_XFER_END)) {
  251. printf("%s: Unsupported flags: %lx\n", __func__, flags);
  252. return -EOPNOTSUPP;
  253. }
  254. if (flags & SPI_XFER_BEGIN) {
  255. priv->tx_slot = 0;
  256. priv->rx_slot = 0;
  257. if (out_bytes && len > NUM_CDRAM) {
  258. printf("%s: Unable to save transfer\n", __func__);
  259. return -EOPNOTSUPP;
  260. }
  261. if (out_bytes && !(flags & SPI_XFER_END)) {
  262. /*
  263. * This is the start of a transmit operation
  264. * that will need repeating if the calling
  265. * code polls for the result. Save it for
  266. * subsequent transmission.
  267. */
  268. debug("spi_xfer: saving command: %x, %d\n",
  269. out_bytes[0], len);
  270. priv->saved_cmd_len = len;
  271. memcpy(priv->saved_cmd, out_bytes, priv->saved_cmd_len);
  272. }
  273. }
  274. if (!(flags & (SPI_XFER_BEGIN | SPI_XFER_END))) {
  275. if (priv->saved_din_addr == din) {
  276. /*
  277. * The caller is polling for status. Repeat
  278. * the last transmission.
  279. */
  280. int ret = 0;
  281. debug("spi_xfer: Making recursive call\n");
  282. ret = bcmstb_spi_xfer(dev, priv->saved_cmd_len * 8,
  283. priv->saved_cmd, NULL,
  284. SPI_XFER_BEGIN);
  285. if (ret) {
  286. printf("%s: Recursive call failed\n", __func__);
  287. return ret;
  288. }
  289. } else {
  290. debug("spi_xfer: saving din address: 0x%p\n", din);
  291. priv->saved_din_addr = din;
  292. }
  293. }
  294. while (rx_len > 0) {
  295. priv->rx_slot = priv->tx_slot;
  296. while (priv->tx_slot < NUM_CDRAM && tx_len > 0) {
  297. bcmstb_spi_hw_set_parms(priv);
  298. debug("WR TXRAM[%d]: %02x\n", priv->tx_slot,
  299. out_bytes ? out_bytes[len - tx_len] : 0xff);
  300. writel(out_bytes ? out_bytes[len - tx_len] : 0xff,
  301. &regs->txram[priv->tx_slot << 1]);
  302. debug("WR CDRAM[%d]: %02x\n", priv->tx_slot, 0x8e);
  303. writel(0x8e, &regs->cdram[priv->tx_slot]);
  304. priv->tx_slot++;
  305. tx_len--;
  306. if (!in_bytes)
  307. rx_len--;
  308. }
  309. debug("spi_xfer: early return clauses: %d, %d, %d\n",
  310. len <= NUM_CDRAM,
  311. !in_bytes,
  312. (flags & (SPI_XFER_BEGIN |
  313. SPI_XFER_END)) == SPI_XFER_BEGIN);
  314. if (len <= NUM_CDRAM &&
  315. !in_bytes &&
  316. (flags & (SPI_XFER_BEGIN | SPI_XFER_END)) == SPI_XFER_BEGIN)
  317. return 0;
  318. bcmstb_spi_submit(priv, tx_len == 0);
  319. if (bcmstb_spi_wait(priv) == -ETIMEDOUT) {
  320. printf("%s: Timed out\n", __func__);
  321. return -ETIMEDOUT;
  322. }
  323. priv->tx_slot %= NUM_CDRAM;
  324. if (in_bytes) {
  325. while (priv->rx_slot < NUM_CDRAM && rx_len > 0) {
  326. in_bytes[len - rx_len] =
  327. readl(&regs->rxram[(priv->rx_slot << 1)
  328. + 1])
  329. & 0xff;
  330. debug("RD RXRAM[%d]: %02x\n",
  331. priv->rx_slot, in_bytes[len - rx_len]);
  332. priv->rx_slot++;
  333. rx_len--;
  334. }
  335. }
  336. }
  337. if (flags & SPI_XFER_END) {
  338. debug("WR WRITE_LOCK: %02x\n", 0);
  339. writel((readl(&priv->regs->write_lock) &
  340. ~HIF_MSPI_WRITE_LOCK_WRITE_LOCK_MASK) | 0,
  341. &priv->regs->write_lock);
  342. readl(&priv->regs->write_lock);
  343. }
  344. return 0;
  345. }
  346. static int bcmstb_spi_set_speed(struct udevice *dev, uint speed)
  347. {
  348. return 0;
  349. }
  350. static int bcmstb_spi_set_mode(struct udevice *dev, uint mode)
  351. {
  352. return 0;
  353. }
  354. static const struct dm_spi_ops bcmstb_spi_ops = {
  355. .xfer = bcmstb_spi_xfer,
  356. .set_speed = bcmstb_spi_set_speed,
  357. .set_mode = bcmstb_spi_set_mode,
  358. };
  359. static const struct udevice_id bcmstb_spi_id[] = {
  360. { .compatible = "brcm,spi-brcmstb" },
  361. { }
  362. };
  363. U_BOOT_DRIVER(bcmstb_spi) = {
  364. .name = "bcmstb_spi",
  365. .id = UCLASS_SPI,
  366. .of_match = bcmstb_spi_id,
  367. .ops = &bcmstb_spi_ops,
  368. .ofdata_to_platdata = bcmstb_spi_ofdata_to_platdata,
  369. .probe = bcmstb_spi_probe,
  370. .platdata_auto_alloc_size = sizeof(struct bcmstb_spi_platdata),
  371. .priv_auto_alloc_size = sizeof(struct bcmstb_spi_priv),
  372. };