MPC8349EMDS.h 9.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2006-2010
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. */
  6. /*
  7. * mpc8349emds board configuration file
  8. *
  9. */
  10. #ifndef __CONFIG_H
  11. #define __CONFIG_H
  12. /*
  13. * High Level Configuration Options
  14. */
  15. #define CONFIG_E300 1 /* E300 Family */
  16. #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
  17. /*
  18. * DDR Setup
  19. */
  20. #define CONFIG_DDR_ECC /* support DDR ECC function */
  21. #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
  22. #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
  23. /*
  24. * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
  25. * unselect it to use old spd_sdram.c
  26. */
  27. #define CONFIG_SYS_SPD_BUS_NUM 0
  28. #define SPD_EEPROM_ADDRESS1 0x52
  29. #define SPD_EEPROM_ADDRESS2 0x51
  30. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  31. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  32. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  33. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  34. #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  35. #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
  36. | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  37. /*
  38. * DDRCDR - DDR Control Driver Register
  39. */
  40. #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
  41. #if defined(CONFIG_SPD_EEPROM)
  42. /*
  43. * Determine DDR configuration from I2C interface.
  44. */
  45. #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
  46. #else
  47. /*
  48. * Manually set up DDR parameters
  49. */
  50. #define CONFIG_SYS_DDR_SIZE 256 /* MB */
  51. #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
  52. | CSCONFIG_ROW_BIT_13 \
  53. | CSCONFIG_COL_BIT_10)
  54. #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  55. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  56. #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  57. #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
  58. /* the default burst length is 4 - for 64-bit data path */
  59. /* DLL,normal,seq,4/2.5, 4 burst len */
  60. #define CONFIG_SYS_DDR_MODE 0x00000022
  61. #endif
  62. /*
  63. * SDRAM on the Local Bus
  64. */
  65. #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
  66. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  67. /*
  68. * FLASH on the Local Bus
  69. */
  70. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
  71. #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
  72. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  73. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
  74. #undef CONFIG_SYS_FLASH_CHECKSUM
  75. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  76. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  77. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  78. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  79. #define CONFIG_SYS_RAMBOOT
  80. #else
  81. #undef CONFIG_SYS_RAMBOOT
  82. #endif
  83. /*
  84. * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
  85. */
  86. #define CONFIG_SYS_BCSR 0xE2400000
  87. /* Access window base at BCSR base */
  88. #define CONFIG_SYS_INIT_RAM_LOCK 1
  89. #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
  90. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
  91. #define CONFIG_SYS_GBL_DATA_OFFSET \
  92. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  93. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  94. #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
  95. #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
  96. /*
  97. * Serial Port
  98. */
  99. #define CONFIG_SYS_NS16550_SERIAL
  100. #define CONFIG_SYS_NS16550_REG_SIZE 1
  101. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  102. #define CONFIG_SYS_BAUDRATE_TABLE \
  103. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
  104. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
  105. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
  106. /* I2C */
  107. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
  108. /* SPI */
  109. #undef CONFIG_SOFT_SPI /* SPI bit-banged */
  110. /* GPIOs. Used as SPI chip selects */
  111. #define CONFIG_SYS_GPIO1_PRELIM
  112. #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
  113. #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
  114. /* TSEC */
  115. #define CONFIG_SYS_TSEC1_OFFSET 0x24000
  116. #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
  117. #define CONFIG_SYS_TSEC2_OFFSET 0x25000
  118. #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
  119. /* USB */
  120. #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
  121. /*
  122. * General PCI
  123. * Addresses are mapped 1-1.
  124. */
  125. #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
  126. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
  127. #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
  128. #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
  129. #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
  130. #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
  131. #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
  132. #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
  133. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  134. #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
  135. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
  136. #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
  137. #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
  138. #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
  139. #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
  140. #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
  141. #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
  142. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  143. #if defined(CONFIG_PCI)
  144. #if !defined(CONFIG_PCI_PNP)
  145. #define PCI_ENET0_IOADDR 0xFIXME
  146. #define PCI_ENET0_MEMADDR 0xFIXME
  147. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  148. #endif
  149. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  150. #endif /* CONFIG_PCI */
  151. /*
  152. * TSEC configuration
  153. */
  154. #if defined(CONFIG_TSEC_ENET)
  155. #define CONFIG_GMII 1 /* MII PHY management */
  156. #define CONFIG_TSEC1 1
  157. #define CONFIG_TSEC1_NAME "TSEC0"
  158. #define CONFIG_TSEC2 1
  159. #define CONFIG_TSEC2_NAME "TSEC1"
  160. #define TSEC1_PHY_ADDR 0
  161. #define TSEC2_PHY_ADDR 1
  162. #define TSEC1_PHYIDX 0
  163. #define TSEC2_PHYIDX 0
  164. #define TSEC1_FLAGS TSEC_GIGABIT
  165. #define TSEC2_FLAGS TSEC_GIGABIT
  166. /* Options are: TSEC[0-1] */
  167. #define CONFIG_ETHPRIME "TSEC0"
  168. #endif /* CONFIG_TSEC_ENET */
  169. /*
  170. * Configure on-board RTC
  171. */
  172. #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
  173. #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
  174. /*
  175. * Environment
  176. */
  177. #ifndef CONFIG_SYS_RAMBOOT
  178. /* Address and size of Redundant Environment Sector */
  179. #endif
  180. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  181. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  182. /*
  183. * BOOTP options
  184. */
  185. #define CONFIG_BOOTP_BOOTFILESIZE
  186. #undef CONFIG_WATCHDOG /* watchdog disabled */
  187. /*
  188. * Miscellaneous configurable options
  189. */
  190. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  191. /*
  192. * For booting Linux, the board info and command line data
  193. * have to be in the first 256 MB of memory, since this is
  194. * the maximum mapped by the Linux kernel during initialization.
  195. */
  196. /* Initial Memory map for Linux*/
  197. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  198. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  199. #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
  200. /*
  201. * System performance
  202. */
  203. #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
  204. #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
  205. /* System IO Config */
  206. #define CONFIG_SYS_SICRH 0
  207. #define CONFIG_SYS_SICRL SICRL_LDP_A
  208. #ifdef CONFIG_PCI
  209. #define CONFIG_PCI_INDIRECT_BRIDGE
  210. #endif
  211. #if defined(CONFIG_CMD_KGDB)
  212. #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
  213. #endif
  214. /*
  215. * Environment Configuration
  216. */
  217. #if defined(CONFIG_TSEC_ENET)
  218. #define CONFIG_HAS_ETH1
  219. #define CONFIG_HAS_ETH0
  220. #endif
  221. #define CONFIG_HOSTNAME "mpc8349emds"
  222. #define CONFIG_ROOTPATH "/nfsroot/rootfs"
  223. #define CONFIG_BOOTFILE "uImage"
  224. #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
  225. #define CONFIG_EXTRA_ENV_SETTINGS \
  226. "netdev=eth0\0" \
  227. "hostname=mpc8349emds\0" \
  228. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  229. "nfsroot=${serverip}:${rootpath}\0" \
  230. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  231. "addip=setenv bootargs ${bootargs} " \
  232. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  233. ":${hostname}:${netdev}:off panic=1\0" \
  234. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  235. "flash_nfs=run nfsargs addip addtty;" \
  236. "bootm ${kernel_addr}\0" \
  237. "flash_self=run ramargs addip addtty;" \
  238. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  239. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  240. "bootm\0" \
  241. "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
  242. "update=protect off fe000000 fe03ffff; " \
  243. "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
  244. "upd=run load update\0" \
  245. "fdtaddr=780000\0" \
  246. "fdtfile=mpc834x_mds.dtb\0" \
  247. ""
  248. #define NFSBOOTCOMMAND \
  249. "setenv bootargs root=/dev/nfs rw " \
  250. "nfsroot=$serverip:$rootpath " \
  251. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
  252. "$netdev:off " \
  253. "console=$consoledev,$baudrate $othbootargs;" \
  254. "tftp $loadaddr $bootfile;" \
  255. "tftp $fdtaddr $fdtfile;" \
  256. "bootm $loadaddr - $fdtaddr"
  257. #define RAMBOOTCOMMAND \
  258. "setenv bootargs root=/dev/ram rw " \
  259. "console=$consoledev,$baudrate $othbootargs;" \
  260. "tftp $ramdiskaddr $ramdiskfile;" \
  261. "tftp $loadaddr $bootfile;" \
  262. "tftp $fdtaddr $fdtfile;" \
  263. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  264. #define CONFIG_BOOTCOMMAND "run flash_self"
  265. #endif /* __CONFIG_H */