spd_sdram.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2006-2007 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2006
  6. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  7. *
  8. * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
  9. * (C) Copyright 2003 Motorola Inc.
  10. * Xianghua Xiao (X.Xiao@motorola.com)
  11. */
  12. #ifndef CONFIG_MPC83XX_SDRAM
  13. #include <common.h>
  14. #include <cpu_func.h>
  15. #include <log.h>
  16. #include <time.h>
  17. #include <vsprintf.h>
  18. #include <asm/processor.h>
  19. #include <asm/io.h>
  20. #include <i2c.h>
  21. #include <spd.h>
  22. #include <asm/mmu.h>
  23. #include <spd_sdram.h>
  24. #include <asm/bitops.h>
  25. #include <asm/global_data.h>
  26. #include <linux/delay.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. void board_add_ram_info(int use_default)
  29. {
  30. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  31. volatile ddr83xx_t *ddr = &immap->ddr;
  32. char buf[32];
  33. printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
  34. >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
  35. #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
  36. if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
  37. puts(", 16-bit");
  38. else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)
  39. puts(", 32-bit");
  40. else
  41. puts(", unknown width");
  42. #else
  43. if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
  44. puts(", 32-bit");
  45. else
  46. puts(", 64-bit");
  47. #endif
  48. if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
  49. puts(", ECC on");
  50. else
  51. puts(", ECC off");
  52. printf(", %s MHz)", strmhz(buf, gd->mem_clk));
  53. #if defined(CONFIG_SYS_LB_SDRAM) && defined(CONFIG_SYS_LBC_SDRAM_SIZE)
  54. puts("\nSDRAM: ");
  55. print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
  56. #endif
  57. }
  58. #ifdef CONFIG_SPD_EEPROM
  59. #ifndef CONFIG_SYS_READ_SPD
  60. #define CONFIG_SYS_READ_SPD i2c_read
  61. #endif
  62. #ifndef SPD_EEPROM_OFFSET
  63. #define SPD_EEPROM_OFFSET 0
  64. #endif
  65. #ifndef SPD_EEPROM_ADDR_LEN
  66. #define SPD_EEPROM_ADDR_LEN 1
  67. #endif
  68. /*
  69. * Convert picoseconds into clock cycles (rounding up if needed).
  70. */
  71. int
  72. picos_to_clk(int picos)
  73. {
  74. unsigned int mem_bus_clk;
  75. int clks;
  76. mem_bus_clk = gd->mem_clk >> 1;
  77. clks = picos / (1000000000 / (mem_bus_clk / 1000));
  78. if (picos % (1000000000 / (mem_bus_clk / 1000)) != 0)
  79. clks++;
  80. return clks;
  81. }
  82. unsigned int banksize(unsigned char row_dens)
  83. {
  84. return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
  85. }
  86. int read_spd(uint addr)
  87. {
  88. return ((int) addr);
  89. }
  90. #undef SPD_DEBUG
  91. #ifdef SPD_DEBUG
  92. static void spd_debug(spd_eeprom_t *spd)
  93. {
  94. printf ("\nDIMM type: %-18.18s\n", spd->mpart);
  95. printf ("SPD size: %d\n", spd->info_size);
  96. printf ("EEPROM size: %d\n", 1 << spd->chip_size);
  97. printf ("Memory type: %d\n", spd->mem_type);
  98. printf ("Row addr: %d\n", spd->nrow_addr);
  99. printf ("Column addr: %d\n", spd->ncol_addr);
  100. printf ("# of rows: %d\n", spd->nrows);
  101. printf ("Row density: %d\n", spd->row_dens);
  102. printf ("# of banks: %d\n", spd->nbanks);
  103. printf ("Data width: %d\n",
  104. 256 * spd->dataw_msb + spd->dataw_lsb);
  105. printf ("Chip width: %d\n", spd->primw);
  106. printf ("Refresh rate: %02X\n", spd->refresh);
  107. printf ("CAS latencies: %02X\n", spd->cas_lat);
  108. printf ("Write latencies: %02X\n", spd->write_lat);
  109. printf ("tRP: %d\n", spd->trp);
  110. printf ("tRCD: %d\n", spd->trcd);
  111. printf ("\n");
  112. }
  113. #endif /* SPD_DEBUG */
  114. long int spd_sdram()
  115. {
  116. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  117. volatile ddr83xx_t *ddr = &immap->ddr;
  118. volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
  119. spd_eeprom_t spd;
  120. unsigned int n_ranks;
  121. unsigned int odt_rd_cfg, odt_wr_cfg;
  122. unsigned char twr_clk, twtr_clk;
  123. unsigned int sdram_type;
  124. unsigned int memsize;
  125. unsigned int law_size;
  126. unsigned char caslat, caslat_ctrl;
  127. unsigned int trfc, trfc_clk, trfc_low;
  128. unsigned int trcd_clk, trtp_clk;
  129. unsigned char cke_min_clk;
  130. unsigned char add_lat, wr_lat;
  131. unsigned char wr_data_delay;
  132. unsigned char four_act;
  133. unsigned char cpo;
  134. unsigned char burstlen;
  135. unsigned char odt_cfg, mode_odt_enable;
  136. unsigned int max_bus_clk;
  137. unsigned int max_data_rate, effective_data_rate;
  138. unsigned int ddrc_clk;
  139. unsigned int refresh_clk;
  140. unsigned int sdram_cfg;
  141. unsigned int ddrc_ecc_enable;
  142. unsigned int pvr = get_pvr();
  143. /*
  144. * First disable the memory controller (could be enabled
  145. * by the debugger)
  146. */
  147. clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
  148. sync();
  149. isync();
  150. /* Read SPD parameters with I2C */
  151. CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET,
  152. SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd));
  153. #ifdef SPD_DEBUG
  154. spd_debug(&spd);
  155. #endif
  156. /* Check the memory type */
  157. if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
  158. debug("DDR: Module mem type is %02X\n", spd.mem_type);
  159. return 0;
  160. }
  161. /* Check the number of physical bank */
  162. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  163. n_ranks = spd.nrows;
  164. } else {
  165. n_ranks = (spd.nrows & 0x7) + 1;
  166. }
  167. if (n_ranks > 2) {
  168. printf("DDR: The number of physical bank is %02X\n", n_ranks);
  169. return 0;
  170. }
  171. /* Check if the number of row of the module is in the range of DDRC */
  172. if (spd.nrow_addr < 12 || spd.nrow_addr > 15) {
  173. printf("DDR: Row number is out of range of DDRC, row=%02X\n",
  174. spd.nrow_addr);
  175. return 0;
  176. }
  177. /* Check if the number of col of the module is in the range of DDRC */
  178. if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
  179. printf("DDR: Col number is out of range of DDRC, col=%02X\n",
  180. spd.ncol_addr);
  181. return 0;
  182. }
  183. #ifdef CONFIG_SYS_DDRCDR_VALUE
  184. /*
  185. * Adjust DDR II IO voltage biasing. It just makes it work.
  186. */
  187. if(spd.mem_type == SPD_MEMTYPE_DDR2) {
  188. immap->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
  189. }
  190. udelay(50000);
  191. #endif
  192. /*
  193. * ODT configuration recommendation from DDR Controller Chapter.
  194. */
  195. odt_rd_cfg = 0; /* Never assert ODT */
  196. odt_wr_cfg = 0; /* Never assert ODT */
  197. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  198. odt_wr_cfg = 1; /* Assert ODT on writes to CSn */
  199. }
  200. /* Setup DDR chip select register */
  201. #ifdef CONFIG_SYS_83XX_DDR_USES_CS0
  202. ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
  203. ddr->cs_config[0] = ( 1 << 31
  204. | (odt_rd_cfg << 20)
  205. | (odt_wr_cfg << 16)
  206. | ((spd.nbanks == 8 ? 1 : 0) << 14)
  207. | ((spd.nrow_addr - 12) << 8)
  208. | (spd.ncol_addr - 8) );
  209. debug("\n");
  210. debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
  211. debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
  212. if (n_ranks == 2) {
  213. ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
  214. | ((banksize(spd.row_dens) >> 23) - 1) );
  215. ddr->cs_config[1] = ( 1<<31
  216. | (odt_rd_cfg << 20)
  217. | (odt_wr_cfg << 16)
  218. | ((spd.nbanks == 8 ? 1 : 0) << 14)
  219. | ((spd.nrow_addr - 12) << 8)
  220. | (spd.ncol_addr - 8) );
  221. debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
  222. debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
  223. }
  224. #else
  225. ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
  226. ddr->cs_config[2] = ( 1 << 31
  227. | (odt_rd_cfg << 20)
  228. | (odt_wr_cfg << 16)
  229. | ((spd.nbanks == 8 ? 1 : 0) << 14)
  230. | ((spd.nrow_addr - 12) << 8)
  231. | (spd.ncol_addr - 8) );
  232. debug("\n");
  233. debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
  234. debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
  235. if (n_ranks == 2) {
  236. ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
  237. | ((banksize(spd.row_dens) >> 23) - 1) );
  238. ddr->cs_config[3] = ( 1<<31
  239. | (odt_rd_cfg << 20)
  240. | (odt_wr_cfg << 16)
  241. | ((spd.nbanks == 8 ? 1 : 0) << 14)
  242. | ((spd.nrow_addr - 12) << 8)
  243. | (spd.ncol_addr - 8) );
  244. debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
  245. debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
  246. }
  247. #endif
  248. /*
  249. * Figure out memory size in Megabytes.
  250. */
  251. memsize = n_ranks * banksize(spd.row_dens) / 0x100000;
  252. /*
  253. * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
  254. */
  255. law_size = 19 + __ilog2(memsize);
  256. /*
  257. * Set up LAWBAR for all of DDR.
  258. */
  259. ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
  260. ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
  261. debug("DDR:bar=0x%08x\n", ecm->bar);
  262. debug("DDR:ar=0x%08x\n", ecm->ar);
  263. /*
  264. * Find the largest CAS by locating the highest 1 bit
  265. * in the spd.cas_lat field. Translate it to a DDR
  266. * controller field value:
  267. *
  268. * CAS Lat DDR I DDR II Ctrl
  269. * Clocks SPD Bit SPD Bit Value
  270. * ------- ------- ------- -----
  271. * 1.0 0 0001
  272. * 1.5 1 0010
  273. * 2.0 2 2 0011
  274. * 2.5 3 0100
  275. * 3.0 4 3 0101
  276. * 3.5 5 0110
  277. * 4.0 6 4 0111
  278. * 4.5 1000
  279. * 5.0 5 1001
  280. */
  281. caslat = __ilog2(spd.cas_lat);
  282. if ((spd.mem_type == SPD_MEMTYPE_DDR)
  283. && (caslat > 6)) {
  284. printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
  285. return 0;
  286. } else if (spd.mem_type == SPD_MEMTYPE_DDR2
  287. && (caslat < 2 || caslat > 5)) {
  288. printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
  289. spd.cas_lat);
  290. return 0;
  291. }
  292. debug("DDR: caslat SPD bit is %d\n", caslat);
  293. max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
  294. + (spd.clk_cycle & 0x0f));
  295. max_data_rate = max_bus_clk * 2;
  296. debug("DDR:Module maximum data rate is: %d MHz\n", max_data_rate);
  297. ddrc_clk = gd->mem_clk / 1000000;
  298. effective_data_rate = 0;
  299. if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */
  300. if (spd.cas_lat & 0x08)
  301. caslat = 3;
  302. else
  303. caslat = 4;
  304. if (ddrc_clk <= 460 && ddrc_clk > 350)
  305. effective_data_rate = 400;
  306. else if (ddrc_clk <=350 && ddrc_clk > 280)
  307. effective_data_rate = 333;
  308. else if (ddrc_clk <= 280 && ddrc_clk > 230)
  309. effective_data_rate = 266;
  310. else
  311. effective_data_rate = 200;
  312. } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */
  313. if (ddrc_clk <= 460 && ddrc_clk > 350) {
  314. /* DDR controller clk at 350~460 */
  315. effective_data_rate = 400; /* 5ns */
  316. caslat = caslat;
  317. } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
  318. /* DDR controller clk at 280~350 */
  319. effective_data_rate = 333; /* 6ns */
  320. if (spd.clk_cycle2 == 0x60)
  321. caslat = caslat - 1;
  322. else
  323. caslat = caslat;
  324. } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
  325. /* DDR controller clk at 230~280 */
  326. effective_data_rate = 266; /* 7.5ns */
  327. if (spd.clk_cycle3 == 0x75)
  328. caslat = caslat - 2;
  329. else if (spd.clk_cycle2 == 0x75)
  330. caslat = caslat - 1;
  331. else
  332. caslat = caslat;
  333. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  334. /* DDR controller clk at 90~230 */
  335. effective_data_rate = 200; /* 10ns */
  336. if (spd.clk_cycle3 == 0xa0)
  337. caslat = caslat - 2;
  338. else if (spd.clk_cycle2 == 0xa0)
  339. caslat = caslat - 1;
  340. else
  341. caslat = caslat;
  342. }
  343. } else if (max_data_rate >= 323) { /* it is DDR 333 */
  344. if (ddrc_clk <= 350 && ddrc_clk > 280) {
  345. /* DDR controller clk at 280~350 */
  346. effective_data_rate = 333; /* 6ns */
  347. caslat = caslat;
  348. } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
  349. /* DDR controller clk at 230~280 */
  350. effective_data_rate = 266; /* 7.5ns */
  351. if (spd.clk_cycle2 == 0x75)
  352. caslat = caslat - 1;
  353. else
  354. caslat = caslat;
  355. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  356. /* DDR controller clk at 90~230 */
  357. effective_data_rate = 200; /* 10ns */
  358. if (spd.clk_cycle3 == 0xa0)
  359. caslat = caslat - 2;
  360. else if (spd.clk_cycle2 == 0xa0)
  361. caslat = caslat - 1;
  362. else
  363. caslat = caslat;
  364. }
  365. } else if (max_data_rate >= 256) { /* it is DDR 266 */
  366. if (ddrc_clk <= 350 && ddrc_clk > 280) {
  367. /* DDR controller clk at 280~350 */
  368. printf("DDR: DDR controller freq is more than "
  369. "max data rate of the module\n");
  370. return 0;
  371. } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
  372. /* DDR controller clk at 230~280 */
  373. effective_data_rate = 266; /* 7.5ns */
  374. caslat = caslat;
  375. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  376. /* DDR controller clk at 90~230 */
  377. effective_data_rate = 200; /* 10ns */
  378. if (spd.clk_cycle2 == 0xa0)
  379. caslat = caslat - 1;
  380. }
  381. } else if (max_data_rate >= 190) { /* it is DDR 200 */
  382. if (ddrc_clk <= 350 && ddrc_clk > 230) {
  383. /* DDR controller clk at 230~350 */
  384. printf("DDR: DDR controller freq is more than "
  385. "max data rate of the module\n");
  386. return 0;
  387. } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
  388. /* DDR controller clk at 90~230 */
  389. effective_data_rate = 200; /* 10ns */
  390. caslat = caslat;
  391. }
  392. }
  393. debug("DDR:Effective data rate is: %dMHz\n", effective_data_rate);
  394. debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
  395. /*
  396. * Errata DDR6 work around: input enable 2 cycles earlier.
  397. * including MPC834X Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
  398. */
  399. if(PVR_MAJ(pvr) <= 1 && spd.mem_type == SPD_MEMTYPE_DDR){
  400. if (caslat == 2)
  401. ddr->debug_reg = 0x201c0000; /* CL=2 */
  402. else if (caslat == 3)
  403. ddr->debug_reg = 0x202c0000; /* CL=2.5 */
  404. else if (caslat == 4)
  405. ddr->debug_reg = 0x202c0000; /* CL=3.0 */
  406. sync();
  407. debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
  408. }
  409. /*
  410. * Convert caslat clocks to DDR controller value.
  411. * Force caslat_ctrl to be DDR Controller field-sized.
  412. */
  413. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  414. caslat_ctrl = (caslat + 1) & 0x07;
  415. } else {
  416. caslat_ctrl = (2 * caslat - 1) & 0x0f;
  417. }
  418. debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
  419. debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
  420. caslat, caslat_ctrl);
  421. /*
  422. * Timing Config 0.
  423. * Avoid writing for DDR I.
  424. */
  425. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  426. unsigned char taxpd_clk = 8; /* By the book. */
  427. unsigned char tmrd_clk = 2; /* By the book. */
  428. unsigned char act_pd_exit = 2; /* Empirical? */
  429. unsigned char pre_pd_exit = 6; /* Empirical? */
  430. ddr->timing_cfg_0 = (0
  431. | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
  432. | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
  433. | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
  434. | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
  435. );
  436. debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
  437. }
  438. /*
  439. * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
  440. * use conservative value.
  441. * For DDR II, they are bytes 36 and 37, in quarter nanos.
  442. */
  443. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  444. twr_clk = 3; /* Clocks */
  445. twtr_clk = 1; /* Clocks */
  446. } else {
  447. twr_clk = picos_to_clk(spd.twr * 250);
  448. twtr_clk = picos_to_clk(spd.twtr * 250);
  449. if (twtr_clk < 2)
  450. twtr_clk = 2;
  451. }
  452. /*
  453. * Calculate Trfc, in picos.
  454. * DDR I: Byte 42 straight up in ns.
  455. * DDR II: Byte 40 and 42 swizzled some, in ns.
  456. */
  457. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  458. trfc = spd.trfc * 1000; /* up to ps */
  459. } else {
  460. unsigned int byte40_table_ps[8] = {
  461. 0,
  462. 250,
  463. 330,
  464. 500,
  465. 660,
  466. 750,
  467. 0,
  468. 0
  469. };
  470. trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
  471. + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
  472. }
  473. trfc_clk = picos_to_clk(trfc);
  474. /*
  475. * Trcd, Byte 29, from quarter nanos to ps and clocks.
  476. */
  477. trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
  478. /*
  479. * Convert trfc_clk to DDR controller fields. DDR I should
  480. * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
  481. * 83xx controller has an extended REFREC field of three bits.
  482. * The controller automatically adds 8 clocks to this value,
  483. * so preadjust it down 8 first before splitting it up.
  484. */
  485. trfc_low = (trfc_clk - 8) & 0xf;
  486. ddr->timing_cfg_1 =
  487. (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | /* PRETOACT */
  488. ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | /* ACTTOPRE */
  489. (trcd_clk << 20 ) | /* ACTTORW */
  490. (caslat_ctrl << 16 ) | /* CASLAT */
  491. (trfc_low << 12 ) | /* REFEC */
  492. ((twr_clk & 0x07) << 8) | /* WRRREC */
  493. ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | /* ACTTOACT */
  494. ((twtr_clk & 0x07) << 0) /* WRTORD */
  495. );
  496. /*
  497. * Additive Latency
  498. * For DDR I, 0.
  499. * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
  500. * which comes from Trcd, and also note that:
  501. * add_lat + caslat must be >= 4
  502. */
  503. add_lat = 0;
  504. if (spd.mem_type == SPD_MEMTYPE_DDR2
  505. && (odt_wr_cfg || odt_rd_cfg)
  506. && (caslat < 4)) {
  507. add_lat = 4 - caslat;
  508. if ((add_lat + caslat) < 4) {
  509. add_lat = 0;
  510. }
  511. }
  512. /*
  513. * Write Data Delay
  514. * Historically 0x2 == 4/8 clock delay.
  515. * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
  516. */
  517. wr_data_delay = 2;
  518. #ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY
  519. wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY;
  520. #endif
  521. /*
  522. * Write Latency
  523. * Read to Precharge
  524. * Minimum CKE Pulse Width.
  525. * Four Activate Window
  526. */
  527. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  528. /*
  529. * This is a lie. It should really be 1, but if it is
  530. * set to 1, bits overlap into the old controller's
  531. * otherwise unused ACSM field. If we leave it 0, then
  532. * the HW will magically treat it as 1 for DDR 1. Oh Yea.
  533. */
  534. wr_lat = 0;
  535. trtp_clk = 2; /* By the book. */
  536. cke_min_clk = 1; /* By the book. */
  537. four_act = 1; /* By the book. */
  538. } else {
  539. wr_lat = caslat - 1;
  540. /* Convert SPD value from quarter nanos to picos. */
  541. trtp_clk = picos_to_clk(spd.trtp * 250);
  542. if (trtp_clk < 2)
  543. trtp_clk = 2;
  544. trtp_clk += add_lat;
  545. cke_min_clk = 3; /* By the book. */
  546. four_act = picos_to_clk(37500); /* By the book. 1k pages? */
  547. }
  548. /*
  549. * Empirically set ~MCAS-to-preamble override for DDR 2.
  550. * Your mileage will vary.
  551. */
  552. cpo = 0;
  553. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  554. #ifdef CONFIG_SYS_DDR_CPO
  555. cpo = CONFIG_SYS_DDR_CPO;
  556. #else
  557. if (effective_data_rate == 266) {
  558. cpo = 0x4; /* READ_LAT + 1/2 */
  559. } else if (effective_data_rate == 333) {
  560. cpo = 0x6; /* READ_LAT + 1 */
  561. } else if (effective_data_rate == 400) {
  562. cpo = 0x7; /* READ_LAT + 5/4 */
  563. } else {
  564. /* Automatic calibration */
  565. cpo = 0x1f;
  566. }
  567. #endif
  568. }
  569. ddr->timing_cfg_2 = (0
  570. | ((add_lat & 0x7) << 28) /* ADD_LAT */
  571. | ((cpo & 0x1f) << 23) /* CPO */
  572. | ((wr_lat & 0x7) << 19) /* WR_LAT */
  573. | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
  574. | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
  575. | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
  576. | ((four_act & 0x1f) << 0) /* FOUR_ACT */
  577. );
  578. debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
  579. debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
  580. /* Check DIMM data bus width */
  581. if (spd.dataw_lsb < 64) {
  582. if (spd.mem_type == SPD_MEMTYPE_DDR)
  583. burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
  584. else
  585. burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
  586. debug("\n DDR DIMM: data bus width is 32 bit");
  587. } else {
  588. burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
  589. debug("\n DDR DIMM: data bus width is 64 bit");
  590. }
  591. /* Is this an ECC DDR chip? */
  592. if (spd.config == 0x02)
  593. debug(" with ECC\n");
  594. else
  595. debug(" without ECC\n");
  596. /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
  597. Burst type is sequential
  598. */
  599. if (spd.mem_type == SPD_MEMTYPE_DDR) {
  600. switch (caslat) {
  601. case 1:
  602. ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
  603. break;
  604. case 2:
  605. ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
  606. break;
  607. case 3:
  608. ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
  609. break;
  610. case 4:
  611. ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
  612. break;
  613. default:
  614. printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
  615. return 0;
  616. }
  617. } else {
  618. mode_odt_enable = 0x0; /* Default disabled */
  619. if (odt_wr_cfg || odt_rd_cfg) {
  620. /*
  621. * Bits 6 and 2 in Extended MRS(1)
  622. * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
  623. * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
  624. */
  625. mode_odt_enable = 0x40; /* 150 Ohm */
  626. }
  627. ddr->sdram_mode =
  628. (0
  629. | (1 << (16 + 10)) /* DQS Differential disable */
  630. #ifdef CONFIG_SYS_DDR_MODE_WEAK
  631. | (1 << (16 + 1)) /* weak driver (~60%) */
  632. #endif
  633. | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
  634. | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
  635. | ((twr_clk - 1) << 9) /* Write Recovery Autopre */
  636. | (caslat << 4) /* caslat */
  637. | (burstlen << 0) /* Burst length */
  638. );
  639. }
  640. debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
  641. /*
  642. * Clear EMRS2 and EMRS3.
  643. */
  644. ddr->sdram_mode2 = 0;
  645. debug("DDR: sdram_mode2 = 0x%08x\n", ddr->sdram_mode2);
  646. switch (spd.refresh) {
  647. case 0x00:
  648. case 0x80:
  649. refresh_clk = picos_to_clk(15625000);
  650. break;
  651. case 0x01:
  652. case 0x81:
  653. refresh_clk = picos_to_clk(3900000);
  654. break;
  655. case 0x02:
  656. case 0x82:
  657. refresh_clk = picos_to_clk(7800000);
  658. break;
  659. case 0x03:
  660. case 0x83:
  661. refresh_clk = picos_to_clk(31300000);
  662. break;
  663. case 0x04:
  664. case 0x84:
  665. refresh_clk = picos_to_clk(62500000);
  666. break;
  667. case 0x05:
  668. case 0x85:
  669. refresh_clk = picos_to_clk(125000000);
  670. break;
  671. default:
  672. refresh_clk = 0x512;
  673. break;
  674. }
  675. /*
  676. * Set BSTOPRE to 0x100 for page mode
  677. * If auto-charge is used, set BSTOPRE = 0
  678. */
  679. ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
  680. debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
  681. /*
  682. * SDRAM Cfg 2
  683. */
  684. odt_cfg = 0;
  685. #ifndef CONFIG_NEVER_ASSERT_ODT_TO_CPU
  686. if (odt_rd_cfg | odt_wr_cfg) {
  687. odt_cfg = 0x2; /* ODT to IOs during reads */
  688. }
  689. #endif
  690. if (spd.mem_type == SPD_MEMTYPE_DDR2) {
  691. ddr->sdram_cfg2 = (0
  692. | (0 << 26) /* True DQS */
  693. | (odt_cfg << 21) /* ODT only read */
  694. | (1 << 12) /* 1 refresh at a time */
  695. );
  696. debug("DDR: sdram_cfg2 = 0x%08x\n", ddr->sdram_cfg2);
  697. }
  698. #ifdef CONFIG_SYS_DDR_SDRAM_CLK_CNTL /* Optional platform specific value */
  699. ddr->sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  700. #endif
  701. debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
  702. sync();
  703. isync();
  704. udelay(600);
  705. /*
  706. * Figure out the settings for the sdram_cfg register. Build up
  707. * the value in 'sdram_cfg' before writing since the write into
  708. * the register will actually enable the memory controller, and all
  709. * settings must be done before enabling.
  710. *
  711. * sdram_cfg[0] = 1 (ddr sdram logic enable)
  712. * sdram_cfg[1] = 1 (self-refresh-enable)
  713. * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
  714. * 010 DDR 1 SDRAM
  715. * 011 DDR 2 SDRAM
  716. * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
  717. * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
  718. */
  719. if (spd.mem_type == SPD_MEMTYPE_DDR)
  720. sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
  721. else
  722. sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
  723. sdram_cfg = (0
  724. | SDRAM_CFG_MEM_EN /* DDR enable */
  725. | SDRAM_CFG_SREN /* Self refresh */
  726. | sdram_type /* SDRAM type */
  727. );
  728. /* sdram_cfg[3] = RD_EN - registered DIMM enable */
  729. if (spd.mod_attr & 0x02)
  730. sdram_cfg |= SDRAM_CFG_RD_EN;
  731. /* The DIMM is 32bit width */
  732. if (spd.dataw_lsb < 64) {
  733. if (spd.mem_type == SPD_MEMTYPE_DDR)
  734. sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
  735. if (spd.mem_type == SPD_MEMTYPE_DDR2)
  736. sdram_cfg |= SDRAM_CFG_32_BE;
  737. }
  738. ddrc_ecc_enable = 0;
  739. #if defined(CONFIG_DDR_ECC)
  740. /* Enable ECC with sdram_cfg[2] */
  741. if (spd.config == 0x02) {
  742. sdram_cfg |= 0x20000000;
  743. ddrc_ecc_enable = 1;
  744. /* disable error detection */
  745. ddr->err_disable = ~ECC_ERROR_ENABLE;
  746. /* set single bit error threshold to maximum value,
  747. * reset counter to zero */
  748. ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
  749. (0 << ECC_ERROR_MAN_SBEC_SHIFT);
  750. }
  751. debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
  752. debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
  753. #endif
  754. debug(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
  755. /* Enable controller, and GO! */
  756. ddr->sdram_cfg = sdram_cfg;
  757. sync();
  758. isync();
  759. udelay(500);
  760. debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
  761. return memsize; /*in MBytes*/
  762. }
  763. #endif /* CONFIG_SPD_EEPROM */
  764. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  765. static inline u32 mftbu(void)
  766. {
  767. u32 rval;
  768. asm volatile("mftbu %0" : "=r" (rval));
  769. return rval;
  770. }
  771. static inline u32 mftb(void)
  772. {
  773. u32 rval;
  774. asm volatile("mftb %0" : "=r" (rval));
  775. return rval;
  776. }
  777. /*
  778. * Use timebase counter, get_timer() is not available
  779. * at this point of initialization yet.
  780. */
  781. static __inline__ unsigned long get_tbms (void)
  782. {
  783. unsigned long tbl;
  784. unsigned long tbu1, tbu2;
  785. unsigned long ms;
  786. unsigned long long tmp;
  787. ulong tbclk = get_tbclk();
  788. /* get the timebase ticks */
  789. do {
  790. tbu1 = mftbu();
  791. tbl = mftb();
  792. tbu2 = mftbu();
  793. } while (tbu1 != tbu2);
  794. /* convert ticks to ms */
  795. tmp = (unsigned long long)(tbu1);
  796. tmp = (tmp << 32);
  797. tmp += (unsigned long long)(tbl);
  798. ms = tmp/(tbclk/1000);
  799. return ms;
  800. }
  801. /*
  802. * Initialize all of memory for ECC, then enable errors.
  803. */
  804. void ddr_enable_ecc(unsigned int dram_size)
  805. {
  806. volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  807. volatile ddr83xx_t *ddr= &immap->ddr;
  808. unsigned long t_start, t_end;
  809. register u64 *p;
  810. register uint size;
  811. unsigned int pattern[2];
  812. icache_enable();
  813. t_start = get_tbms();
  814. pattern[0] = 0xdeadbeef;
  815. pattern[1] = 0xdeadbeef;
  816. debug("ddr init: CPU FP write method\n");
  817. size = dram_size;
  818. for (p = 0; p < (u64*)(size); p++) {
  819. ppcDWstore((u32*)p, pattern);
  820. }
  821. sync();
  822. t_end = get_tbms();
  823. icache_disable();
  824. debug("\nREADY!!\n");
  825. debug("ddr init duration: %ld ms\n", t_end - t_start);
  826. /* Clear All ECC Errors */
  827. if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
  828. ddr->err_detect |= ECC_ERROR_DETECT_MME;
  829. if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
  830. ddr->err_detect |= ECC_ERROR_DETECT_MBE;
  831. if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
  832. ddr->err_detect |= ECC_ERROR_DETECT_SBE;
  833. if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
  834. ddr->err_detect |= ECC_ERROR_DETECT_MSE;
  835. /* Disable ECC-Interrupts */
  836. ddr->err_int_en &= ECC_ERR_INT_DISABLE;
  837. /* Enable errors for ECC */
  838. ddr->err_disable &= ECC_ERROR_ENABLE;
  839. sync();
  840. isync();
  841. }
  842. #endif /* CONFIG_DDR_ECC */
  843. #endif /* !CONFIG_MPC83XX_SDRAM */