mux.c 4.4 KB

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  1. /*
  2. * mux.c
  3. *
  4. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <common.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <asm/arch/hardware.h>
  18. #include <asm/arch/mux.h>
  19. #include <asm/io.h>
  20. #include <i2c.h>
  21. #include "board.h"
  22. static struct module_pin_mux uart0_pin_mux[] = {
  23. {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
  24. {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
  25. {-1},
  26. };
  27. static struct module_pin_mux mmc0_pin_mux[] = {
  28. {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
  29. {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
  30. {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
  31. {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
  32. {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
  33. {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
  34. {-1},
  35. };
  36. static struct module_pin_mux i2c1_pin_mux[] = {
  37. {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
  38. PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
  39. {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
  40. PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
  41. {-1},
  42. };
  43. static struct module_pin_mux rmii1_pin_mux[] = {
  44. {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
  45. {OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */
  46. {OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */
  47. {OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */
  48. {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
  49. {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */
  50. {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RGMII1_TCTL */
  51. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
  52. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  53. {-1},
  54. };
  55. static struct module_pin_mux rgmii2_pin_mux[] = {
  56. {OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */
  57. {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
  58. {OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */
  59. {OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */
  60. {OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */
  61. {OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */
  62. {OFFSET(gpmc_a6), MODE(2)}, /* RGMII1_TCLK */
  63. {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
  64. {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
  65. {OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
  66. {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
  67. {OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
  68. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
  69. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  70. {-1},
  71. };
  72. static struct module_pin_mux nand_pin_mux[] = {
  73. {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
  74. {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
  75. {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
  76. {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
  77. {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
  78. {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
  79. {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
  80. {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
  81. {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
  82. {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
  83. {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
  84. {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
  85. {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
  86. {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
  87. {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
  88. {-1},
  89. };
  90. void enable_uart0_pin_mux(void)
  91. {
  92. configure_module_pin_mux(uart0_pin_mux);
  93. }
  94. void enable_i2c1_pin_mux(void)
  95. {
  96. configure_module_pin_mux(i2c1_pin_mux);
  97. }
  98. void enable_board_pin_mux()
  99. {
  100. configure_module_pin_mux(i2c1_pin_mux);
  101. configure_module_pin_mux(rgmii2_pin_mux);
  102. configure_module_pin_mux(rmii1_pin_mux);
  103. configure_module_pin_mux(mmc0_pin_mux);
  104. #if defined(CONFIG_MTD_RAW_NAND)
  105. configure_module_pin_mux(nand_pin_mux);
  106. #endif
  107. }