board.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for TI AM335X based boards
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <errno.h>
  12. #include <init.h>
  13. #include <serial.h>
  14. #include <linux/libfdt.h>
  15. #include <spl.h>
  16. #include <asm/arch/cpu.h>
  17. #include <asm/arch/hardware.h>
  18. #include <asm/arch/omap.h>
  19. #include <asm/arch/ddr_defs.h>
  20. #include <asm/arch/clock.h>
  21. #include <asm/arch/gpio.h>
  22. #include <asm/arch/mmc_host_def.h>
  23. #include <asm/arch/sys_proto.h>
  24. #include <asm/arch/mem.h>
  25. #include <asm/arch/mux.h>
  26. #include <asm/io.h>
  27. #include <asm/emif.h>
  28. #include <asm/gpio.h>
  29. #include <i2c.h>
  30. #include <miiphy.h>
  31. #include <cpsw.h>
  32. #include <power/tps65910.h>
  33. #include <watchdog.h>
  34. #include "board.h"
  35. DECLARE_GLOBAL_DATA_PTR;
  36. /* GPIO that controls DIP switch and mPCIe slot */
  37. #define DIP_S1 44
  38. #define MPCIE_SW 100
  39. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  40. static int baltos_set_console(void)
  41. {
  42. int val, i, dips = 0;
  43. char buf[7];
  44. for (i = 0; i < 4; i++) {
  45. sprintf(buf, "dip_s%d", i + 1);
  46. if (gpio_request(DIP_S1 + i, buf)) {
  47. printf("failed to export GPIO %d\n", DIP_S1 + i);
  48. return 0;
  49. }
  50. if (gpio_direction_input(DIP_S1 + i)) {
  51. printf("failed to set GPIO %d direction\n", DIP_S1 + i);
  52. return 0;
  53. }
  54. val = gpio_get_value(DIP_S1 + i);
  55. dips |= val << i;
  56. }
  57. printf("DIPs: 0x%1x\n", (~dips) & 0xf);
  58. if ((dips & 0xf) == 0xe)
  59. env_set("console", "ttyUSB0,115200n8");
  60. return 0;
  61. }
  62. static int read_eeprom(BSP_VS_HWPARAM *header)
  63. {
  64. i2c_set_bus_num(1);
  65. /* Check if baseboard eeprom is available */
  66. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  67. puts("Could not probe the EEPROM; something fundamentally "
  68. "wrong on the I2C bus.\n");
  69. return -ENODEV;
  70. }
  71. /* read the eeprom using i2c */
  72. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  73. sizeof(BSP_VS_HWPARAM))) {
  74. puts("Could not read the EEPROM; something fundamentally"
  75. " wrong on the I2C bus.\n");
  76. return -EIO;
  77. }
  78. if (header->Magic != 0xDEADBEEF) {
  79. printf("Incorrect magic number (0x%x) in EEPROM\n",
  80. header->Magic);
  81. /* fill default values */
  82. header->SystemId = 211;
  83. header->MAC1[0] = 0x00;
  84. header->MAC1[1] = 0x00;
  85. header->MAC1[2] = 0x00;
  86. header->MAC1[3] = 0x00;
  87. header->MAC1[4] = 0x00;
  88. header->MAC1[5] = 0x01;
  89. header->MAC2[0] = 0x00;
  90. header->MAC2[1] = 0x00;
  91. header->MAC2[2] = 0x00;
  92. header->MAC2[3] = 0x00;
  93. header->MAC2[4] = 0x00;
  94. header->MAC2[5] = 0x02;
  95. header->MAC3[0] = 0x00;
  96. header->MAC3[1] = 0x00;
  97. header->MAC3[2] = 0x00;
  98. header->MAC3[3] = 0x00;
  99. header->MAC3[4] = 0x00;
  100. header->MAC3[5] = 0x03;
  101. }
  102. return 0;
  103. }
  104. #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
  105. static const struct ddr_data ddr3_baltos_data = {
  106. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  107. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  108. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  109. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  110. };
  111. static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
  112. .cmd0csratio = MT41K256M16HA125E_RATIO,
  113. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  114. .cmd1csratio = MT41K256M16HA125E_RATIO,
  115. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  116. .cmd2csratio = MT41K256M16HA125E_RATIO,
  117. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  118. };
  119. static struct emif_regs ddr3_baltos_emif_reg_data = {
  120. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  121. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  122. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  123. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  124. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  125. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  126. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  127. };
  128. #ifdef CONFIG_SPL_OS_BOOT
  129. int spl_start_uboot(void)
  130. {
  131. /* break into full u-boot on 'c' */
  132. return (serial_tstc() && serial_getc() == 'c');
  133. }
  134. #endif
  135. #define OSC (V_OSCK/1000000)
  136. const struct dpll_params dpll_ddr = {
  137. 266, OSC-1, 1, -1, -1, -1, -1};
  138. const struct dpll_params dpll_ddr_evm_sk = {
  139. 303, OSC-1, 1, -1, -1, -1, -1};
  140. const struct dpll_params dpll_ddr_baltos = {
  141. 400, OSC-1, 1, -1, -1, -1, -1};
  142. void am33xx_spl_board_init(void)
  143. {
  144. int mpu_vdd;
  145. int sil_rev;
  146. /* Get the frequency */
  147. dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  148. /*
  149. * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
  150. * MPU frequencies we support we use a CORE voltage of
  151. * 1.1375V. For MPU voltage we need to switch based on
  152. * the frequency we are running at.
  153. */
  154. i2c_set_bus_num(1);
  155. printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
  156. if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
  157. puts("i2c: cannot access TPS65910\n");
  158. return;
  159. }
  160. /*
  161. * Depending on MPU clock and PG we will need a different
  162. * VDD to drive at that speed.
  163. */
  164. sil_rev = readl(&cdev->deviceid) >> 28;
  165. mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
  166. dpll_mpu_opp100.m);
  167. /* Tell the TPS65910 to use i2c */
  168. tps65910_set_i2c_control();
  169. /* First update MPU voltage. */
  170. if (tps65910_voltage_update(MPU, mpu_vdd))
  171. return;
  172. /* Second, update the CORE voltage. */
  173. if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
  174. return;
  175. /* Set CORE Frequencies to OPP100 */
  176. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  177. /* Set MPU Frequency to what we detected now that voltages are set */
  178. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  179. writel(0x000010ff, PRM_DEVICE_INST + 4);
  180. }
  181. const struct dpll_params *get_dpll_ddr_params(void)
  182. {
  183. enable_i2c1_pin_mux();
  184. i2c_set_bus_num(1);
  185. return &dpll_ddr_baltos;
  186. }
  187. void set_uart_mux_conf(void)
  188. {
  189. enable_uart0_pin_mux();
  190. }
  191. void set_mux_conf_regs(void)
  192. {
  193. enable_board_pin_mux();
  194. }
  195. const struct ctrl_ioregs ioregs_baltos = {
  196. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  197. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  198. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  199. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  200. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  201. };
  202. void sdram_init(void)
  203. {
  204. config_ddr(400, &ioregs_baltos,
  205. &ddr3_baltos_data,
  206. &ddr3_baltos_cmd_ctrl_data,
  207. &ddr3_baltos_emif_reg_data, 0);
  208. }
  209. #endif
  210. /*
  211. * Basic board specific setup. Pinmux has been handled already.
  212. */
  213. int board_init(void)
  214. {
  215. #if defined(CONFIG_HW_WATCHDOG)
  216. hw_watchdog_init();
  217. #endif
  218. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  219. #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
  220. gpmc_init();
  221. #endif
  222. return 0;
  223. }
  224. int ft_board_setup(void *blob, bd_t *bd)
  225. {
  226. int node, ret;
  227. unsigned char mac_addr[6];
  228. BSP_VS_HWPARAM header;
  229. /* get production data */
  230. if (read_eeprom(&header))
  231. return 0;
  232. /* setup MAC1 */
  233. mac_addr[0] = header.MAC1[0];
  234. mac_addr[1] = header.MAC1[1];
  235. mac_addr[2] = header.MAC1[2];
  236. mac_addr[3] = header.MAC1[3];
  237. mac_addr[4] = header.MAC1[4];
  238. mac_addr[5] = header.MAC1[5];
  239. node = fdt_path_offset(blob, "ethernet0");
  240. if (node < 0) {
  241. printf("no ethernet0 path offset\n");
  242. return -ENODEV;
  243. }
  244. ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
  245. if (ret) {
  246. printf("error setting mac-address property\n");
  247. return -ENODEV;
  248. }
  249. /* setup MAC2 */
  250. mac_addr[0] = header.MAC2[0];
  251. mac_addr[1] = header.MAC2[1];
  252. mac_addr[2] = header.MAC2[2];
  253. mac_addr[3] = header.MAC2[3];
  254. mac_addr[4] = header.MAC2[4];
  255. mac_addr[5] = header.MAC2[5];
  256. node = fdt_path_offset(blob, "ethernet1");
  257. if (node < 0) {
  258. printf("no ethernet1 path offset\n");
  259. return -ENODEV;
  260. }
  261. ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
  262. if (ret) {
  263. printf("error setting mac-address property\n");
  264. return -ENODEV;
  265. }
  266. printf("\nFDT was successfully setup\n");
  267. return 0;
  268. }
  269. static struct module_pin_mux pcie_sw_pin_mux[] = {
  270. {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )}, /* GPIO3_4 */
  271. {-1},
  272. };
  273. static struct module_pin_mux dip_pin_mux[] = {
  274. {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */
  275. {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */
  276. {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */
  277. {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */
  278. {-1},
  279. };
  280. #ifdef CONFIG_BOARD_LATE_INIT
  281. int board_late_init(void)
  282. {
  283. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  284. BSP_VS_HWPARAM header;
  285. char model[4];
  286. /* get production data */
  287. if (read_eeprom(&header)) {
  288. strcpy(model, "211");
  289. } else {
  290. sprintf(model, "%d", header.SystemId);
  291. if (header.SystemId == 215) {
  292. configure_module_pin_mux(dip_pin_mux);
  293. baltos_set_console();
  294. }
  295. }
  296. /* turn power for the mPCIe slot */
  297. configure_module_pin_mux(pcie_sw_pin_mux);
  298. if (gpio_request(MPCIE_SW, "mpcie_sw")) {
  299. printf("failed to export GPIO %d\n", MPCIE_SW);
  300. return -ENODEV;
  301. }
  302. if (gpio_direction_output(MPCIE_SW, 1)) {
  303. printf("failed to set GPIO %d direction\n", MPCIE_SW);
  304. return -ENODEV;
  305. }
  306. env_set("board_name", model);
  307. #endif
  308. return 0;
  309. }
  310. #endif
  311. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  312. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  313. static void cpsw_control(int enabled)
  314. {
  315. /* VTP can be added here */
  316. return;
  317. }
  318. static struct cpsw_slave_data cpsw_slaves[] = {
  319. {
  320. .slave_reg_ofs = 0x208,
  321. .sliver_reg_ofs = 0xd80,
  322. .phy_addr = 0,
  323. },
  324. {
  325. .slave_reg_ofs = 0x308,
  326. .sliver_reg_ofs = 0xdc0,
  327. .phy_addr = 7,
  328. },
  329. };
  330. static struct cpsw_platform_data cpsw_data = {
  331. .mdio_base = CPSW_MDIO_BASE,
  332. .cpsw_base = CPSW_BASE,
  333. .mdio_div = 0xff,
  334. .channels = 8,
  335. .cpdma_reg_ofs = 0x800,
  336. .slaves = 2,
  337. .slave_data = cpsw_slaves,
  338. .active_slave = 1,
  339. .ale_reg_ofs = 0xd00,
  340. .ale_entries = 1024,
  341. .host_port_reg_ofs = 0x108,
  342. .hw_stats_reg_ofs = 0x900,
  343. .bd_ram_ofs = 0x2000,
  344. .mac_control = (1 << 5),
  345. .control = cpsw_control,
  346. .host_port_num = 0,
  347. .version = CPSW_CTRL_VERSION_2,
  348. };
  349. #endif
  350. #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) \
  351. && defined(CONFIG_SPL_BUILD)) || \
  352. ((defined(CONFIG_DRIVER_TI_CPSW) || \
  353. defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
  354. !defined(CONFIG_SPL_BUILD))
  355. int board_eth_init(bd_t *bis)
  356. {
  357. int rv, n = 0;
  358. uint8_t mac_addr[6];
  359. uint32_t mac_hi, mac_lo;
  360. /*
  361. * Note here that we're using CPSW1 since that has a 1Gbit PHY while
  362. * CSPW0 has a 100Mbit PHY.
  363. *
  364. * On product, CPSW1 maps to port labeled WAN.
  365. */
  366. /* try reading mac address from efuse */
  367. mac_lo = readl(&cdev->macid1l);
  368. mac_hi = readl(&cdev->macid1h);
  369. mac_addr[0] = mac_hi & 0xFF;
  370. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  371. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  372. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  373. mac_addr[4] = mac_lo & 0xFF;
  374. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  375. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  376. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  377. if (!env_get("ethaddr")) {
  378. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  379. if (is_valid_ethaddr(mac_addr))
  380. eth_env_set_enetaddr("ethaddr", mac_addr);
  381. }
  382. #ifdef CONFIG_DRIVER_TI_CPSW
  383. writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
  384. cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
  385. rv = cpsw_register(&cpsw_data);
  386. if (rv < 0)
  387. printf("Error %d registering CPSW switch\n", rv);
  388. else
  389. n += rv;
  390. #endif
  391. /*
  392. *
  393. * CPSW RGMII Internal Delay Mode is not supported in all PVT
  394. * operating points. So we must set the TX clock delay feature
  395. * in the AR8051 PHY. Since we only support a single ethernet
  396. * device in U-Boot, we only do this for the first instance.
  397. */
  398. #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
  399. #define AR8051_PHY_DEBUG_DATA_REG 0x1e
  400. #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
  401. #define AR8051_RGMII_TX_CLK_DLY 0x100
  402. const char *devname;
  403. devname = miiphy_get_current_dev();
  404. miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
  405. AR8051_DEBUG_RGMII_CLK_DLY_REG);
  406. miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
  407. AR8051_RGMII_TX_CLK_DLY);
  408. #endif
  409. return n;
  410. }
  411. #endif