mux.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * mux.c
  4. *
  5. * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
  6. */
  7. #include <common.h>
  8. #include <asm/arch/sys_proto.h>
  9. #include <asm/arch/mux.h>
  10. #include "../common/board_detect.h"
  11. #include "board.h"
  12. static struct module_pin_mux rmii1_pin_mux[] = {
  13. {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
  14. {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TD1 */
  15. {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TD0 */
  16. {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RD1 */
  17. {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RD0 */
  18. {OFFSET(mii1_rxdv), MODE(1) | RXACTIVE}, /* RMII1_RXDV */
  19. {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS_DV */
  20. {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
  21. {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_refclk */
  22. {-1},
  23. };
  24. static struct module_pin_mux rgmii1_pin_mux[] = {
  25. {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
  26. {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
  27. {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
  28. {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
  29. {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
  30. {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
  31. {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
  32. {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
  33. {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
  34. {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
  35. {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
  36. {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
  37. {-1},
  38. };
  39. static struct module_pin_mux mdio_pin_mux[] = {
  40. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
  41. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  42. {-1},
  43. };
  44. static struct module_pin_mux uart0_pin_mux[] = {
  45. {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
  46. {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS | PULLUP_EN | SLEWCTRL)},
  47. {-1},
  48. };
  49. static struct module_pin_mux mmc0_pin_mux[] = {
  50. {OFFSET(mmc0_clk), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* MMC0_CLK */
  51. {OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CMD */
  52. {OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT0 */
  53. {OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT1 */
  54. {OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT2 */
  55. {OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_DAT3 */
  56. {-1},
  57. };
  58. static struct module_pin_mux i2c0_pin_mux[] = {
  59. {OFFSET(i2c0_sda), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
  60. {OFFSET(i2c0_scl), (MODE(0) | PULLUP_EN | RXACTIVE | SLEWCTRL)},
  61. {-1},
  62. };
  63. static struct module_pin_mux gpio5_7_pin_mux[] = {
  64. {OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)}, /* GPIO5_7 */
  65. {-1},
  66. };
  67. #ifdef CONFIG_MTD_RAW_NAND
  68. static struct module_pin_mux nand_pin_mux[] = {
  69. {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD0 */
  70. {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD1 */
  71. {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD2 */
  72. {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD3 */
  73. {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD4 */
  74. {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD5 */
  75. {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD6 */
  76. {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD7 */
  77. #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
  78. {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD8 */
  79. {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD9 */
  80. {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD10 */
  81. {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD11 */
  82. {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD12 */
  83. {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD13 */
  84. {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD14 */
  85. {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* AD15 */
  86. #endif
  87. {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* Wait */
  88. {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)}, /* Write Protect */
  89. {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, /* Chip-Select */
  90. {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)}, /* Write Enable */
  91. {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)}, /* Read Enable */
  92. {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)}, /* Addr Latch Enable*/
  93. {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)}, /* Byte Enable */
  94. {-1},
  95. };
  96. #endif
  97. static __maybe_unused struct module_pin_mux qspi_pin_mux[] = {
  98. {OFFSET(gpmc_csn0), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_CS0 */
  99. {OFFSET(gpmc_csn3), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* QSPI_CLK */
  100. {OFFSET(gpmc_advn_ale), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D0 */
  101. {OFFSET(gpmc_oen_ren), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D1 */
  102. {OFFSET(gpmc_wen), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D2 */
  103. {OFFSET(gpmc_be0n_cle), (MODE(3) | PULLUP_EN | RXACTIVE)}, /* QSPI_D3 */
  104. {-1},
  105. };
  106. void enable_uart0_pin_mux(void)
  107. {
  108. configure_module_pin_mux(uart0_pin_mux);
  109. }
  110. void enable_board_pin_mux(void)
  111. {
  112. configure_module_pin_mux(mmc0_pin_mux);
  113. configure_module_pin_mux(i2c0_pin_mux);
  114. configure_module_pin_mux(mdio_pin_mux);
  115. if (board_is_evm()) {
  116. configure_module_pin_mux(gpio5_7_pin_mux);
  117. configure_module_pin_mux(rgmii1_pin_mux);
  118. #if defined(CONFIG_MTD_RAW_NAND)
  119. configure_module_pin_mux(nand_pin_mux);
  120. #endif
  121. } else if (board_is_sk() || board_is_idk()) {
  122. configure_module_pin_mux(rgmii1_pin_mux);
  123. #if defined(CONFIG_MTD_RAW_NAND)
  124. printf("Error: NAND flash not present on this board\n");
  125. #endif
  126. configure_module_pin_mux(qspi_pin_mux);
  127. } else if (board_is_eposevm()) {
  128. configure_module_pin_mux(rmii1_pin_mux);
  129. #if defined(CONFIG_MTD_RAW_NAND)
  130. configure_module_pin_mux(nand_pin_mux);
  131. #else
  132. configure_module_pin_mux(qspi_pin_mux);
  133. #endif
  134. }
  135. }
  136. void enable_i2c0_pin_mux(void)
  137. {
  138. configure_module_pin_mux(i2c0_pin_mux);
  139. }