board.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for TI AM335X based boards
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <env.h>
  12. #include <errno.h>
  13. #include <init.h>
  14. #include <spl.h>
  15. #include <serial.h>
  16. #include <asm/arch/cpu.h>
  17. #include <asm/arch/hardware.h>
  18. #include <asm/arch/omap.h>
  19. #include <asm/arch/ddr_defs.h>
  20. #include <asm/arch/clock.h>
  21. #include <asm/arch/clk_synthesizer.h>
  22. #include <asm/arch/gpio.h>
  23. #include <asm/arch/mmc_host_def.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <asm/arch/mem.h>
  26. #include <asm/io.h>
  27. #include <asm/emif.h>
  28. #include <asm/gpio.h>
  29. #include <asm/omap_common.h>
  30. #include <asm/omap_sec_common.h>
  31. #include <asm/omap_mmc.h>
  32. #include <i2c.h>
  33. #include <miiphy.h>
  34. #include <cpsw.h>
  35. #include <power/tps65217.h>
  36. #include <power/tps65910.h>
  37. #include <env_internal.h>
  38. #include <watchdog.h>
  39. #include "../common/board_detect.h"
  40. #include "board.h"
  41. DECLARE_GLOBAL_DATA_PTR;
  42. /* GPIO that controls power to DDR on EVM-SK */
  43. #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
  44. #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
  45. #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
  46. #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
  47. #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
  48. #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
  49. #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
  50. #define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11)
  51. #define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26)
  52. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  53. #define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
  54. #define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
  55. #define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
  56. #define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
  57. #define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024)
  58. #define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024)
  59. /*
  60. * Read header information from EEPROM into global structure.
  61. */
  62. #ifdef CONFIG_TI_I2C_BOARD_DETECT
  63. void do_board_detect(void)
  64. {
  65. enable_i2c0_pin_mux();
  66. #ifndef CONFIG_DM_I2C
  67. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  68. #endif
  69. if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  70. CONFIG_EEPROM_CHIP_ADDRESS))
  71. printf("ti_i2c_eeprom_init failed\n");
  72. }
  73. #endif
  74. #ifndef CONFIG_DM_SERIAL
  75. struct serial_device *default_serial_console(void)
  76. {
  77. if (board_is_icev2())
  78. return &eserial4_device;
  79. else
  80. return &eserial1_device;
  81. }
  82. #endif
  83. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  84. static const struct ddr_data ddr2_data = {
  85. .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  86. .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  87. .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  88. };
  89. static const struct cmd_control ddr2_cmd_ctrl_data = {
  90. .cmd0csratio = MT47H128M16RT25E_RATIO,
  91. .cmd1csratio = MT47H128M16RT25E_RATIO,
  92. .cmd2csratio = MT47H128M16RT25E_RATIO,
  93. };
  94. static const struct emif_regs ddr2_emif_reg_data = {
  95. .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  96. .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  97. .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  98. .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  99. .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  100. .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  101. };
  102. static const struct emif_regs ddr2_evm_emif_reg_data = {
  103. .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  104. .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  105. .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  106. .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  107. .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  108. .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
  109. .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  110. };
  111. static const struct ddr_data ddr3_data = {
  112. .datardsratio0 = MT41J128MJT125_RD_DQS,
  113. .datawdsratio0 = MT41J128MJT125_WR_DQS,
  114. .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
  115. .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
  116. };
  117. static const struct ddr_data ddr3_beagleblack_data = {
  118. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  119. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  120. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  121. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  122. };
  123. static const struct ddr_data ddr3_evm_data = {
  124. .datardsratio0 = MT41J512M8RH125_RD_DQS,
  125. .datawdsratio0 = MT41J512M8RH125_WR_DQS,
  126. .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
  127. .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
  128. };
  129. static const struct ddr_data ddr3_icev2_data = {
  130. .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
  131. .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
  132. .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
  133. .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
  134. };
  135. static const struct cmd_control ddr3_cmd_ctrl_data = {
  136. .cmd0csratio = MT41J128MJT125_RATIO,
  137. .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
  138. .cmd1csratio = MT41J128MJT125_RATIO,
  139. .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
  140. .cmd2csratio = MT41J128MJT125_RATIO,
  141. .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
  142. };
  143. static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
  144. .cmd0csratio = MT41K256M16HA125E_RATIO,
  145. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  146. .cmd1csratio = MT41K256M16HA125E_RATIO,
  147. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  148. .cmd2csratio = MT41K256M16HA125E_RATIO,
  149. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  150. };
  151. static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
  152. .cmd0csratio = MT41J512M8RH125_RATIO,
  153. .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
  154. .cmd1csratio = MT41J512M8RH125_RATIO,
  155. .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
  156. .cmd2csratio = MT41J512M8RH125_RATIO,
  157. .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
  158. };
  159. static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
  160. .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
  161. .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
  162. .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
  163. .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
  164. .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
  165. .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
  166. };
  167. static struct emif_regs ddr3_emif_reg_data = {
  168. .sdram_config = MT41J128MJT125_EMIF_SDCFG,
  169. .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
  170. .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
  171. .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
  172. .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
  173. .zq_config = MT41J128MJT125_ZQ_CFG,
  174. .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
  175. PHY_EN_DYN_PWRDN,
  176. };
  177. static struct emif_regs ddr3_beagleblack_emif_reg_data = {
  178. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  179. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  180. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  181. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  182. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  183. .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
  184. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  185. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  186. };
  187. static struct emif_regs ddr3_evm_emif_reg_data = {
  188. .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
  189. .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
  190. .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
  191. .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
  192. .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
  193. .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
  194. .zq_config = MT41J512M8RH125_ZQ_CFG,
  195. .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
  196. PHY_EN_DYN_PWRDN,
  197. };
  198. static struct emif_regs ddr3_icev2_emif_reg_data = {
  199. .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
  200. .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
  201. .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
  202. .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
  203. .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
  204. .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
  205. .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
  206. PHY_EN_DYN_PWRDN,
  207. };
  208. #ifdef CONFIG_SPL_OS_BOOT
  209. int spl_start_uboot(void)
  210. {
  211. #ifdef CONFIG_SPL_SERIAL_SUPPORT
  212. /* break into full u-boot on 'c' */
  213. if (serial_tstc() && serial_getc() == 'c')
  214. return 1;
  215. #endif
  216. #ifdef CONFIG_SPL_ENV_SUPPORT
  217. env_init();
  218. env_load();
  219. if (env_get_yesno("boot_os") != 1)
  220. return 1;
  221. #endif
  222. return 0;
  223. }
  224. #endif
  225. const struct dpll_params *get_dpll_ddr_params(void)
  226. {
  227. int ind = get_sys_clk_index();
  228. if (board_is_evm_sk())
  229. return &dpll_ddr3_303MHz[ind];
  230. else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
  231. return &dpll_ddr3_400MHz[ind];
  232. else if (board_is_evm_15_or_later())
  233. return &dpll_ddr3_303MHz[ind];
  234. else
  235. return &dpll_ddr2_266MHz[ind];
  236. }
  237. static u8 bone_not_connected_to_ac_power(void)
  238. {
  239. if (board_is_bone()) {
  240. uchar pmic_status_reg;
  241. if (tps65217_reg_read(TPS65217_STATUS,
  242. &pmic_status_reg))
  243. return 1;
  244. if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
  245. puts("No AC power, switching to default OPP\n");
  246. return 1;
  247. }
  248. }
  249. return 0;
  250. }
  251. const struct dpll_params *get_dpll_mpu_params(void)
  252. {
  253. int ind = get_sys_clk_index();
  254. int freq = am335x_get_efuse_mpu_max_freq(cdev);
  255. if (bone_not_connected_to_ac_power())
  256. freq = MPUPLL_M_600;
  257. if (board_is_pb() || board_is_bone_lt())
  258. freq = MPUPLL_M_1000;
  259. switch (freq) {
  260. case MPUPLL_M_1000:
  261. return &dpll_mpu_opp[ind][5];
  262. case MPUPLL_M_800:
  263. return &dpll_mpu_opp[ind][4];
  264. case MPUPLL_M_720:
  265. return &dpll_mpu_opp[ind][3];
  266. case MPUPLL_M_600:
  267. return &dpll_mpu_opp[ind][2];
  268. case MPUPLL_M_500:
  269. return &dpll_mpu_opp100;
  270. case MPUPLL_M_300:
  271. return &dpll_mpu_opp[ind][0];
  272. }
  273. return &dpll_mpu_opp[ind][0];
  274. }
  275. static void scale_vcores_bone(int freq)
  276. {
  277. int usb_cur_lim, mpu_vdd;
  278. /*
  279. * Only perform PMIC configurations if board rev > A1
  280. * on Beaglebone White
  281. */
  282. if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
  283. return;
  284. #ifndef CONFIG_DM_I2C
  285. if (i2c_probe(TPS65217_CHIP_PM))
  286. return;
  287. #else
  288. if (power_tps65217_init(0))
  289. return;
  290. #endif
  291. /*
  292. * On Beaglebone White we need to ensure we have AC power
  293. * before increasing the frequency.
  294. */
  295. if (bone_not_connected_to_ac_power())
  296. freq = MPUPLL_M_600;
  297. /*
  298. * Override what we have detected since we know if we have
  299. * a Beaglebone Black it supports 1GHz.
  300. */
  301. if (board_is_pb() || board_is_bone_lt())
  302. freq = MPUPLL_M_1000;
  303. switch (freq) {
  304. case MPUPLL_M_1000:
  305. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  306. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  307. break;
  308. case MPUPLL_M_800:
  309. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  310. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  311. break;
  312. case MPUPLL_M_720:
  313. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
  314. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  315. break;
  316. case MPUPLL_M_600:
  317. case MPUPLL_M_500:
  318. case MPUPLL_M_300:
  319. default:
  320. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
  321. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  322. break;
  323. }
  324. if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
  325. TPS65217_POWER_PATH,
  326. usb_cur_lim,
  327. TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  328. puts("tps65217_reg_write failure\n");
  329. /* Set DCDC3 (CORE) voltage to 1.10V */
  330. if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  331. TPS65217_DCDC_VOLT_SEL_1100MV)) {
  332. puts("tps65217_voltage_update failure\n");
  333. return;
  334. }
  335. /* Set DCDC2 (MPU) voltage */
  336. if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  337. puts("tps65217_voltage_update failure\n");
  338. return;
  339. }
  340. /*
  341. * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
  342. * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
  343. */
  344. if (board_is_bone()) {
  345. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  346. TPS65217_DEFLS1,
  347. TPS65217_LDO_VOLTAGE_OUT_3_3,
  348. TPS65217_LDO_MASK))
  349. puts("tps65217_reg_write failure\n");
  350. } else {
  351. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  352. TPS65217_DEFLS1,
  353. TPS65217_LDO_VOLTAGE_OUT_1_8,
  354. TPS65217_LDO_MASK))
  355. puts("tps65217_reg_write failure\n");
  356. }
  357. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  358. TPS65217_DEFLS2,
  359. TPS65217_LDO_VOLTAGE_OUT_3_3,
  360. TPS65217_LDO_MASK))
  361. puts("tps65217_reg_write failure\n");
  362. }
  363. void scale_vcores_generic(int freq)
  364. {
  365. int sil_rev, mpu_vdd;
  366. /*
  367. * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
  368. * MPU frequencies we support we use a CORE voltage of
  369. * 1.10V. For MPU voltage we need to switch based on
  370. * the frequency we are running at.
  371. */
  372. #ifndef CONFIG_DM_I2C
  373. if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
  374. return;
  375. #else
  376. if (power_tps65910_init(0))
  377. return;
  378. #endif
  379. /*
  380. * Depending on MPU clock and PG we will need a different
  381. * VDD to drive at that speed.
  382. */
  383. sil_rev = readl(&cdev->deviceid) >> 28;
  384. mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
  385. /* Tell the TPS65910 to use i2c */
  386. tps65910_set_i2c_control();
  387. /* First update MPU voltage. */
  388. if (tps65910_voltage_update(MPU, mpu_vdd))
  389. return;
  390. /* Second, update the CORE voltage. */
  391. if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
  392. return;
  393. }
  394. void gpi2c_init(void)
  395. {
  396. /* When needed to be invoked prior to BSS initialization */
  397. static bool first_time = true;
  398. if (first_time) {
  399. enable_i2c0_pin_mux();
  400. #ifndef CONFIG_DM_I2C
  401. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
  402. CONFIG_SYS_OMAP24_I2C_SLAVE);
  403. #endif
  404. first_time = false;
  405. }
  406. }
  407. void scale_vcores(void)
  408. {
  409. int freq;
  410. gpi2c_init();
  411. freq = am335x_get_efuse_mpu_max_freq(cdev);
  412. if (board_is_beaglebonex())
  413. scale_vcores_bone(freq);
  414. else
  415. scale_vcores_generic(freq);
  416. }
  417. void set_uart_mux_conf(void)
  418. {
  419. #if CONFIG_CONS_INDEX == 1
  420. enable_uart0_pin_mux();
  421. #elif CONFIG_CONS_INDEX == 2
  422. enable_uart1_pin_mux();
  423. #elif CONFIG_CONS_INDEX == 3
  424. enable_uart2_pin_mux();
  425. #elif CONFIG_CONS_INDEX == 4
  426. enable_uart3_pin_mux();
  427. #elif CONFIG_CONS_INDEX == 5
  428. enable_uart4_pin_mux();
  429. #elif CONFIG_CONS_INDEX == 6
  430. enable_uart5_pin_mux();
  431. #endif
  432. }
  433. void set_mux_conf_regs(void)
  434. {
  435. enable_board_pin_mux();
  436. }
  437. const struct ctrl_ioregs ioregs_evmsk = {
  438. .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
  439. .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
  440. .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
  441. .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
  442. .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
  443. };
  444. const struct ctrl_ioregs ioregs_bonelt = {
  445. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  446. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  447. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  448. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  449. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  450. };
  451. const struct ctrl_ioregs ioregs_evm15 = {
  452. .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  453. .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  454. .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  455. .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  456. .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  457. };
  458. const struct ctrl_ioregs ioregs = {
  459. .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  460. .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  461. .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  462. .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  463. .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  464. };
  465. void sdram_init(void)
  466. {
  467. if (board_is_evm_sk()) {
  468. /*
  469. * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
  470. * This is safe enough to do on older revs.
  471. */
  472. gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
  473. gpio_direction_output(GPIO_DDR_VTT_EN, 1);
  474. }
  475. if (board_is_icev2()) {
  476. gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
  477. gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
  478. }
  479. if (board_is_evm_sk())
  480. config_ddr(303, &ioregs_evmsk, &ddr3_data,
  481. &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  482. else if (board_is_pb() || board_is_bone_lt())
  483. config_ddr(400, &ioregs_bonelt,
  484. &ddr3_beagleblack_data,
  485. &ddr3_beagleblack_cmd_ctrl_data,
  486. &ddr3_beagleblack_emif_reg_data, 0);
  487. else if (board_is_evm_15_or_later())
  488. config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
  489. &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
  490. else if (board_is_icev2())
  491. config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
  492. &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
  493. 0);
  494. else if (board_is_gp_evm())
  495. config_ddr(266, &ioregs, &ddr2_data,
  496. &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
  497. else
  498. config_ddr(266, &ioregs, &ddr2_data,
  499. &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
  500. }
  501. #endif
  502. #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
  503. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
  504. static void request_and_set_gpio(int gpio, char *name, int val)
  505. {
  506. int ret;
  507. ret = gpio_request(gpio, name);
  508. if (ret < 0) {
  509. printf("%s: Unable to request %s\n", __func__, name);
  510. return;
  511. }
  512. ret = gpio_direction_output(gpio, 0);
  513. if (ret < 0) {
  514. printf("%s: Unable to set %s as output\n", __func__, name);
  515. goto err_free_gpio;
  516. }
  517. gpio_set_value(gpio, val);
  518. return;
  519. err_free_gpio:
  520. gpio_free(gpio);
  521. }
  522. #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
  523. #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
  524. /**
  525. * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
  526. * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
  527. * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
  528. * give 50MHz output for Eth0 and 1.
  529. */
  530. static struct clk_synth cdce913_data = {
  531. .id = 0x81,
  532. .capacitor = 0x90,
  533. .mux = 0x6d,
  534. .pdiv2 = 0x2,
  535. .pdiv3 = 0x2,
  536. };
  537. #endif
  538. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
  539. defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
  540. #define MAX_CPSW_SLAVES 2
  541. /* At the moment, we do not want to stop booting for any failures here */
  542. int ft_board_setup(void *fdt, bd_t *bd)
  543. {
  544. const char *slave_path, *enet_name;
  545. int enetnode, slavenode, phynode;
  546. struct udevice *ethdev;
  547. char alias[16];
  548. u32 phy_id[2];
  549. int phy_addr;
  550. int i, ret;
  551. /* phy address fixup needed only on beagle bone family */
  552. if (!board_is_beaglebonex())
  553. goto done;
  554. for (i = 0; i < MAX_CPSW_SLAVES; i++) {
  555. sprintf(alias, "ethernet%d", i);
  556. slave_path = fdt_get_alias(fdt, alias);
  557. if (!slave_path)
  558. continue;
  559. slavenode = fdt_path_offset(fdt, slave_path);
  560. if (slavenode < 0)
  561. continue;
  562. enetnode = fdt_parent_offset(fdt, slavenode);
  563. enet_name = fdt_get_name(fdt, enetnode, NULL);
  564. ethdev = eth_get_dev_by_name(enet_name);
  565. if (!ethdev)
  566. continue;
  567. phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
  568. /* check for phy_id as well as phy-handle properties */
  569. ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
  570. phy_id, 2);
  571. if (ret == 2) {
  572. if (phy_id[1] != phy_addr) {
  573. printf("fixing up phy_id for %s, old: %d, new: %d\n",
  574. alias, phy_id[1], phy_addr);
  575. phy_id[0] = cpu_to_fdt32(phy_id[0]);
  576. phy_id[1] = cpu_to_fdt32(phy_addr);
  577. do_fixup_by_path(fdt, slave_path, "phy_id",
  578. phy_id, sizeof(phy_id), 0);
  579. }
  580. } else {
  581. phynode = fdtdec_lookup_phandle(fdt, slavenode,
  582. "phy-handle");
  583. if (phynode < 0)
  584. continue;
  585. ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
  586. if (ret < 0)
  587. continue;
  588. if (ret != phy_addr) {
  589. printf("fixing up phy-handle for %s, old: %d, new: %d\n",
  590. alias, ret, phy_addr);
  591. fdt_setprop_u32(fdt, phynode, "reg",
  592. cpu_to_fdt32(phy_addr));
  593. }
  594. }
  595. }
  596. done:
  597. return 0;
  598. }
  599. #endif
  600. /*
  601. * Basic board specific setup. Pinmux has been handled already.
  602. */
  603. int board_init(void)
  604. {
  605. #if defined(CONFIG_HW_WATCHDOG)
  606. hw_watchdog_init();
  607. #endif
  608. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  609. #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
  610. gpmc_init();
  611. #endif
  612. #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
  613. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
  614. if (board_is_icev2()) {
  615. int rv;
  616. u32 reg;
  617. REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
  618. /* Make J19 status available on GPIO1_26 */
  619. REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
  620. REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
  621. /*
  622. * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
  623. * jumpers near the port. Read the jumper value and set
  624. * the pinmux, external mux and PHY clock accordingly.
  625. * As jumper line is overridden by PHY RX_DV pin immediately
  626. * after bootstrap (power-up/reset), we need to sample
  627. * it during PHY reset using GPIO rising edge detection.
  628. */
  629. REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
  630. /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
  631. reg = readl(GPIO0_RISINGDETECT) | BIT(11);
  632. writel(reg, GPIO0_RISINGDETECT);
  633. reg = readl(GPIO1_RISINGDETECT) | BIT(26);
  634. writel(reg, GPIO1_RISINGDETECT);
  635. /* Reset PHYs to capture the Jumper setting */
  636. gpio_set_value(GPIO_PHY_RESET, 0);
  637. udelay(2); /* PHY datasheet states 1uS min. */
  638. gpio_set_value(GPIO_PHY_RESET, 1);
  639. reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
  640. if (reg) {
  641. writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
  642. /* RMII mode */
  643. printf("ETH0, CPSW\n");
  644. } else {
  645. /* MII mode */
  646. printf("ETH0, PRU\n");
  647. cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
  648. }
  649. reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
  650. if (reg) {
  651. writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
  652. /* RMII mode */
  653. printf("ETH1, CPSW\n");
  654. gpio_set_value(GPIO_MUX_MII_CTRL, 1);
  655. } else {
  656. /* MII mode */
  657. printf("ETH1, PRU\n");
  658. cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
  659. }
  660. /* disable rising edge IRQs */
  661. reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
  662. writel(reg, GPIO0_RISINGDETECT);
  663. reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
  664. writel(reg, GPIO1_RISINGDETECT);
  665. rv = setup_clock_synthesizer(&cdce913_data);
  666. if (rv) {
  667. printf("Clock synthesizer setup failed %d\n", rv);
  668. return rv;
  669. }
  670. /* reset PHYs */
  671. gpio_set_value(GPIO_PHY_RESET, 0);
  672. udelay(2); /* PHY datasheet states 1uS min. */
  673. gpio_set_value(GPIO_PHY_RESET, 1);
  674. }
  675. #endif
  676. return 0;
  677. }
  678. #ifdef CONFIG_BOARD_LATE_INIT
  679. int board_late_init(void)
  680. {
  681. struct udevice *dev;
  682. #if !defined(CONFIG_SPL_BUILD)
  683. uint8_t mac_addr[6];
  684. uint32_t mac_hi, mac_lo;
  685. #endif
  686. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  687. char *name = NULL;
  688. if (board_is_bone_lt()) {
  689. /* BeagleBoard.org BeagleBone Black Wireless: */
  690. if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
  691. name = "BBBW";
  692. }
  693. /* SeeedStudio BeagleBone Green Wireless */
  694. if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
  695. name = "BBGW";
  696. }
  697. /* BeagleBoard.org BeagleBone Blue */
  698. if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
  699. name = "BBBL";
  700. }
  701. }
  702. if (board_is_bbg1())
  703. name = "BBG1";
  704. if (board_is_bben())
  705. name = "BBEN";
  706. set_board_info_env(name);
  707. /*
  708. * Default FIT boot on HS devices. Non FIT images are not allowed
  709. * on HS devices.
  710. */
  711. if (get_device_type() == HS_DEVICE)
  712. env_set("boot_fit", "1");
  713. #endif
  714. #if !defined(CONFIG_SPL_BUILD)
  715. /* try reading mac address from efuse */
  716. mac_lo = readl(&cdev->macid0l);
  717. mac_hi = readl(&cdev->macid0h);
  718. mac_addr[0] = mac_hi & 0xFF;
  719. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  720. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  721. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  722. mac_addr[4] = mac_lo & 0xFF;
  723. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  724. if (!env_get("ethaddr")) {
  725. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  726. if (is_valid_ethaddr(mac_addr))
  727. eth_env_set_enetaddr("ethaddr", mac_addr);
  728. }
  729. mac_lo = readl(&cdev->macid1l);
  730. mac_hi = readl(&cdev->macid1h);
  731. mac_addr[0] = mac_hi & 0xFF;
  732. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  733. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  734. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  735. mac_addr[4] = mac_lo & 0xFF;
  736. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  737. if (!env_get("eth1addr")) {
  738. if (is_valid_ethaddr(mac_addr))
  739. eth_env_set_enetaddr("eth1addr", mac_addr);
  740. }
  741. #endif
  742. if (!env_get("serial#")) {
  743. char *board_serial = env_get("board_serial");
  744. char *ethaddr = env_get("ethaddr");
  745. if (!board_serial || !strncmp(board_serial, "unknown", 7))
  746. env_set("serial#", ethaddr);
  747. else
  748. env_set("serial#", board_serial);
  749. }
  750. /* Just probe the potentially supported cdce913 device */
  751. uclass_get_device(UCLASS_CLK, 0, &dev);
  752. return 0;
  753. }
  754. #endif
  755. /* CPSW platdata */
  756. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  757. struct cpsw_slave_data slave_data[] = {
  758. {
  759. .slave_reg_ofs = CPSW_SLAVE0_OFFSET,
  760. .sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
  761. .phy_addr = 0,
  762. },
  763. {
  764. .slave_reg_ofs = CPSW_SLAVE1_OFFSET,
  765. .sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
  766. .phy_addr = 1,
  767. },
  768. };
  769. struct cpsw_platform_data am335_eth_data = {
  770. .cpsw_base = CPSW_BASE,
  771. .version = CPSW_CTRL_VERSION_2,
  772. .bd_ram_ofs = CPSW_BD_OFFSET,
  773. .ale_reg_ofs = CPSW_ALE_OFFSET,
  774. .cpdma_reg_ofs = CPSW_CPDMA_OFFSET,
  775. .mdio_div = CPSW_MDIO_DIV,
  776. .host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
  777. .channels = 8,
  778. .slaves = 2,
  779. .slave_data = slave_data,
  780. .ale_entries = 1024,
  781. .bd_ram_ofs = 0x2000,
  782. .mac_control = 0x20,
  783. .active_slave = 0,
  784. .mdio_base = 0x4a101000,
  785. .gmii_sel = 0x44e10650,
  786. .phy_sel_compat = "ti,am3352-cpsw-phy-sel",
  787. .syscon_addr = 0x44e10630,
  788. .macid_sel_compat = "cpsw,am33xx",
  789. };
  790. struct eth_pdata cpsw_pdata = {
  791. .iobase = 0x4a100000,
  792. .phy_interface = 0,
  793. .priv_pdata = &am335_eth_data,
  794. };
  795. U_BOOT_DEVICE(am335x_eth) = {
  796. .name = "eth_cpsw",
  797. .platdata = &cpsw_pdata,
  798. };
  799. #endif
  800. #ifdef CONFIG_SPL_LOAD_FIT
  801. int board_fit_config_name_match(const char *name)
  802. {
  803. if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
  804. return 0;
  805. else if (board_is_bone() && !strcmp(name, "am335x-bone"))
  806. return 0;
  807. else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
  808. return 0;
  809. else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
  810. return 0;
  811. else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
  812. return 0;
  813. else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
  814. return 0;
  815. else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
  816. return 0;
  817. else
  818. return -1;
  819. }
  820. #endif
  821. #ifdef CONFIG_TI_SECURE_DEVICE
  822. void board_fit_image_post_process(void **p_image, size_t *p_size)
  823. {
  824. secure_boot_verify_image(p_image, p_size);
  825. }
  826. #endif
  827. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  828. static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
  829. .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
  830. .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
  831. .cfg.f_min = 400000,
  832. .cfg.f_max = 52000000,
  833. .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
  834. .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  835. };
  836. U_BOOT_DEVICE(am335x_mmc0) = {
  837. .name = "omap_hsmmc",
  838. .platdata = &am335x_mmc0_platdata,
  839. };
  840. static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
  841. .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
  842. .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
  843. .cfg.f_min = 400000,
  844. .cfg.f_max = 52000000,
  845. .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
  846. .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  847. };
  848. U_BOOT_DEVICE(am335x_mmc1) = {
  849. .name = "omap_hsmmc",
  850. .platdata = &am335x_mmc1_platdata,
  851. };
  852. #endif