ci20.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * CI20 setup code
  4. *
  5. * Copyright (c) 2013 Imagination Technologies
  6. * Author: Paul Burton <paul.burton@imgtec.com>
  7. */
  8. #include <common.h>
  9. #include <env.h>
  10. #include <net.h>
  11. #include <netdev.h>
  12. #include <asm/io.h>
  13. #include <asm/gpio.h>
  14. #include <mach/jz4780.h>
  15. #include <mach/jz4780_dram.h>
  16. #include <mach/jz4780_gpio.h>
  17. struct ci20_otp {
  18. u32 serial_number;
  19. u32 date;
  20. u8 manufacturer[2];
  21. u8 mac[6];
  22. } __packed;
  23. static void ci20_mux_mmc(void)
  24. {
  25. void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
  26. /* setup MSC1 pins */
  27. writel(0x30f00000, gpio_regs + GPIO_PXINTC(4));
  28. writel(0x30f00000, gpio_regs + GPIO_PXMASKC(4));
  29. writel(0x30f00000, gpio_regs + GPIO_PXPAT1C(4));
  30. writel(0x30f00000, gpio_regs + GPIO_PXPAT0C(4));
  31. writel(0x30f00000, gpio_regs + GPIO_PXPENC(4));
  32. jz4780_clk_ungate_mmc();
  33. }
  34. #ifndef CONFIG_SPL_BUILD
  35. static void ci20_mux_eth(void)
  36. {
  37. void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
  38. #ifdef CONFIG_MTD_RAW_NAND
  39. /* setup pins (some already setup for NAND) */
  40. writel(0x04030000, gpio_regs + GPIO_PXINTC(0));
  41. writel(0x04030000, gpio_regs + GPIO_PXMASKC(0));
  42. writel(0x04030000, gpio_regs + GPIO_PXPAT1C(0));
  43. writel(0x04030000, gpio_regs + GPIO_PXPAT0C(0));
  44. writel(0x04030000, gpio_regs + GPIO_PXPENS(0));
  45. #else
  46. /* setup pins (as above +NAND CS +RD/WE +SDx +SAx) */
  47. writel(0x0dff00ff, gpio_regs + GPIO_PXINTC(0));
  48. writel(0x0dff00ff, gpio_regs + GPIO_PXMASKC(0));
  49. writel(0x0dff00ff, gpio_regs + GPIO_PXPAT1C(0));
  50. writel(0x0dff00ff, gpio_regs + GPIO_PXPAT0C(0));
  51. writel(0x0dff00ff, gpio_regs + GPIO_PXPENS(0));
  52. writel(0x00000003, gpio_regs + GPIO_PXINTC(1));
  53. writel(0x00000003, gpio_regs + GPIO_PXMASKC(1));
  54. writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1));
  55. writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1));
  56. writel(0x00000003, gpio_regs + GPIO_PXPENS(1));
  57. #endif
  58. }
  59. static void ci20_mux_jtag(void)
  60. {
  61. #ifdef CONFIG_JTAG
  62. void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
  63. /* enable JTAG */
  64. writel(3 << 30, gpio_regs + GPIO_PXINTC(0));
  65. writel(3 << 30, gpio_regs + GPIO_PXMASKC(0));
  66. writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0));
  67. writel(3 << 30, gpio_regs + GPIO_PXPAT0C(0));
  68. #endif
  69. }
  70. static void ci20_mux_nand(void)
  71. {
  72. void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
  73. /* setup pins */
  74. writel(0x002c00ff, gpio_regs + GPIO_PXINTC(0));
  75. writel(0x002c00ff, gpio_regs + GPIO_PXMASKC(0));
  76. writel(0x002c00ff, gpio_regs + GPIO_PXPAT1C(0));
  77. writel(0x002c00ff, gpio_regs + GPIO_PXPAT0C(0));
  78. writel(0x002c00ff, gpio_regs + GPIO_PXPENS(0));
  79. writel(0x00000003, gpio_regs + GPIO_PXINTC(1));
  80. writel(0x00000003, gpio_regs + GPIO_PXMASKC(1));
  81. writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1));
  82. writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1));
  83. writel(0x00000003, gpio_regs + GPIO_PXPENS(1));
  84. /* FRB0_N */
  85. jz47xx_gpio_direction_input(JZ_GPIO(0, 20));
  86. writel(20, gpio_regs + GPIO_PXPENS(0));
  87. /* disable write protect */
  88. jz47xx_gpio_direction_output(JZ_GPIO(5, 22), 1);
  89. }
  90. static void ci20_mux_uart(void)
  91. {
  92. void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
  93. /* UART0 */
  94. writel(0x9, gpio_regs + GPIO_PXINTC(5));
  95. writel(0x9, gpio_regs + GPIO_PXMASKC(5));
  96. writel(0x9, gpio_regs + GPIO_PXPAT1C(5));
  97. writel(0x9, gpio_regs + GPIO_PXPAT0C(5));
  98. writel(0x9, gpio_regs + GPIO_PXPENC(5));
  99. jz4780_clk_ungate_uart(0);
  100. /* UART 1 and 2 */
  101. jz4780_clk_ungate_uart(1);
  102. jz4780_clk_ungate_uart(2);
  103. #ifndef CONFIG_JTAG
  104. /* UART3 */
  105. writel(1 << 12, gpio_regs + GPIO_PXINTC(3));
  106. writel(1 << 12, gpio_regs + GPIO_PXMASKS(3));
  107. writel(1 << 12, gpio_regs + GPIO_PXPAT1S(3));
  108. writel(1 << 12, gpio_regs + GPIO_PXPAT0C(3));
  109. writel(3 << 30, gpio_regs + GPIO_PXINTC(0));
  110. writel(3 << 30, gpio_regs + GPIO_PXMASKC(0));
  111. writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0));
  112. writel(1 << 30, gpio_regs + GPIO_PXPAT0C(0));
  113. writel(1 << 31, gpio_regs + GPIO_PXPAT0S(0));
  114. jz4780_clk_ungate_uart(3);
  115. #endif
  116. /* UART4 */
  117. writel(0x100400, gpio_regs + GPIO_PXINTC(2));
  118. writel(0x100400, gpio_regs + GPIO_PXMASKC(2));
  119. writel(0x100400, gpio_regs + GPIO_PXPAT1S(2));
  120. writel(0x100400, gpio_regs + GPIO_PXPAT0C(2));
  121. writel(0x100400, gpio_regs + GPIO_PXPENC(2));
  122. jz4780_clk_ungate_uart(4);
  123. }
  124. int board_early_init_f(void)
  125. {
  126. ci20_mux_jtag();
  127. ci20_mux_uart();
  128. ci20_mux_eth();
  129. ci20_mux_mmc();
  130. ci20_mux_nand();
  131. /* SYS_POWER_IND high (LED blue, VBUS off) */
  132. jz47xx_gpio_direction_output(JZ_GPIO(5, 15), 0);
  133. /* LEDs off */
  134. jz47xx_gpio_direction_output(JZ_GPIO(2, 0), 0);
  135. jz47xx_gpio_direction_output(JZ_GPIO(2, 1), 0);
  136. jz47xx_gpio_direction_output(JZ_GPIO(2, 2), 0);
  137. jz47xx_gpio_direction_output(JZ_GPIO(2, 3), 0);
  138. return 0;
  139. }
  140. int misc_init_r(void)
  141. {
  142. const u32 efuse_clk = jz4780_clk_get_efuse_clk();
  143. struct ci20_otp otp;
  144. char manufacturer[3];
  145. /* Read the board OTP data */
  146. jz4780_efuse_init(efuse_clk);
  147. jz4780_efuse_read(0x18, 16, (u8 *)&otp);
  148. /* Set MAC address */
  149. if (!is_valid_ethaddr(otp.mac)) {
  150. /* no MAC assigned, generate one from the unique chip ID */
  151. jz4780_efuse_read(0x8, 4, &otp.mac[0]);
  152. jz4780_efuse_read(0x12, 2, &otp.mac[4]);
  153. otp.mac[0] = (otp.mac[0] | 0x02) & ~0x01;
  154. }
  155. eth_env_set_enetaddr("ethaddr", otp.mac);
  156. /* Put other board information into the environment */
  157. env_set_ulong("serial#", otp.serial_number);
  158. env_set_ulong("board_date", otp.date);
  159. manufacturer[0] = otp.manufacturer[0];
  160. manufacturer[1] = otp.manufacturer[1];
  161. manufacturer[2] = 0;
  162. env_set("board_mfr", manufacturer);
  163. return 0;
  164. }
  165. #ifdef CONFIG_DRIVER_DM9000
  166. int board_eth_init(bd_t *bis)
  167. {
  168. /* Enable clock */
  169. jz4780_clk_ungate_ethernet();
  170. /* Enable power (PB25) */
  171. jz47xx_gpio_direction_output(JZ_GPIO(1, 25), 1);
  172. /* Reset (PF12) */
  173. mdelay(10);
  174. jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 0);
  175. mdelay(10);
  176. jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 1);
  177. mdelay(10);
  178. return dm9000_initialize(bis);
  179. }
  180. #endif /* CONFIG_DRIVER_DM9000 */
  181. #endif
  182. static u8 ci20_revision(void)
  183. {
  184. void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
  185. int val;
  186. jz47xx_gpio_direction_input(JZ_GPIO(2, 18));
  187. jz47xx_gpio_direction_input(JZ_GPIO(2, 19));
  188. /* Enable pullups */
  189. writel(BIT(18) | BIT(19), gpio_regs + GPIO_PXPENC(2));
  190. /* Read PC18/19 for version */
  191. val = (!!jz47xx_gpio_get_value(JZ_GPIO(2, 18))) |
  192. ((!!jz47xx_gpio_get_value(JZ_GPIO(2, 19))) << 1);
  193. if (val == 3) /* Rev 1 boards had no pulldowns - giving 3 */
  194. return 1;
  195. if (val == 1) /* Rev 2 boards pulldown port C bit 18 giving 1 */
  196. return 2;
  197. return 0;
  198. }
  199. int dram_init(void)
  200. {
  201. gd->ram_size = sdram_size(0) + sdram_size(1);
  202. return 0;
  203. }
  204. /* U-Boot common routines */
  205. int checkboard(void)
  206. {
  207. printf("Board: Creator CI20 (rev.%d)\n", ci20_revision());
  208. return 0;
  209. }
  210. #ifdef CONFIG_SPL_BUILD
  211. #if defined(CONFIG_SPL_MMC_SUPPORT)
  212. int board_mmc_init(bd_t *bd)
  213. {
  214. ci20_mux_mmc();
  215. return jz_mmc_init((void __iomem *)MSC0_BASE);
  216. }
  217. #endif
  218. static const struct jz4780_ddr_config K4B2G0846Q_48_config = {
  219. .timing = {
  220. (4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) |
  221. (6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT),
  222. (4 << DDRC_TIMING2_TCCD_BIT) | (15 << DDRC_TIMING2_TRAS_BIT) |
  223. (6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT),
  224. (4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) |
  225. (6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) |
  226. (21 << DDRC_TIMING3_TRC_BIT),
  227. (31 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) |
  228. (4 << DDRC_TIMING4_TCKE_BIT) | (9 << DDRC_TIMING4_TMINSR_BIT) |
  229. (8 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT),
  230. (8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) |
  231. (4 << DDRC_TIMING5_TWDLAT_BIT),
  232. (25 << DDRC_TIMING6_TXSRD_BIT) | (12 << DDRC_TIMING6_TFAW_BIT) |
  233. (2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT),
  234. },
  235. /* PHY */
  236. /* Mode Register 0 */
  237. .mr0 = 0x420,
  238. #ifdef SDRAM_DISABLE_DLL
  239. .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
  240. #else
  241. .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
  242. #endif
  243. .ptr0 = 0x002000d4,
  244. .ptr1 = 0x02230d40,
  245. .ptr2 = 0x04013880,
  246. .dtpr0 = 0x2a8f6690,
  247. .dtpr1 = 0x00400860,
  248. .dtpr2 = 0x10042a00,
  249. .pullup = 0x0b,
  250. .pulldn = 0x0b,
  251. };
  252. static const struct jz4780_ddr_config H5TQ2G83CFR_48_config = {
  253. .timing = {
  254. (4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) |
  255. (6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT),
  256. (4 << DDRC_TIMING2_TCCD_BIT) | (16 << DDRC_TIMING2_TRAS_BIT) |
  257. (6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT),
  258. (4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) |
  259. (6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) |
  260. (22 << DDRC_TIMING3_TRC_BIT),
  261. (42 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) |
  262. (4 << DDRC_TIMING4_TCKE_BIT) | (7 << DDRC_TIMING4_TMINSR_BIT) |
  263. (3 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT),
  264. (8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) |
  265. (4 << DDRC_TIMING5_TWDLAT_BIT),
  266. (25 << DDRC_TIMING6_TXSRD_BIT) | (20 << DDRC_TIMING6_TFAW_BIT) |
  267. (2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT),
  268. },
  269. /* PHY */
  270. /* Mode Register 0 */
  271. .mr0 = 0x420,
  272. #ifdef SDRAM_DISABLE_DLL
  273. .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
  274. #else
  275. .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
  276. #endif
  277. .ptr0 = 0x002000d4,
  278. .ptr1 = 0x02d30d40,
  279. .ptr2 = 0x04013880,
  280. .dtpr0 = 0x2c906690,
  281. .dtpr1 = 0x005608a0,
  282. .dtpr2 = 0x10042a00,
  283. .pullup = 0x0e,
  284. .pulldn = 0x0e,
  285. };
  286. #if (CONFIG_SYS_MHZ != 1200)
  287. #error No DDR configuration for CPU speed
  288. #endif
  289. const struct jz4780_ddr_config *jz4780_get_ddr_config(void)
  290. {
  291. const int board_revision = ci20_revision();
  292. if (board_revision == 2)
  293. return &K4B2G0846Q_48_config;
  294. else /* Fall back to H5TQ2G83CFR RAM */
  295. return &H5TQ2G83CFR_48_config;
  296. }
  297. #endif