ls2080aqds.c 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Freescale Semiconductor
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <malloc.h>
  8. #include <errno.h>
  9. #include <netdev.h>
  10. #include <fsl_ifc.h>
  11. #include <fsl_ddr.h>
  12. #include <asm/io.h>
  13. #include <fdt_support.h>
  14. #include <linux/libfdt.h>
  15. #include <fsl-mc/fsl_mc.h>
  16. #include <env_internal.h>
  17. #include <i2c.h>
  18. #include <rtc.h>
  19. #include <asm/arch/soc.h>
  20. #include <hwconfig.h>
  21. #include <fsl_sec.h>
  22. #include <asm/arch/ppa.h>
  23. #include <asm/arch-fsl-layerscape/fsl_icid.h>
  24. #include "../common/qixis.h"
  25. #include "ls2080aqds_qixis.h"
  26. #include "../common/vid.h"
  27. #define PIN_MUX_SEL_SDHC 0x00
  28. #define PIN_MUX_SEL_DSPI 0x0a
  29. #define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
  30. #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
  31. DECLARE_GLOBAL_DATA_PTR;
  32. enum {
  33. MUX_TYPE_SDHC,
  34. MUX_TYPE_DSPI,
  35. };
  36. unsigned long long get_qixis_addr(void)
  37. {
  38. unsigned long long addr;
  39. if (gd->flags & GD_FLG_RELOC)
  40. addr = QIXIS_BASE_PHYS;
  41. else
  42. addr = QIXIS_BASE_PHYS_EARLY;
  43. /*
  44. * IFC address under 256MB is mapped to 0x30000000, any address above
  45. * is mapped to 0x5_10000000 up to 4GB.
  46. */
  47. addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
  48. return addr;
  49. }
  50. int checkboard(void)
  51. {
  52. char buf[64];
  53. u8 sw;
  54. static const char *const freq[] = {"100", "125", "156.25",
  55. "100 separate SSCG"};
  56. int clock;
  57. cpu_name(buf);
  58. printf("Board: %s-QDS, ", buf);
  59. sw = QIXIS_READ(arch);
  60. printf("Board Arch: V%d, ", sw >> 4);
  61. printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  62. memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
  63. sw = QIXIS_READ(brdcfg[0]);
  64. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  65. if (sw < 0x8)
  66. printf("vBank: %d\n", sw);
  67. else if (sw == 0x8)
  68. puts("PromJet\n");
  69. else if (sw == 0x9)
  70. puts("NAND\n");
  71. else if (sw == 0xf)
  72. puts("QSPI\n");
  73. else if (sw == 0x15)
  74. printf("IFCCard\n");
  75. else
  76. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  77. printf("FPGA: v%d (%s), build %d",
  78. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  79. (int)qixis_read_minor());
  80. /* the timestamp string contains "\n" at the end */
  81. printf(" on %s", qixis_read_time(buf));
  82. /*
  83. * Display the actual SERDES reference clocks as configured by the
  84. * dip switches on the board. Note that the SWx registers could
  85. * technically be set to force the reference clocks to match the
  86. * values that the SERDES expects (or vice versa). For now, however,
  87. * we just display both values and hope the user notices when they
  88. * don't match.
  89. */
  90. puts("SERDES1 Reference : ");
  91. sw = QIXIS_READ(brdcfg[2]);
  92. clock = (sw >> 6) & 3;
  93. printf("Clock1 = %sMHz ", freq[clock]);
  94. clock = (sw >> 4) & 3;
  95. printf("Clock2 = %sMHz", freq[clock]);
  96. puts("\nSERDES2 Reference : ");
  97. clock = (sw >> 2) & 3;
  98. printf("Clock1 = %sMHz ", freq[clock]);
  99. clock = (sw >> 0) & 3;
  100. printf("Clock2 = %sMHz\n", freq[clock]);
  101. return 0;
  102. }
  103. unsigned long get_board_sys_clk(void)
  104. {
  105. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  106. switch (sysclk_conf & 0x0F) {
  107. case QIXIS_SYSCLK_83:
  108. return 83333333;
  109. case QIXIS_SYSCLK_100:
  110. return 100000000;
  111. case QIXIS_SYSCLK_125:
  112. return 125000000;
  113. case QIXIS_SYSCLK_133:
  114. return 133333333;
  115. case QIXIS_SYSCLK_150:
  116. return 150000000;
  117. case QIXIS_SYSCLK_160:
  118. return 160000000;
  119. case QIXIS_SYSCLK_166:
  120. return 166666666;
  121. }
  122. return 66666666;
  123. }
  124. unsigned long get_board_ddr_clk(void)
  125. {
  126. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  127. switch ((ddrclk_conf & 0x30) >> 4) {
  128. case QIXIS_DDRCLK_100:
  129. return 100000000;
  130. case QIXIS_DDRCLK_125:
  131. return 125000000;
  132. case QIXIS_DDRCLK_133:
  133. return 133333333;
  134. }
  135. return 66666666;
  136. }
  137. int select_i2c_ch_pca9547(u8 ch)
  138. {
  139. int ret;
  140. #ifdef CONFIG_DM_I2C
  141. struct udevice *dev;
  142. ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  143. if (!ret)
  144. ret = dm_i2c_write(dev, 0, &ch, 1);
  145. #else
  146. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  147. #endif
  148. if (ret) {
  149. puts("PCA: failed to select proper channel\n");
  150. return ret;
  151. }
  152. return 0;
  153. }
  154. int config_board_mux(int ctrl_type)
  155. {
  156. u8 reg5;
  157. reg5 = QIXIS_READ(brdcfg[5]);
  158. switch (ctrl_type) {
  159. case MUX_TYPE_SDHC:
  160. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
  161. break;
  162. case MUX_TYPE_DSPI:
  163. reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
  164. break;
  165. default:
  166. printf("Wrong mux interface type\n");
  167. return -1;
  168. }
  169. QIXIS_WRITE(brdcfg[5], reg5);
  170. return 0;
  171. }
  172. int board_init(void)
  173. {
  174. char *env_hwconfig;
  175. u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
  176. u32 val;
  177. init_final_memctl_regs();
  178. val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
  179. env_hwconfig = env_get("hwconfig");
  180. if (hwconfig_f("dspi", env_hwconfig) &&
  181. DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
  182. config_board_mux(MUX_TYPE_DSPI);
  183. else
  184. config_board_mux(MUX_TYPE_SDHC);
  185. #if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI)
  186. val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
  187. if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
  188. QIXIS_WRITE(brdcfg[9],
  189. (QIXIS_READ(brdcfg[9]) & 0xf8) |
  190. FSL_QIXIS_BRDCFG9_QSPI);
  191. #endif
  192. #ifdef CONFIG_ENV_IS_NOWHERE
  193. gd->env_addr = (ulong)&default_environment[0];
  194. #endif
  195. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  196. #ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
  197. #ifdef CONFIG_DM_I2C
  198. rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
  199. #else
  200. rtc_enable_32khz_output();
  201. #endif
  202. #endif
  203. #ifdef CONFIG_FSL_CAAM
  204. sec_init();
  205. #endif
  206. #ifdef CONFIG_FSL_LS_PPA
  207. ppa_init();
  208. #endif
  209. return 0;
  210. }
  211. int board_early_init_f(void)
  212. {
  213. #ifdef CONFIG_SYS_I2C_EARLY_INIT
  214. i2c_early_init_f();
  215. #endif
  216. fsl_lsch3_early_init_f();
  217. #ifdef CONFIG_FSL_QSPI
  218. /* input clk: 1/2 platform clk, output: input/20 */
  219. out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
  220. #endif
  221. return 0;
  222. }
  223. int misc_init_r(void)
  224. {
  225. if (adjust_vdd(0))
  226. printf("Warning: Adjusting core voltage failed.\n");
  227. return 0;
  228. }
  229. void detail_board_ddr_info(void)
  230. {
  231. puts("\nDDR ");
  232. print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
  233. print_ddr_info(0);
  234. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  235. if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
  236. puts("\nDP-DDR ");
  237. print_size(gd->bd->bi_dram[2].size, "");
  238. print_ddr_info(CONFIG_DP_DDR_CTRL);
  239. }
  240. #endif
  241. }
  242. #if defined(CONFIG_ARCH_MISC_INIT)
  243. int arch_misc_init(void)
  244. {
  245. return 0;
  246. }
  247. #endif
  248. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  249. void fdt_fixup_board_enet(void *fdt)
  250. {
  251. int offset;
  252. offset = fdt_path_offset(fdt, "/soc/fsl-mc");
  253. if (offset < 0)
  254. offset = fdt_path_offset(fdt, "/fsl-mc");
  255. if (offset < 0) {
  256. printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
  257. __func__, offset);
  258. return;
  259. }
  260. if (get_mc_boot_status() == 0 &&
  261. (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
  262. fdt_status_okay(fdt, offset);
  263. else
  264. fdt_status_fail(fdt, offset);
  265. }
  266. void board_quiesce_devices(void)
  267. {
  268. fsl_mc_ldpaa_exit(gd->bd);
  269. }
  270. #endif
  271. #ifdef CONFIG_OF_BOARD_SETUP
  272. int ft_board_setup(void *blob, bd_t *bd)
  273. {
  274. u64 base[CONFIG_NR_DRAM_BANKS];
  275. u64 size[CONFIG_NR_DRAM_BANKS];
  276. ft_cpu_setup(blob, bd);
  277. /* fixup DT for the two GPP DDR banks */
  278. base[0] = gd->bd->bi_dram[0].start;
  279. size[0] = gd->bd->bi_dram[0].size;
  280. base[1] = gd->bd->bi_dram[1].start;
  281. size[1] = gd->bd->bi_dram[1].size;
  282. #ifdef CONFIG_RESV_RAM
  283. /* reduce size if reserved memory is within this bank */
  284. if (gd->arch.resv_ram >= base[0] &&
  285. gd->arch.resv_ram < base[0] + size[0])
  286. size[0] = gd->arch.resv_ram - base[0];
  287. else if (gd->arch.resv_ram >= base[1] &&
  288. gd->arch.resv_ram < base[1] + size[1])
  289. size[1] = gd->arch.resv_ram - base[1];
  290. #endif
  291. fdt_fixup_memory_banks(blob, base, size, 2);
  292. fdt_fsl_mc_fixup_iommu_map_entry(blob);
  293. fsl_fdt_fixup_dr_usb(blob, bd);
  294. #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
  295. fdt_fixup_board_enet(blob);
  296. #endif
  297. fdt_fixup_icid(blob);
  298. return 0;
  299. }
  300. #endif
  301. void qixis_dump_switch(void)
  302. {
  303. int i, nr_of_cfgsw;
  304. QIXIS_WRITE(cms[0], 0x00);
  305. nr_of_cfgsw = QIXIS_READ(cms[1]);
  306. puts("DIP switch settings dump:\n");
  307. for (i = 1; i <= nr_of_cfgsw; i++) {
  308. QIXIS_WRITE(cms[0], i);
  309. printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
  310. }
  311. }