mux.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * mux.c
  4. *
  5. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  6. * Copyright (C) 2018 Robert Bosch Power Tools GmbH
  7. */
  8. #include <common.h>
  9. #include <i2c.h>
  10. #include <asm/arch/hardware.h>
  11. #include <asm/arch/mux.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/io.h>
  14. #include "board.h"
  15. static struct module_pin_mux uart0_pin_mux[] = {
  16. {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
  17. {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
  18. {-1},
  19. };
  20. static struct module_pin_mux i2c0_pin_mux[] = {
  21. {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  22. {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  23. {-1},
  24. };
  25. static struct module_pin_mux guardian_interfaces_pin_mux[] = {
  26. {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLDOWN_EN)},
  27. {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUP_EN)},
  28. {OFFSET(mii1_txd0), (MODE(7) | PULLUP_EN)},
  29. {OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)},
  30. {OFFSET(uart1_txd), (MODE(7) | PULLUDDIS)},
  31. {OFFSET(mii1_crs), (MODE(7) | PULLDOWN_EN)},
  32. {OFFSET(rmii1_refclk), (MODE(7) | PULLDOWN_EN)},
  33. {OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},
  34. {OFFSET(mii1_rxdv), (MODE(7) | PULLDOWN_EN)},
  35. {-1},
  36. };
  37. #ifdef CONFIG_MTD_RAW_NAND
  38. static struct module_pin_mux nand_pin_mux[] = {
  39. {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)},
  40. {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)},
  41. {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)},
  42. {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)},
  43. {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)},
  44. {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)},
  45. {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)},
  46. {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)},
  47. #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
  48. {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)},
  49. {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)},
  50. {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)},
  51. {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)},
  52. {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)},
  53. {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)},
  54. {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)},
  55. {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)},
  56. #endif
  57. {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)},
  58. {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)},
  59. {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)},
  60. {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)},
  61. {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)},
  62. {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)},
  63. {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)},
  64. {-1},
  65. };
  66. #endif
  67. void enable_uart0_pin_mux(void)
  68. {
  69. configure_module_pin_mux(uart0_pin_mux);
  70. }
  71. void enable_i2c0_pin_mux(void)
  72. {
  73. configure_module_pin_mux(i2c0_pin_mux);
  74. }
  75. void enable_board_pin_mux(void)
  76. {
  77. #ifdef CONFIG_MTD_RAW_NAND
  78. configure_module_pin_mux(nand_pin_mux);
  79. #endif
  80. configure_module_pin_mux(guardian_interfaces_pin_mux);
  81. }