board.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for Birdland Audio BAV335x Network Processor
  6. *
  7. * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <errno.h>
  12. #include <init.h>
  13. #include <serial.h>
  14. #include <spl.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/omap.h>
  18. #include <asm/arch/ddr_defs.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/gpio.h>
  21. #include <asm/arch/mmc_host_def.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/arch/mem.h>
  24. #include <asm/io.h>
  25. #include <asm/emif.h>
  26. #include <asm/gpio.h>
  27. #include <i2c.h>
  28. #include <miiphy.h>
  29. #include <cpsw.h>
  30. #include <power/tps65217.h>
  31. #include <power/tps65910.h>
  32. #include <env_internal.h>
  33. #include <watchdog.h>
  34. #include "board.h"
  35. DECLARE_GLOBAL_DATA_PTR;
  36. /* GPIO that controls power to DDR on EVM-SK */
  37. #define GPIO_DDR_VTT_EN 7
  38. static __maybe_unused struct ctrl_dev *cdev =
  39. (struct ctrl_dev *)CTRL_DEVICE_BASE;
  40. /*
  41. * Read header information from EEPROM into global structure.
  42. */
  43. static int read_eeprom(struct board_eeconfig *header)
  44. {
  45. /* Check if baseboard eeprom is available */
  46. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR))
  47. return -ENODEV;
  48. /* read the eeprom using i2c */
  49. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
  50. sizeof(struct board_eeconfig)))
  51. return -EIO;
  52. if (header->magic != BOARD_MAGIC) {
  53. /* read the i2c eeprom again using only a 1 byte address */
  54. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  55. sizeof(struct board_eeconfig)))
  56. return -EIO;
  57. if (header->magic != BOARD_MAGIC)
  58. return -EINVAL;
  59. }
  60. return 0;
  61. }
  62. enum board_type get_board_type(bool debug)
  63. {
  64. int ecode;
  65. struct board_eeconfig header;
  66. ecode = read_eeprom(&header);
  67. if (ecode == 0) {
  68. if (header.version[1] == 'A') {
  69. if (debug)
  70. puts("=== Detected Board model BAV335x Rev.A");
  71. return BAV335A;
  72. } else if (header.version[1] == 'B') {
  73. if (debug)
  74. puts("=== Detected Board model BAV335x Rev.B");
  75. return BAV335B;
  76. } else if (debug) {
  77. puts("### Un-known board model in serial-EE\n");
  78. }
  79. } else if (debug) {
  80. switch (ecode) {
  81. case -ENODEV:
  82. puts("### Board doesn't have a serial-EE\n");
  83. break;
  84. case -EINVAL:
  85. puts("### Board serial-EE signature is incorrect.\n");
  86. break;
  87. default:
  88. puts("### IO Error reading serial-EE.\n");
  89. break;
  90. }
  91. }
  92. #if (CONFIG_BAV_VERSION == 1)
  93. if (debug)
  94. puts("### Selecting BAV335A as per config\n");
  95. return BAV335A;
  96. #elif (CONFIG_BAV_VERSION == 2)
  97. if (debug)
  98. puts("### Selecting BAV335B as per config\n");
  99. return BAV335B;
  100. #endif
  101. #if (NOT_DEFINED == 2)
  102. #error "SHOULD NEVER DISPLAY THIS"
  103. #endif
  104. if (debug)
  105. puts("### Defaulting to model BAV335x Rev.B\n");
  106. return BAV335B;
  107. }
  108. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  109. static const struct ddr_data ddr3_bav335x_data = {
  110. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  111. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  112. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  113. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  114. };
  115. static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = {
  116. .cmd0csratio = MT41K256M16HA125E_RATIO,
  117. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  118. .cmd1csratio = MT41K256M16HA125E_RATIO,
  119. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  120. .cmd2csratio = MT41K256M16HA125E_RATIO,
  121. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  122. };
  123. static struct emif_regs ddr3_bav335x_emif_reg_data = {
  124. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  125. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  126. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  127. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  128. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  129. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  130. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  131. };
  132. #ifdef CONFIG_SPL_OS_BOOT
  133. int spl_start_uboot(void)
  134. {
  135. /* break into full u-boot on 'c' */
  136. if (serial_tstc() && serial_getc() == 'c')
  137. return 1;
  138. #ifdef CONFIG_SPL_ENV_SUPPORT
  139. env_init();
  140. env_load();
  141. if (env_get_yesno("boot_os") != 1)
  142. return 1;
  143. #endif
  144. return 0;
  145. }
  146. #endif
  147. #define OSC (V_OSCK/1000000)
  148. const struct dpll_params dpll_ddr = {
  149. 266, OSC-1, 1, -1, -1, -1, -1};
  150. const struct dpll_params dpll_ddr_evm_sk = {
  151. 303, OSC-1, 1, -1, -1, -1, -1};
  152. const struct dpll_params dpll_ddr_bone_black = {
  153. 400, OSC-1, 1, -1, -1, -1, -1};
  154. void am33xx_spl_board_init(void)
  155. {
  156. /* debug print detect status */
  157. (void)get_board_type(true);
  158. /* Get the frequency */
  159. /* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */
  160. dpll_mpu_opp100.m = MPUPLL_M_1000;
  161. if (i2c_probe(TPS65217_CHIP_PM))
  162. return;
  163. /* Set the USB Current Limit */
  164. if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
  165. TPS65217_USB_INPUT_CUR_LIMIT_1800MA,
  166. TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  167. puts("! tps65217_reg_write: could not set USB limit\n");
  168. /* Set the Core Voltage (DCDC3) to 1.125V */
  169. if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  170. TPS65217_DCDC_VOLT_SEL_1125MV)) {
  171. puts("! tps65217_reg_write: could not set Core Voltage\n");
  172. return;
  173. }
  174. /* Set CORE Frequencies to OPP100 */
  175. do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  176. /* Set the MPU Voltage (DCDC2) */
  177. if (tps65217_voltage_update(TPS65217_DEFDCDC2,
  178. TPS65217_DCDC_VOLT_SEL_1325MV)) {
  179. puts("! tps65217_reg_write: could not set MPU Voltage\n");
  180. return;
  181. }
  182. /*
  183. * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
  184. * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
  185. */
  186. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1,
  187. TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK))
  188. puts("! tps65217_reg_write: could not set LDO3\n");
  189. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2,
  190. TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK))
  191. puts("! tps65217_reg_write: could not set LDO4\n");
  192. /* Set MPU Frequency to what we detected now that voltages are set */
  193. do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  194. }
  195. const struct dpll_params *get_dpll_ddr_params(void)
  196. {
  197. enable_i2c0_pin_mux();
  198. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  199. return &dpll_ddr_bone_black;
  200. }
  201. void set_uart_mux_conf(void)
  202. {
  203. #if CONFIG_CONS_INDEX == 1
  204. enable_uart0_pin_mux();
  205. #elif CONFIG_CONS_INDEX == 2
  206. enable_uart1_pin_mux();
  207. #elif CONFIG_CONS_INDEX == 3
  208. enable_uart2_pin_mux();
  209. #elif CONFIG_CONS_INDEX == 4
  210. enable_uart3_pin_mux();
  211. #elif CONFIG_CONS_INDEX == 5
  212. enable_uart4_pin_mux();
  213. #elif CONFIG_CONS_INDEX == 6
  214. enable_uart5_pin_mux();
  215. #endif
  216. }
  217. void set_mux_conf_regs(void)
  218. {
  219. enum board_type board;
  220. board = get_board_type(false);
  221. enable_board_pin_mux(board);
  222. }
  223. const struct ctrl_ioregs ioregs_bonelt = {
  224. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  225. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  226. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  227. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  228. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  229. };
  230. void sdram_init(void)
  231. {
  232. config_ddr(400, &ioregs_bonelt,
  233. &ddr3_bav335x_data,
  234. &ddr3_bav335x_cmd_ctrl_data,
  235. &ddr3_bav335x_emif_reg_data, 0);
  236. }
  237. #endif
  238. /*
  239. * Basic board specific setup. Pinmux has been handled already.
  240. */
  241. int board_init(void)
  242. {
  243. #if defined(CONFIG_HW_WATCHDOG)
  244. hw_watchdog_init();
  245. #endif
  246. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  247. #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
  248. gpmc_init();
  249. #endif
  250. return 0;
  251. }
  252. #ifdef CONFIG_BOARD_LATE_INIT
  253. int board_late_init(void)
  254. {
  255. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  256. env_set("board_name", "BAV335xB");
  257. env_set("board_rev", "B"); /* Fix me, but why bother.. */
  258. #endif
  259. return 0;
  260. }
  261. #endif
  262. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  263. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  264. static void cpsw_control(int enabled)
  265. {
  266. /* VTP can be added here */
  267. return;
  268. }
  269. static struct cpsw_slave_data cpsw_slaves[] = {
  270. {
  271. .slave_reg_ofs = 0x208,
  272. .sliver_reg_ofs = 0xd80,
  273. .phy_addr = 0,
  274. },
  275. {
  276. .slave_reg_ofs = 0x308,
  277. .sliver_reg_ofs = 0xdc0,
  278. .phy_addr = 1,
  279. },
  280. };
  281. static struct cpsw_platform_data cpsw_data = {
  282. .mdio_base = CPSW_MDIO_BASE,
  283. .cpsw_base = CPSW_BASE,
  284. .mdio_div = 0xff,
  285. .channels = 8,
  286. .cpdma_reg_ofs = 0x800,
  287. .slaves = 1,
  288. .slave_data = cpsw_slaves,
  289. .ale_reg_ofs = 0xd00,
  290. .ale_entries = 1024,
  291. .host_port_reg_ofs = 0x108,
  292. .hw_stats_reg_ofs = 0x900,
  293. .bd_ram_ofs = 0x2000,
  294. .mac_control = (1 << 5),
  295. .control = cpsw_control,
  296. .host_port_num = 0,
  297. .version = CPSW_CTRL_VERSION_2,
  298. };
  299. #endif
  300. /*
  301. * This function will:
  302. * Perform fixups to the PHY present on certain boards. We only need this
  303. * function in:
  304. * - SPL with either CPSW or USB ethernet support
  305. * - Full U-Boot, with either CPSW or USB ethernet
  306. * Build in only these cases to avoid warnings about unused variables
  307. * when we build an SPL that has neither option but full U-Boot will.
  308. */
  309. #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\
  310. defined(CONFIG_SPL_BUILD)) || \
  311. ((defined(CONFIG_DRIVER_TI_CPSW) || \
  312. defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
  313. !defined(CONFIG_SPL_BUILD))
  314. int board_eth_init(bd_t *bis)
  315. {
  316. int ecode, rv, n;
  317. uint8_t mac_addr[6];
  318. struct board_eeconfig header;
  319. __maybe_unused enum board_type board;
  320. /* Default manufacturing address; used when no EE or invalid */
  321. n = 0;
  322. mac_addr[0] = 0;
  323. mac_addr[1] = 0x20;
  324. mac_addr[2] = 0x18;
  325. mac_addr[3] = 0x1C;
  326. mac_addr[4] = 0x00;
  327. mac_addr[5] = 0x01;
  328. ecode = read_eeprom(&header);
  329. /* if we have a valid EE, get mac address from there */
  330. if ((ecode == 0) &&
  331. is_valid_ethaddr((const u8 *)&header.mac_addr[0][0])) {
  332. memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6);
  333. }
  334. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  335. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  336. if (!env_get("ethaddr")) {
  337. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  338. if (is_valid_ethaddr(mac_addr))
  339. eth_env_set_enetaddr("ethaddr", mac_addr);
  340. }
  341. #ifdef CONFIG_DRIVER_TI_CPSW
  342. board = get_board_type(false);
  343. /* Rev.A uses 10/100 PHY in mii mode */
  344. if (board == BAV335A) {
  345. writel(MII_MODE_ENABLE, &cdev->miisel);
  346. cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
  347. cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
  348. }
  349. /* Rev.B (default) uses GB PHY in rmii mode */
  350. else {
  351. writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
  352. cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if
  353. = PHY_INTERFACE_MODE_RGMII;
  354. }
  355. rv = cpsw_register(&cpsw_data);
  356. if (rv < 0)
  357. printf("Error %d registering CPSW switch\n", rv);
  358. else
  359. n += rv;
  360. #endif
  361. #endif
  362. return n;
  363. }
  364. #endif