mem-common.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Texas Instruments, <www.ti.com>
  5. *
  6. * Author :
  7. * Mansoor Ahamed <mansoor.ahamed@ti.com>
  8. *
  9. * Initial Code from:
  10. * Manikandan Pillai <mani.pillai@ti.com>
  11. * Richard Woodruff <r-woodruff2@ti.com>
  12. * Syed Mohammed Khasim <khasim@ti.com>
  13. */
  14. #include <common.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/cpu.h>
  17. #include <asm/arch/mem.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <command.h>
  20. #include <linux/mtd/omap_gpmc.h>
  21. #include <jffs2/load_kernel.h>
  22. const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE;
  23. #if defined(CONFIG_NOR)
  24. char gpmc_cs0_flash = MTD_DEV_TYPE_NOR;
  25. #elif defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND)
  26. char gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
  27. #elif defined(CONFIG_CMD_ONENAND)
  28. char gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
  29. #else
  30. char gpmc_cs0_flash = -1;
  31. #endif
  32. #if defined(CONFIG_OMAP34XX)
  33. /********************************************************
  34. * mem_ok() - test used to see if timings are correct
  35. * for a part. Helps in guessing which part
  36. * we are currently using.
  37. *******************************************************/
  38. u32 mem_ok(u32 cs)
  39. {
  40. u32 val1, val2, addr;
  41. u32 pattern = 0x12345678;
  42. addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
  43. writel(0x0, addr + 0x400); /* clear pos A */
  44. writel(pattern, addr); /* pattern to pos B */
  45. writel(0x0, addr + 4); /* remove pattern off the bus */
  46. val1 = readl(addr + 0x400); /* get pos A value */
  47. val2 = readl(addr); /* get val2 */
  48. writel(0x0, addr + 0x400); /* clear pos A */
  49. if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
  50. return 0;
  51. else
  52. return 1;
  53. }
  54. #endif
  55. void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
  56. u32 base, u32 size)
  57. {
  58. writel(0, &cs->config7);
  59. sdelay(1000);
  60. /* Delay for settling */
  61. writel(gpmc_config[0], &cs->config1);
  62. writel(gpmc_config[1], &cs->config2);
  63. writel(gpmc_config[2], &cs->config3);
  64. writel(gpmc_config[3], &cs->config4);
  65. writel(gpmc_config[4], &cs->config5);
  66. writel(gpmc_config[5], &cs->config6);
  67. /* Enable the config */
  68. writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
  69. (1 << 6)), &cs->config7);
  70. sdelay(2000);
  71. }
  72. void set_gpmc_cs0(int flash_type)
  73. {
  74. const u32 *gpmc_regs;
  75. u32 base, size;
  76. #if defined(CONFIG_NOR)
  77. const u32 gpmc_regs_nor[GPMC_MAX_REG] = {
  78. STNOR_GPMC_CONFIG1,
  79. STNOR_GPMC_CONFIG2,
  80. STNOR_GPMC_CONFIG3,
  81. STNOR_GPMC_CONFIG4,
  82. STNOR_GPMC_CONFIG5,
  83. STNOR_GPMC_CONFIG6,
  84. STNOR_GPMC_CONFIG7
  85. };
  86. #endif
  87. #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND)
  88. const u32 gpmc_regs_nand[GPMC_MAX_REG] = {
  89. M_NAND_GPMC_CONFIG1,
  90. M_NAND_GPMC_CONFIG2,
  91. M_NAND_GPMC_CONFIG3,
  92. M_NAND_GPMC_CONFIG4,
  93. M_NAND_GPMC_CONFIG5,
  94. M_NAND_GPMC_CONFIG6,
  95. 0
  96. };
  97. #endif
  98. #if defined(CONFIG_CMD_ONENAND)
  99. const u32 gpmc_regs_onenand[GPMC_MAX_REG] = {
  100. ONENAND_GPMC_CONFIG1,
  101. ONENAND_GPMC_CONFIG2,
  102. ONENAND_GPMC_CONFIG3,
  103. ONENAND_GPMC_CONFIG4,
  104. ONENAND_GPMC_CONFIG5,
  105. ONENAND_GPMC_CONFIG6,
  106. 0
  107. };
  108. #endif
  109. switch (flash_type) {
  110. #if defined(CONFIG_NOR)
  111. case MTD_DEV_TYPE_NOR:
  112. gpmc_regs = gpmc_regs_nor;
  113. base = CONFIG_SYS_FLASH_BASE;
  114. size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M :
  115. ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M :
  116. ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M :
  117. ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M :
  118. GPMC_SIZE_16M)));
  119. break;
  120. #endif
  121. #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_CMD_NAND)
  122. case MTD_DEV_TYPE_NAND:
  123. gpmc_regs = gpmc_regs_nand;
  124. base = CONFIG_SYS_NAND_BASE;
  125. size = GPMC_SIZE_16M;
  126. break;
  127. #endif
  128. #if defined(CONFIG_CMD_ONENAND)
  129. case MTD_DEV_TYPE_ONENAND:
  130. gpmc_regs = gpmc_regs_onenand;
  131. base = CONFIG_SYS_ONENAND_BASE;
  132. size = GPMC_SIZE_128M;
  133. break;
  134. #endif
  135. default:
  136. /* disable the GPMC0 config set by ROM code */
  137. writel(0, &gpmc_cfg->cs[0].config7);
  138. sdelay(1000);
  139. return;
  140. }
  141. /* enable chip-select specific configurations */
  142. enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
  143. }
  144. /*****************************************************
  145. * gpmc_init(): init gpmc bus
  146. * Init GPMC for x16, MuxMode (SDRAM in x32).
  147. * This code can only be executed from SRAM or SDRAM.
  148. *****************************************************/
  149. void gpmc_init(void)
  150. {
  151. /* global settings */
  152. writel(0x00000008, &gpmc_cfg->sysconfig);
  153. writel(0x00000000, &gpmc_cfg->irqstatus);
  154. writel(0x00000000, &gpmc_cfg->irqenable);
  155. /* disable timeout, set a safe reset value */
  156. writel(0x00001ff0, &gpmc_cfg->timeout_control);
  157. writel(gpmc_cs0_flash == MTD_DEV_TYPE_NOR ?
  158. 0x00000200 : 0x00000012, &gpmc_cfg->config);
  159. set_gpmc_cs0(gpmc_cs0_flash);
  160. }