hx8238d.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copied from simple-panel
  4. * Copyright (c) 2016 Google, Inc
  5. * Written by Simon Glass <sjg@chromium.org>
  6. * Copyright (c) 2018 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
  7. * Modified by Moses Christopher <BollavarapuMoses.Christopher@in.bosch.com>
  8. *
  9. * Panel Initialization for HX8238D panel from Himax
  10. * Resolution: 320x240
  11. * Color-Mode: RGB
  12. *
  13. */
  14. #include <common.h>
  15. #include <dm.h>
  16. #include <panel.h>
  17. #include <spi.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. /* Register Address */
  20. #define HX8238D_OUTPUT_CTRL_ADDR 0x01
  21. #define HX8238D_LCD_AC_CTRL_ADDR 0x02
  22. #define HX8238D_POWER_CTRL_1_ADDR 0x03
  23. #define HX8238D_DATA_CLR_CTRL_ADDR 0X04
  24. #define HX8238D_FUNCTION_CTRL_ADDR 0x05
  25. #define HX8238D_LED_CTRL_ADDR 0x08
  26. #define HX8238D_CONT_BRIGHT_CTRL_ADDR 0x0A
  27. #define HX8238D_FRAME_CYCLE_CTRL_ADDR 0x0B
  28. #define HX8238D_POWER_CTRL_2_ADDR 0x0D
  29. #define HX8238D_POWER_CTRL_3_ADDR 0x0E
  30. #define HX8238D_GATE_SCAN_POS_ADDR 0x0F
  31. #define HX8238D_HORIZONTAL_PORCH_ADDR 0x16
  32. #define HX8238D_VERTICAL_PORCH_ADDR 0x17
  33. #define HX8238D_POWER_CTRL_4_ADDR 0x1E
  34. #define HX8238D_GAMMA_CTRL_1_ADDR 0x30
  35. #define HX8238D_GAMMA_CTRL_2_ADDR 0x31
  36. #define HX8238D_GAMMA_CTRL_3_ADDR 0x32
  37. #define HX8238D_GAMMA_CTRL_4_ADDR 0x33
  38. #define HX8238D_GAMMA_CTRL_5_ADDR 0x34
  39. #define HX8238D_GAMMA_CTRL_6_ADDR 0x35
  40. #define HX8238D_GAMMA_CTRL_7_ADDR 0x36
  41. #define HX8238D_GAMMA_CTRL_8_ADDR 0x37
  42. #define HX8238D_GAMMA_CTRL_9_ADDR 0x3A
  43. #define HX8238D_GAMMA_CTRL_10_ADDR 0x3B
  44. /* Register Data */
  45. #define HX8238D_OUTPUT_CTRL 0x6300
  46. #define HX8238D_LCD_AC_CTRL 0x0200
  47. #define HX8238D_POWER_CTRL_1 0x6564
  48. #define HX8238D_DATA_CLR_CTRL 0x04C7
  49. #define HX8238D_FUNCTION_CTRL 0xA884
  50. #define HX8238D_LED_CTRL 0x00CE
  51. #define HX8238D_CONT_BRIGHT_CTRL 0x4008
  52. #define HX8238D_FRAME_CYCLE_CTRL 0xD400
  53. #define HX8238D_POWER_CTRL_2 0x3229
  54. #define HX8238D_POWER_CTRL_3 0x1200
  55. #define HX8238D_GATE_SCAN_POS 0x0000
  56. #define HX8238D_HORIZONTAL_PORCH 0x9F80
  57. #define HX8238D_VERTICAL_PORCH 0x3F02
  58. #define HX8238D_POWER_CTRL_4 0x005C
  59. /* Gamma Control */
  60. #define HX8238D_GAMMA_CTRL_1 0x0103
  61. #define HX8238D_GAMMA_CTRL_2 0x0407
  62. #define HX8238D_GAMMA_CTRL_3 0x0705
  63. #define HX8238D_GAMMA_CTRL_4 0x0002
  64. #define HX8238D_GAMMA_CTRL_5 0x0505
  65. #define HX8238D_GAMMA_CTRL_6 0x0303
  66. #define HX8238D_GAMMA_CTRL_7 0x0707
  67. #define HX8238D_GAMMA_CTRL_8 0x0100
  68. #define HX8238D_GAMMA_CTRL_9 0x1F00
  69. #define HX8238D_GAMMA_CTRL_10 0x000F
  70. /* Primary SPI register identification, 011100 */
  71. /* Select register, RS=0, RS=0 */
  72. /* Write register, RS=1, RW=0 */
  73. #define HX8238D_PRIMARY_SELECT_REG 0x70
  74. #define HX8238D_PRIMARY_WRITE_REG (HX8238D_PRIMARY_SELECT_REG | (0x1 << 1))
  75. #define HX8238D_REG_BIT_LEN 24
  76. struct hx8238d_priv {
  77. struct spi_slave *spi;
  78. };
  79. static int hx8238d_ofdata_to_platdata(struct udevice *dev)
  80. {
  81. struct hx8238d_priv *priv = dev_get_priv(dev);
  82. priv->spi = dev_get_parent_priv(dev);
  83. return 0;
  84. }
  85. /* data[0] => REGISTER ADDRESS */
  86. /* data[1] => REGISTER VALUE */
  87. struct hx8238d_command {
  88. u16 data[2];
  89. };
  90. static struct hx8238d_command hx8238d_init_commands[] = {
  91. { .data = { HX8238D_OUTPUT_CTRL_ADDR, HX8238D_OUTPUT_CTRL } },
  92. { .data = { HX8238D_LCD_AC_CTRL_ADDR, HX8238D_LCD_AC_CTRL } },
  93. { .data = { HX8238D_POWER_CTRL_1_ADDR, HX8238D_POWER_CTRL_1 } },
  94. { .data = { HX8238D_DATA_CLR_CTRL_ADDR, HX8238D_DATA_CLR_CTRL } },
  95. { .data = { HX8238D_FUNCTION_CTRL_ADDR, HX8238D_FUNCTION_CTRL } },
  96. { .data = { HX8238D_LED_CTRL_ADDR, HX8238D_LED_CTRL } },
  97. { .data = { HX8238D_CONT_BRIGHT_CTRL_ADDR, HX8238D_CONT_BRIGHT_CTRL } },
  98. { .data = { HX8238D_FRAME_CYCLE_CTRL_ADDR, HX8238D_FRAME_CYCLE_CTRL } },
  99. { .data = { HX8238D_POWER_CTRL_2_ADDR, HX8238D_POWER_CTRL_2 } },
  100. { .data = { HX8238D_POWER_CTRL_3_ADDR, HX8238D_POWER_CTRL_3 } },
  101. { .data = { HX8238D_GATE_SCAN_POS_ADDR, HX8238D_GATE_SCAN_POS } },
  102. { .data = { HX8238D_HORIZONTAL_PORCH_ADDR, HX8238D_HORIZONTAL_PORCH } },
  103. { .data = { HX8238D_VERTICAL_PORCH_ADDR, HX8238D_VERTICAL_PORCH } },
  104. { .data = { HX8238D_POWER_CTRL_4_ADDR, HX8238D_POWER_CTRL_4 } },
  105. { .data = { HX8238D_GAMMA_CTRL_1_ADDR, HX8238D_GAMMA_CTRL_1 } },
  106. { .data = { HX8238D_GAMMA_CTRL_2_ADDR, HX8238D_GAMMA_CTRL_2 } },
  107. { .data = { HX8238D_GAMMA_CTRL_3_ADDR, HX8238D_GAMMA_CTRL_3 } },
  108. { .data = { HX8238D_GAMMA_CTRL_4_ADDR, HX8238D_GAMMA_CTRL_4 } },
  109. { .data = { HX8238D_GAMMA_CTRL_5_ADDR, HX8238D_GAMMA_CTRL_5 } },
  110. { .data = { HX8238D_GAMMA_CTRL_6_ADDR, HX8238D_GAMMA_CTRL_6 } },
  111. { .data = { HX8238D_GAMMA_CTRL_7_ADDR, HX8238D_GAMMA_CTRL_7 } },
  112. { .data = { HX8238D_GAMMA_CTRL_8_ADDR, HX8238D_GAMMA_CTRL_8 } },
  113. { .data = { HX8238D_GAMMA_CTRL_9_ADDR, HX8238D_GAMMA_CTRL_9 } },
  114. { .data = { HX8238D_GAMMA_CTRL_10_ADDR, HX8238D_GAMMA_CTRL_10 } },
  115. };
  116. /*
  117. * Generate Primary Register Buffer for Register Select and Register Write
  118. * First 6 MSB bits of Primary Register is represented with 011100
  119. *
  120. */
  121. static void hx8238d_generate_reg_buffers(struct hx8238d_command command,
  122. u8 *sr_buf, uint8_t *wr_buf)
  123. {
  124. struct hx8238d_command cmd = command;
  125. sr_buf[0] = HX8238D_PRIMARY_SELECT_REG;
  126. sr_buf[1] = (cmd.data[0] >> 8) & 0xff;
  127. sr_buf[2] = (cmd.data[0]) & 0xff;
  128. wr_buf[0] = HX8238D_PRIMARY_WRITE_REG;
  129. wr_buf[1] = (cmd.data[1] >> 8) & 0xff;
  130. wr_buf[2] = (cmd.data[1]) & 0xff;
  131. }
  132. static int hx8238d_probe(struct udevice *dev)
  133. {
  134. struct hx8238d_priv *priv = dev_get_priv(dev);
  135. int ret;
  136. ret = spi_claim_bus(priv->spi);
  137. if (ret) {
  138. debug("Failed to claim bus: %d\n", ret);
  139. return ret;
  140. }
  141. for (int i = 0; i < ARRAY_SIZE(hx8238d_init_commands); i++) {
  142. u8 sr_buf[3], wr_buf[3];
  143. const struct hx8238d_command cmd = hx8238d_init_commands[i];
  144. hx8238d_generate_reg_buffers(cmd, sr_buf, wr_buf);
  145. ret = spi_xfer(priv->spi, HX8238D_REG_BIT_LEN, sr_buf, NULL,
  146. SPI_XFER_BEGIN | SPI_XFER_END);
  147. if (ret) {
  148. debug("Failed to select register %d\n", ret);
  149. goto free;
  150. }
  151. ret = spi_xfer(priv->spi, HX8238D_REG_BIT_LEN, wr_buf, NULL,
  152. SPI_XFER_BEGIN | SPI_XFER_END);
  153. if (ret) {
  154. debug("Failed to write value %d\n", ret);
  155. goto free;
  156. }
  157. }
  158. free:
  159. spi_release_bus(priv->spi);
  160. return ret;
  161. }
  162. static const struct udevice_id hx8238d_ids[] = {
  163. { .compatible = "himax,hx8238d" },
  164. { }
  165. };
  166. U_BOOT_DRIVER(hx8238d) = {
  167. .name = "hx8238d",
  168. .id = UCLASS_PANEL,
  169. .of_match = hx8238d_ids,
  170. .of_to_plat = hx8238d_ofdata_to_platdata,
  171. .probe = hx8238d_probe,
  172. .priv_auto = sizeof(struct hx8238d_priv),
  173. };