da8xx-fb.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Porting to u-boot:
  4. *
  5. * (C) Copyright 2011
  6. * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  7. *
  8. * Copyright (C) 2008-2009 MontaVista Software Inc.
  9. * Copyright (C) 2008-2009 Texas Instruments Inc
  10. *
  11. * Based on the LCD driver for TI Avalanche processors written by
  12. * Ajay Singh and Shalom Hai.
  13. */
  14. #include <common.h>
  15. #include <log.h>
  16. #include <malloc.h>
  17. #include <memalign.h>
  18. #include <video_fb.h>
  19. #include <asm/global_data.h>
  20. #include <linux/delay.h>
  21. #include <linux/list.h>
  22. #include <linux/fb.h>
  23. #include <linux/errno.h>
  24. #include <asm/io.h>
  25. #include <asm/arch/hardware.h>
  26. #include "videomodes.h"
  27. #include "da8xx-fb.h"
  28. #if !defined(DA8XX_LCD_CNTL_BASE)
  29. #define DA8XX_LCD_CNTL_BASE DAVINCI_LCD_CNTL_BASE
  30. #endif
  31. #define DRIVER_NAME "da8xx_lcdc"
  32. #define LCD_VERSION_1 1
  33. #define LCD_VERSION_2 2
  34. /* LCD Status Register */
  35. #define LCD_END_OF_FRAME1 (1 << 9)
  36. #define LCD_END_OF_FRAME0 (1 << 8)
  37. #define LCD_PL_LOAD_DONE (1 << 6)
  38. #define LCD_FIFO_UNDERFLOW (1 << 5)
  39. #define LCD_SYNC_LOST (1 << 2)
  40. /* LCD DMA Control Register */
  41. #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
  42. #define LCD_DMA_BURST_1 0x0
  43. #define LCD_DMA_BURST_2 0x1
  44. #define LCD_DMA_BURST_4 0x2
  45. #define LCD_DMA_BURST_8 0x3
  46. #define LCD_DMA_BURST_16 0x4
  47. #define LCD_V1_END_OF_FRAME_INT_ENA (1 << 2)
  48. #define LCD_V2_END_OF_FRAME0_INT_ENA (1 << 8)
  49. #define LCD_V2_END_OF_FRAME1_INT_ENA (1 << 9)
  50. #define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
  51. #define LCD_V2_TFT_24BPP_MODE (1 << 25)
  52. #define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
  53. /* LCD Control Register */
  54. #define LCD_CLK_DIVISOR(x) ((x) << 8)
  55. #define LCD_RASTER_MODE 0x01
  56. /* LCD Raster Control Register */
  57. #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
  58. #define PALETTE_AND_DATA 0x00
  59. #define PALETTE_ONLY 0x01
  60. #define DATA_ONLY 0x02
  61. #define LCD_MONO_8BIT_MODE (1 << 9)
  62. #define LCD_RASTER_ORDER (1 << 8)
  63. #define LCD_TFT_MODE (1 << 7)
  64. #define LCD_V1_UNDERFLOW_INT_ENA (1 << 6)
  65. #define LCD_V2_UNDERFLOW_INT_ENA (1 << 5)
  66. #define LCD_V1_PL_INT_ENA (1 << 4)
  67. #define LCD_V2_PL_INT_ENA (1 << 6)
  68. #define LCD_MONOCHROME_MODE (1 << 1)
  69. #define LCD_RASTER_ENABLE (1 << 0)
  70. #define LCD_TFT_ALT_ENABLE (1 << 23)
  71. #define LCD_STN_565_ENABLE (1 << 24)
  72. #define LCD_V2_DMA_CLK_EN (1 << 2)
  73. #define LCD_V2_LIDD_CLK_EN (1 << 1)
  74. #define LCD_V2_CORE_CLK_EN (1 << 0)
  75. #define LCD_V2_LPP_B10 26
  76. #define LCD_V2_TFT_24BPP_MODE (1 << 25)
  77. #define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
  78. /* LCD Raster Timing 2 Register */
  79. #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
  80. #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
  81. #define LCD_SYNC_CTRL (1 << 25)
  82. #define LCD_SYNC_EDGE (1 << 24)
  83. #define LCD_INVERT_PIXEL_CLOCK (1 << 22)
  84. #define LCD_INVERT_LINE_CLOCK (1 << 21)
  85. #define LCD_INVERT_FRAME_CLOCK (1 << 20)
  86. /* Clock registers available only on Version 2 */
  87. #define LCD_CLK_MAIN_RESET (1 << 3)
  88. /* LCD Block */
  89. struct da8xx_lcd_regs {
  90. u32 revid;
  91. u32 ctrl;
  92. u32 stat;
  93. u32 lidd_ctrl;
  94. u32 lidd_cs0_conf;
  95. u32 lidd_cs0_addr;
  96. u32 lidd_cs0_data;
  97. u32 lidd_cs1_conf;
  98. u32 lidd_cs1_addr;
  99. u32 lidd_cs1_data;
  100. u32 raster_ctrl;
  101. u32 raster_timing_0;
  102. u32 raster_timing_1;
  103. u32 raster_timing_2;
  104. u32 raster_subpanel;
  105. u32 reserved;
  106. u32 dma_ctrl;
  107. u32 dma_frm_buf_base_addr_0;
  108. u32 dma_frm_buf_ceiling_addr_0;
  109. u32 dma_frm_buf_base_addr_1;
  110. u32 dma_frm_buf_ceiling_addr_1;
  111. u32 resv1;
  112. u32 raw_stat;
  113. u32 masked_stat;
  114. u32 int_ena_set;
  115. u32 int_ena_clr;
  116. u32 end_of_int_ind;
  117. /* Clock registers available only on Version 2 */
  118. u32 clk_ena;
  119. u32 clk_reset;
  120. };
  121. #define LCD_NUM_BUFFERS 1
  122. #define WSI_TIMEOUT 50
  123. #define PALETTE_SIZE 256
  124. #define LEFT_MARGIN 64
  125. #define RIGHT_MARGIN 64
  126. #define UPPER_MARGIN 32
  127. #define LOWER_MARGIN 32
  128. #define WAIT_FOR_FRAME_DONE true
  129. #define NO_WAIT_FOR_FRAME_DONE false
  130. #define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
  131. static struct da8xx_lcd_regs *da8xx_fb_reg_base;
  132. DECLARE_GLOBAL_DATA_PTR;
  133. /* graphics setup */
  134. static GraphicDevice gpanel;
  135. static const struct da8xx_panel *lcd_panel;
  136. static struct fb_info *da8xx_fb_info;
  137. static int bits_x_pixel;
  138. static unsigned int lcd_revision;
  139. const struct lcd_ctrl_config *da8xx_lcd_cfg;
  140. static inline unsigned int lcdc_read(u32 *addr)
  141. {
  142. return (unsigned int)readl(addr);
  143. }
  144. static inline void lcdc_write(unsigned int val, u32 *addr)
  145. {
  146. writel(val, addr);
  147. }
  148. struct da8xx_fb_par {
  149. u32 p_palette_base;
  150. unsigned char *v_palette_base;
  151. dma_addr_t vram_phys;
  152. unsigned long vram_size;
  153. void *vram_virt;
  154. unsigned int dma_start;
  155. unsigned int dma_end;
  156. struct clk *lcdc_clk;
  157. int irq;
  158. unsigned short pseudo_palette[16];
  159. unsigned int palette_sz;
  160. unsigned int pxl_clk;
  161. int blank;
  162. int vsync_flag;
  163. int vsync_timeout;
  164. };
  165. /* Variable Screen Information */
  166. static struct fb_var_screeninfo da8xx_fb_var = {
  167. .xoffset = 0,
  168. .yoffset = 0,
  169. .transp = {0, 0, 0},
  170. .nonstd = 0,
  171. .activate = 0,
  172. .height = -1,
  173. .width = -1,
  174. .pixclock = 46666, /* 46us - AUO display */
  175. .accel_flags = 0,
  176. .left_margin = LEFT_MARGIN,
  177. .right_margin = RIGHT_MARGIN,
  178. .upper_margin = UPPER_MARGIN,
  179. .lower_margin = LOWER_MARGIN,
  180. .sync = 0,
  181. .vmode = FB_VMODE_NONINTERLACED
  182. };
  183. static struct fb_fix_screeninfo da8xx_fb_fix = {
  184. .id = "DA8xx FB Drv",
  185. .type = FB_TYPE_PACKED_PIXELS,
  186. .type_aux = 0,
  187. .visual = FB_VISUAL_PSEUDOCOLOR,
  188. .xpanstep = 0,
  189. .ypanstep = 1,
  190. .ywrapstep = 0,
  191. .accel = FB_ACCEL_NONE
  192. };
  193. /* Enable the Raster Engine of the LCD Controller */
  194. static inline void lcd_enable_raster(void)
  195. {
  196. u32 reg;
  197. /* Put LCDC in reset for several cycles */
  198. if (lcd_revision == LCD_VERSION_2)
  199. lcdc_write(LCD_CLK_MAIN_RESET,
  200. &da8xx_fb_reg_base->clk_reset);
  201. udelay(1000);
  202. /* Bring LCDC out of reset */
  203. if (lcd_revision == LCD_VERSION_2)
  204. lcdc_write(0,
  205. &da8xx_fb_reg_base->clk_reset);
  206. udelay(1000);
  207. reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
  208. if (!(reg & LCD_RASTER_ENABLE))
  209. lcdc_write(reg | LCD_RASTER_ENABLE,
  210. &da8xx_fb_reg_base->raster_ctrl);
  211. }
  212. /* Disable the Raster Engine of the LCD Controller */
  213. static inline void lcd_disable_raster(bool wait_for_frame_done)
  214. {
  215. u32 reg;
  216. u32 loop_cnt = 0;
  217. u32 stat;
  218. u32 i = 0;
  219. if (wait_for_frame_done)
  220. loop_cnt = 5000;
  221. reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
  222. if (reg & LCD_RASTER_ENABLE)
  223. lcdc_write(reg & ~LCD_RASTER_ENABLE,
  224. &da8xx_fb_reg_base->raster_ctrl);
  225. /* Wait for the current frame to complete */
  226. do {
  227. if (lcd_revision == LCD_VERSION_1)
  228. stat = lcdc_read(&da8xx_fb_reg_base->stat);
  229. else
  230. stat = lcdc_read(&da8xx_fb_reg_base->raw_stat);
  231. mdelay(1);
  232. } while (!(stat & 0x01) && (i++ < loop_cnt));
  233. if (lcd_revision == LCD_VERSION_1)
  234. lcdc_write(stat, &da8xx_fb_reg_base->stat);
  235. else
  236. lcdc_write(stat, &da8xx_fb_reg_base->raw_stat);
  237. if ((loop_cnt != 0) && (i >= loop_cnt)) {
  238. printf("LCD Controller timed out\n");
  239. return;
  240. }
  241. }
  242. static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
  243. {
  244. u32 start;
  245. u32 end;
  246. u32 reg_ras;
  247. u32 reg_dma;
  248. u32 reg_int;
  249. /* init reg to clear PLM (loading mode) fields */
  250. reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
  251. reg_ras &= ~(3 << 20);
  252. reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
  253. if (load_mode == LOAD_DATA) {
  254. start = par->dma_start;
  255. end = par->dma_end;
  256. reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
  257. if (lcd_revision == LCD_VERSION_1) {
  258. reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
  259. } else {
  260. reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
  261. LCD_V2_END_OF_FRAME0_INT_ENA |
  262. LCD_V2_END_OF_FRAME1_INT_ENA |
  263. LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
  264. lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
  265. }
  266. #if (LCD_NUM_BUFFERS == 2)
  267. reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
  268. lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  269. lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  270. lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
  271. lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
  272. #else
  273. reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
  274. lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  275. lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  276. lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
  277. lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
  278. #endif
  279. } else if (load_mode == LOAD_PALETTE) {
  280. start = par->p_palette_base;
  281. end = start + par->palette_sz - 1;
  282. reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
  283. if (lcd_revision == LCD_VERSION_1) {
  284. reg_ras |= LCD_V1_PL_INT_ENA;
  285. } else {
  286. reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
  287. LCD_V2_PL_INT_ENA;
  288. lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
  289. }
  290. lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  291. lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  292. }
  293. lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
  294. lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
  295. /*
  296. * The Raster enable bit must be set after all other control fields are
  297. * set.
  298. */
  299. lcd_enable_raster();
  300. }
  301. /* Configure the Burst Size of DMA */
  302. static int lcd_cfg_dma(int burst_size)
  303. {
  304. u32 reg;
  305. reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
  306. switch (burst_size) {
  307. case 1:
  308. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
  309. break;
  310. case 2:
  311. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
  312. break;
  313. case 4:
  314. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
  315. break;
  316. case 8:
  317. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
  318. break;
  319. case 16:
  320. reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
  321. break;
  322. default:
  323. return -EINVAL;
  324. }
  325. lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
  326. return 0;
  327. }
  328. static void lcd_cfg_ac_bias(int period, int transitions_per_int)
  329. {
  330. u32 reg;
  331. /* Set the AC Bias Period and Number of Transitions per Interrupt */
  332. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
  333. reg |= LCD_AC_BIAS_FREQUENCY(period) |
  334. LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
  335. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
  336. }
  337. static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
  338. int front_porch)
  339. {
  340. u32 reg;
  341. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
  342. reg |= ((back_porch & 0xff) << 24)
  343. | ((front_porch & 0xff) << 16)
  344. | ((pulse_width & 0x3f) << 10);
  345. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
  346. }
  347. static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
  348. int front_porch)
  349. {
  350. u32 reg;
  351. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
  352. reg |= ((back_porch & 0xff) << 24)
  353. | ((front_porch & 0xff) << 16)
  354. | ((pulse_width & 0x3f) << 10);
  355. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
  356. }
  357. static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
  358. {
  359. u32 reg;
  360. u32 reg_int;
  361. reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
  362. LCD_MONO_8BIT_MODE |
  363. LCD_MONOCHROME_MODE);
  364. switch (cfg->p_disp_panel->panel_shade) {
  365. case MONOCHROME:
  366. reg |= LCD_MONOCHROME_MODE;
  367. if (cfg->mono_8bit_mode)
  368. reg |= LCD_MONO_8BIT_MODE;
  369. break;
  370. case COLOR_ACTIVE:
  371. reg |= LCD_TFT_MODE;
  372. if (cfg->tft_alt_mode)
  373. reg |= LCD_TFT_ALT_ENABLE;
  374. break;
  375. case COLOR_PASSIVE:
  376. if (cfg->stn_565_mode)
  377. reg |= LCD_STN_565_ENABLE;
  378. break;
  379. default:
  380. return -EINVAL;
  381. }
  382. /* enable additional interrupts here */
  383. if (lcd_revision == LCD_VERSION_1) {
  384. reg |= LCD_V1_UNDERFLOW_INT_ENA;
  385. } else {
  386. reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
  387. LCD_V2_UNDERFLOW_INT_ENA;
  388. lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
  389. }
  390. lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
  391. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
  392. if (cfg->sync_ctrl)
  393. reg |= LCD_SYNC_CTRL;
  394. else
  395. reg &= ~LCD_SYNC_CTRL;
  396. if (cfg->sync_edge)
  397. reg |= LCD_SYNC_EDGE;
  398. else
  399. reg &= ~LCD_SYNC_EDGE;
  400. if (cfg->invert_line_clock)
  401. reg |= LCD_INVERT_LINE_CLOCK;
  402. else
  403. reg &= ~LCD_INVERT_LINE_CLOCK;
  404. if (cfg->invert_frm_clock)
  405. reg |= LCD_INVERT_FRAME_CLOCK;
  406. else
  407. reg &= ~LCD_INVERT_FRAME_CLOCK;
  408. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
  409. return 0;
  410. }
  411. static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
  412. u32 bpp, u32 raster_order)
  413. {
  414. u32 reg;
  415. /* Set the Panel Width */
  416. /* Pixels per line = (PPL + 1)*16 */
  417. if (lcd_revision == LCD_VERSION_1) {
  418. /*
  419. * 0x3F in bits 4..9 gives max horizontal resolution = 1024
  420. * pixels
  421. */
  422. width &= 0x3f0;
  423. } else {
  424. /*
  425. * 0x7F in bits 4..10 gives max horizontal resolution = 2048
  426. * pixels.
  427. */
  428. width &= 0x7f0;
  429. }
  430. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
  431. reg &= 0xfffffc00;
  432. if (lcd_revision == LCD_VERSION_1) {
  433. reg |= ((width >> 4) - 1) << 4;
  434. } else {
  435. width = (width >> 4) - 1;
  436. reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
  437. }
  438. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
  439. /* Set the Panel Height */
  440. /* Set bits 9:0 of Lines Per Pixel */
  441. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
  442. reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
  443. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
  444. /* Set bit 10 of Lines Per Pixel */
  445. if (lcd_revision == LCD_VERSION_2) {
  446. reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
  447. reg |= ((height - 1) & 0x400) << 16;
  448. lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
  449. }
  450. /* Set the Raster Order of the Frame Buffer */
  451. reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
  452. if (raster_order)
  453. reg |= LCD_RASTER_ORDER;
  454. if (bpp == 24)
  455. reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
  456. else if (bpp == 32)
  457. reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
  458. | LCD_V2_TFT_24BPP_UNPACK);
  459. lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
  460. switch (bpp) {
  461. case 1:
  462. case 2:
  463. case 4:
  464. case 16:
  465. case 24:
  466. case 32:
  467. par->palette_sz = 16 * 2;
  468. break;
  469. case 8:
  470. par->palette_sz = 256 * 2;
  471. break;
  472. default:
  473. return -EINVAL;
  474. }
  475. return 0;
  476. }
  477. static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
  478. unsigned blue, unsigned transp,
  479. struct fb_info *info)
  480. {
  481. struct da8xx_fb_par *par = info->par;
  482. unsigned short *palette = (unsigned short *) par->v_palette_base;
  483. u_short pal;
  484. int update_hw = 0;
  485. if (regno > 255)
  486. return 1;
  487. if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
  488. return 1;
  489. if (info->var.bits_per_pixel == 8) {
  490. red >>= 4;
  491. green >>= 8;
  492. blue >>= 12;
  493. pal = (red & 0x0f00);
  494. pal |= (green & 0x00f0);
  495. pal |= (blue & 0x000f);
  496. if (palette[regno] != pal) {
  497. update_hw = 1;
  498. palette[regno] = pal;
  499. }
  500. } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
  501. red >>= (16 - info->var.red.length);
  502. red <<= info->var.red.offset;
  503. green >>= (16 - info->var.green.length);
  504. green <<= info->var.green.offset;
  505. blue >>= (16 - info->var.blue.length);
  506. blue <<= info->var.blue.offset;
  507. par->pseudo_palette[regno] = red | green | blue;
  508. if (palette[0] != 0x4000) {
  509. update_hw = 1;
  510. palette[0] = 0x4000;
  511. }
  512. } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
  513. ((info->var.bits_per_pixel == 24) && regno < 24)) {
  514. red >>= (24 - info->var.red.length);
  515. red <<= info->var.red.offset;
  516. green >>= (24 - info->var.green.length);
  517. green <<= info->var.green.offset;
  518. blue >>= (24 - info->var.blue.length);
  519. blue <<= info->var.blue.offset;
  520. par->pseudo_palette[regno] = red | green | blue;
  521. if (palette[0] != 0x4000) {
  522. update_hw = 1;
  523. palette[0] = 0x4000;
  524. }
  525. }
  526. /* Update the palette in the h/w as needed. */
  527. if (update_hw)
  528. lcd_blit(LOAD_PALETTE, par);
  529. return 0;
  530. }
  531. static void lcd_reset(struct da8xx_fb_par *par)
  532. {
  533. /* Disable the Raster if previously Enabled */
  534. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  535. /* DMA has to be disabled */
  536. lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
  537. lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
  538. if (lcd_revision == LCD_VERSION_2) {
  539. lcdc_write(0, &da8xx_fb_reg_base->int_ena_set);
  540. /* Write 1 to reset */
  541. lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
  542. lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
  543. }
  544. }
  545. static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
  546. {
  547. unsigned int lcd_clk, div;
  548. /* Get clock from sysclk2 */
  549. lcd_clk = clk_get(2);
  550. div = lcd_clk / par->pxl_clk;
  551. debug("LCD Clock: %d Divider: %d PixClk: %d\n",
  552. lcd_clk, div, par->pxl_clk);
  553. /* Configure the LCD clock divisor. */
  554. lcdc_write(LCD_CLK_DIVISOR(div) |
  555. (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
  556. if (lcd_revision == LCD_VERSION_2)
  557. lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
  558. LCD_V2_CORE_CLK_EN,
  559. &da8xx_fb_reg_base->clk_ena);
  560. }
  561. static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
  562. const struct da8xx_panel *panel)
  563. {
  564. u32 bpp;
  565. int ret = 0;
  566. lcd_reset(par);
  567. /* Calculate the divider */
  568. lcd_calc_clk_divider(par);
  569. if (panel->invert_pxl_clk)
  570. lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
  571. LCD_INVERT_PIXEL_CLOCK),
  572. &da8xx_fb_reg_base->raster_timing_2);
  573. else
  574. lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
  575. ~LCD_INVERT_PIXEL_CLOCK),
  576. &da8xx_fb_reg_base->raster_timing_2);
  577. /* Configure the DMA burst size. */
  578. ret = lcd_cfg_dma(cfg->dma_burst_sz);
  579. if (ret < 0)
  580. return ret;
  581. /* Configure the AC bias properties. */
  582. lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
  583. /* Configure the vertical and horizontal sync properties. */
  584. lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
  585. lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
  586. /* Configure for display */
  587. ret = lcd_cfg_display(cfg);
  588. if (ret < 0)
  589. return ret;
  590. if ((QVGA != cfg->p_disp_panel->panel_type) &&
  591. (WVGA != cfg->p_disp_panel->panel_type))
  592. return -EINVAL;
  593. if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
  594. cfg->bpp >= cfg->p_disp_panel->min_bpp)
  595. bpp = cfg->bpp;
  596. else
  597. bpp = cfg->p_disp_panel->max_bpp;
  598. if (bpp == 12)
  599. bpp = 16;
  600. ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
  601. (unsigned int)panel->height, bpp,
  602. cfg->raster_order);
  603. if (ret < 0)
  604. return ret;
  605. /* Configure FDD */
  606. lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
  607. (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
  608. return 0;
  609. }
  610. static void lcdc_dma_start(void)
  611. {
  612. struct da8xx_fb_par *par = da8xx_fb_info->par;
  613. lcdc_write(par->dma_start,
  614. &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  615. lcdc_write(par->dma_end,
  616. &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  617. lcdc_write(0,
  618. &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
  619. lcdc_write(0,
  620. &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
  621. }
  622. static u32 lcdc_irq_handler_rev01(void)
  623. {
  624. struct da8xx_fb_par *par = da8xx_fb_info->par;
  625. u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
  626. u32 reg_ras;
  627. if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
  628. debug("LCD_SYNC_LOST\n");
  629. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  630. lcdc_write(stat, &da8xx_fb_reg_base->stat);
  631. lcd_enable_raster();
  632. return LCD_SYNC_LOST;
  633. } else if (stat & LCD_PL_LOAD_DONE) {
  634. debug("LCD_PL_LOAD_DONE\n");
  635. /*
  636. * Must disable raster before changing state of any control bit.
  637. * And also must be disabled before clearing the PL loading
  638. * interrupt via the following write to the status register. If
  639. * this is done after then one gets multiple PL done interrupts.
  640. */
  641. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  642. lcdc_write(stat, &da8xx_fb_reg_base->stat);
  643. /* Disable PL completion interrupt */
  644. reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
  645. reg_ras &= ~LCD_V1_PL_INT_ENA;
  646. lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
  647. /* Setup and start data loading mode */
  648. lcd_blit(LOAD_DATA, par);
  649. return LCD_PL_LOAD_DONE;
  650. } else {
  651. lcdc_write(stat, &da8xx_fb_reg_base->stat);
  652. if (stat & LCD_END_OF_FRAME0)
  653. debug("LCD_END_OF_FRAME0\n");
  654. lcdc_write(par->dma_start,
  655. &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  656. lcdc_write(par->dma_end,
  657. &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  658. par->vsync_flag = 1;
  659. return LCD_END_OF_FRAME0;
  660. }
  661. return stat;
  662. }
  663. static u32 lcdc_irq_handler_rev02(void)
  664. {
  665. struct da8xx_fb_par *par = da8xx_fb_info->par;
  666. u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
  667. u32 reg_int;
  668. if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
  669. debug("LCD_SYNC_LOST\n");
  670. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  671. lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
  672. lcd_enable_raster();
  673. lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
  674. return LCD_SYNC_LOST;
  675. } else if (stat & LCD_PL_LOAD_DONE) {
  676. debug("LCD_PL_LOAD_DONE\n");
  677. /*
  678. * Must disable raster before changing state of any control bit.
  679. * And also must be disabled before clearing the PL loading
  680. * interrupt via the following write to the status register. If
  681. * this is done after then one gets multiple PL done interrupts.
  682. */
  683. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  684. lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
  685. /* Disable PL completion interrupt */
  686. reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) |
  687. (LCD_V2_PL_INT_ENA);
  688. lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr);
  689. /* Setup and start data loading mode */
  690. lcd_blit(LOAD_DATA, par);
  691. lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
  692. return LCD_PL_LOAD_DONE;
  693. } else {
  694. lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
  695. if (stat & LCD_END_OF_FRAME0)
  696. debug("LCD_END_OF_FRAME0\n");
  697. lcdc_write(par->dma_start,
  698. &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
  699. lcdc_write(par->dma_end,
  700. &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
  701. par->vsync_flag = 1;
  702. lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
  703. return LCD_END_OF_FRAME0;
  704. }
  705. lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
  706. return stat;
  707. }
  708. static u32 lcdc_irq_handler(void)
  709. {
  710. if (lcd_revision == LCD_VERSION_1)
  711. return lcdc_irq_handler_rev01();
  712. else
  713. return lcdc_irq_handler_rev02();
  714. }
  715. static u32 wait_for_event(u32 event)
  716. {
  717. u32 timeout = 50000;
  718. u32 ret;
  719. do {
  720. ret = lcdc_irq_handler();
  721. udelay(1000);
  722. --timeout;
  723. } while (!(ret & event) && timeout);
  724. if (!(ret & event)) {
  725. printf("%s: event %d not hit\n", __func__, event);
  726. return -1;
  727. }
  728. return 0;
  729. }
  730. void *video_hw_init(void)
  731. {
  732. struct da8xx_fb_par *par;
  733. u32 size;
  734. u32 rev;
  735. char *p;
  736. if (!lcd_panel) {
  737. printf("Display not initialized\n");
  738. return NULL;
  739. }
  740. gpanel.winSizeX = lcd_panel->width;
  741. gpanel.winSizeY = lcd_panel->height;
  742. gpanel.plnSizeX = lcd_panel->width;
  743. gpanel.plnSizeY = lcd_panel->height;
  744. switch (bits_x_pixel) {
  745. case 32:
  746. gpanel.gdfBytesPP = 4;
  747. gpanel.gdfIndex = GDF_32BIT_X888RGB;
  748. break;
  749. case 24:
  750. gpanel.gdfBytesPP = 4;
  751. gpanel.gdfIndex = GDF_32BIT_X888RGB;
  752. break;
  753. case 16:
  754. gpanel.gdfBytesPP = 2;
  755. gpanel.gdfIndex = GDF_16BIT_565RGB;
  756. break;
  757. default:
  758. gpanel.gdfBytesPP = 1;
  759. gpanel.gdfIndex = GDF__8BIT_INDEX;
  760. break;
  761. }
  762. da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE;
  763. /* Determine LCD IP Version */
  764. rev = lcdc_read(&da8xx_fb_reg_base->revid);
  765. switch (rev) {
  766. case 0x4C100102:
  767. lcd_revision = LCD_VERSION_1;
  768. break;
  769. case 0x4F200800:
  770. case 0x4F201000:
  771. lcd_revision = LCD_VERSION_2;
  772. break;
  773. default:
  774. printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n",
  775. rev);
  776. lcd_revision = LCD_VERSION_1;
  777. break;
  778. }
  779. debug("rev: 0x%x Resolution: %dx%d %d\n", rev,
  780. gpanel.winSizeX,
  781. gpanel.winSizeY,
  782. da8xx_lcd_cfg->bpp);
  783. size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
  784. da8xx_fb_info = malloc_cache_aligned(size);
  785. debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
  786. if (!da8xx_fb_info) {
  787. printf("Memory allocation failed for fb_info\n");
  788. return NULL;
  789. }
  790. memset(da8xx_fb_info, 0, size);
  791. p = (char *)da8xx_fb_info;
  792. da8xx_fb_info->par = p + sizeof(struct fb_info);
  793. debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
  794. par = da8xx_fb_info->par;
  795. par->pxl_clk = lcd_panel->pxl_clk;
  796. if (lcd_init(par, da8xx_lcd_cfg, lcd_panel) < 0) {
  797. printf("lcd_init failed\n");
  798. goto err_release_fb;
  799. }
  800. /* allocate frame buffer */
  801. par->vram_size = lcd_panel->width * lcd_panel->height *
  802. da8xx_lcd_cfg->bpp;
  803. par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
  804. par->vram_virt = malloc_cache_aligned(par->vram_size);
  805. par->vram_phys = (dma_addr_t) par->vram_virt;
  806. debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
  807. (unsigned int)par->vram_size,
  808. (unsigned int)par->vram_virt);
  809. if (!par->vram_virt) {
  810. printf("GLCD: malloc for frame buffer failed\n");
  811. goto err_release_fb;
  812. }
  813. gd->fb_base = (int)par->vram_virt;
  814. gpanel.frameAdrs = (unsigned int)par->vram_virt;
  815. da8xx_fb_info->screen_base = (char *) par->vram_virt;
  816. da8xx_fb_fix.smem_start = gpanel.frameAdrs;
  817. da8xx_fb_fix.smem_len = par->vram_size;
  818. da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8;
  819. par->dma_start = par->vram_phys;
  820. par->dma_end = par->dma_start + lcd_panel->height *
  821. da8xx_fb_fix.line_length - 1;
  822. /* allocate palette buffer */
  823. par->v_palette_base = malloc_cache_aligned(PALETTE_SIZE);
  824. if (!par->v_palette_base) {
  825. printf("GLCD: malloc for palette buffer failed\n");
  826. goto err_release_fb_mem;
  827. }
  828. memset(par->v_palette_base, 0, PALETTE_SIZE);
  829. par->p_palette_base = (unsigned int)par->v_palette_base;
  830. /* Initialize par */
  831. da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp;
  832. da8xx_fb_var.xres = lcd_panel->width;
  833. da8xx_fb_var.xres_virtual = lcd_panel->width;
  834. da8xx_fb_var.yres = lcd_panel->height;
  835. da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
  836. da8xx_fb_var.grayscale =
  837. da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
  838. da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp;
  839. da8xx_fb_var.hsync_len = lcd_panel->hsw;
  840. da8xx_fb_var.vsync_len = lcd_panel->vsw;
  841. /* Initialize fbinfo */
  842. da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
  843. da8xx_fb_info->fix = da8xx_fb_fix;
  844. da8xx_fb_info->var = da8xx_fb_var;
  845. da8xx_fb_info->pseudo_palette = par->pseudo_palette;
  846. da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
  847. FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
  848. /* Clear interrupt */
  849. memset((void *)par->vram_virt, 0, par->vram_size);
  850. lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
  851. if (lcd_revision == LCD_VERSION_1)
  852. lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
  853. else
  854. lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat);
  855. debug("Palette at 0x%x size %d\n", par->p_palette_base,
  856. par->palette_sz);
  857. lcdc_dma_start();
  858. /* Load a default palette */
  859. fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
  860. /* Check that the palette is loaded */
  861. wait_for_event(LCD_PL_LOAD_DONE);
  862. /* Wait until DMA is working */
  863. wait_for_event(LCD_END_OF_FRAME0);
  864. return (void *)&gpanel;
  865. err_release_fb_mem:
  866. free(par->vram_virt);
  867. err_release_fb:
  868. free(da8xx_fb_info);
  869. return NULL;
  870. }
  871. void da8xx_video_init(const struct da8xx_panel *panel,
  872. const struct lcd_ctrl_config *lcd_cfg, int bits_pixel)
  873. {
  874. lcd_panel = panel;
  875. da8xx_lcd_cfg = lcd_cfg;
  876. bits_x_pixel = bits_pixel;
  877. }