atmel_hlcdfb.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Driver for AT91/AT32 MULTI LAYER LCD Controller
  4. *
  5. * Copyright (C) 2012 Atmel Corporation
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <part.h>
  12. #include <asm/global_data.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/gpio.h>
  15. #include <asm/arch/clk.h>
  16. #include <clk.h>
  17. #include <dm.h>
  18. #include <fdtdec.h>
  19. #include <lcd.h>
  20. #include <video.h>
  21. #include <wait_bit.h>
  22. #include <atmel_hlcdc.h>
  23. #include <linux/bug.h>
  24. #if defined(CONFIG_LCD_LOGO)
  25. #include <bmp_logo.h>
  26. #endif
  27. DECLARE_GLOBAL_DATA_PTR;
  28. #ifndef CONFIG_DM_VIDEO
  29. /* configurable parameters */
  30. #define ATMEL_LCDC_CVAL_DEFAULT 0xc8
  31. #define ATMEL_LCDC_DMA_BURST_LEN 8
  32. #ifndef ATMEL_LCDC_GUARD_TIME
  33. #define ATMEL_LCDC_GUARD_TIME 1
  34. #endif
  35. #define ATMEL_LCDC_FIFO_SIZE 512
  36. /*
  37. * the CLUT register map as following
  38. * RCLUT(24 ~ 16), GCLUT(15 ~ 8), BCLUT(7 ~ 0)
  39. */
  40. void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
  41. {
  42. writel(panel_info.mmio + ATMEL_LCDC_LUT(regno),
  43. ((red << LCDC_BASECLUT_RCLUT_Pos) & LCDC_BASECLUT_RCLUT_Msk)
  44. | ((green << LCDC_BASECLUT_GCLUT_Pos) & LCDC_BASECLUT_GCLUT_Msk)
  45. | ((blue << LCDC_BASECLUT_BCLUT_Pos) & LCDC_BASECLUT_BCLUT_Msk));
  46. }
  47. ushort *configuration_get_cmap(void)
  48. {
  49. #if defined(CONFIG_LCD_LOGO)
  50. return bmp_logo_palette;
  51. #else
  52. return NULL;
  53. #endif
  54. }
  55. void lcd_ctrl_init(void *lcdbase)
  56. {
  57. unsigned long value;
  58. struct lcd_dma_desc *desc;
  59. struct atmel_hlcd_regs *regs;
  60. int ret;
  61. if (!has_lcdc())
  62. return; /* No lcdc */
  63. regs = (struct atmel_hlcd_regs *)panel_info.mmio;
  64. /* Disable DISP signal */
  65. writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
  66. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  67. false, 1000, false);
  68. if (ret)
  69. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  70. /* Disable synchronization */
  71. writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
  72. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  73. false, 1000, false);
  74. if (ret)
  75. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  76. /* Disable pixel clock */
  77. writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
  78. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  79. false, 1000, false);
  80. if (ret)
  81. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  82. /* Disable PWM */
  83. writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
  84. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  85. false, 1000, false);
  86. if (ret)
  87. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  88. /* Set pixel clock */
  89. value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
  90. if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
  91. value++;
  92. if (value < 1) {
  93. /* Using system clock as pixel clock */
  94. writel(LCDC_LCDCFG0_CLKDIV(0)
  95. | LCDC_LCDCFG0_CGDISHCR
  96. | LCDC_LCDCFG0_CGDISHEO
  97. | LCDC_LCDCFG0_CGDISOVR1
  98. | LCDC_LCDCFG0_CGDISBASE
  99. | panel_info.vl_clk_pol
  100. | LCDC_LCDCFG0_CLKSEL,
  101. &regs->lcdc_lcdcfg0);
  102. } else {
  103. writel(LCDC_LCDCFG0_CLKDIV(value - 2)
  104. | LCDC_LCDCFG0_CGDISHCR
  105. | LCDC_LCDCFG0_CGDISHEO
  106. | LCDC_LCDCFG0_CGDISOVR1
  107. | LCDC_LCDCFG0_CGDISBASE
  108. | panel_info.vl_clk_pol,
  109. &regs->lcdc_lcdcfg0);
  110. }
  111. /* Initialize control register 5 */
  112. value = 0;
  113. value |= panel_info.vl_sync;
  114. #ifndef LCD_OUTPUT_BPP
  115. /* Output is 24bpp */
  116. value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
  117. #else
  118. switch (LCD_OUTPUT_BPP) {
  119. case 12:
  120. value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
  121. break;
  122. case 16:
  123. value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
  124. break;
  125. case 18:
  126. value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
  127. break;
  128. case 24:
  129. value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
  130. break;
  131. default:
  132. BUG();
  133. break;
  134. }
  135. #endif
  136. value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME);
  137. value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
  138. writel(value, &regs->lcdc_lcdcfg5);
  139. /* Vertical & Horizontal Timing */
  140. value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1);
  141. value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
  142. writel(value, &regs->lcdc_lcdcfg1);
  143. value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
  144. value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
  145. writel(value, &regs->lcdc_lcdcfg2);
  146. value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
  147. value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
  148. writel(value, &regs->lcdc_lcdcfg3);
  149. /* Display size */
  150. value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1);
  151. value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1);
  152. writel(value, &regs->lcdc_lcdcfg4);
  153. writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
  154. &regs->lcdc_basecfg0);
  155. switch (NBITS(panel_info.vl_bpix)) {
  156. case 16:
  157. writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
  158. &regs->lcdc_basecfg1);
  159. break;
  160. case 32:
  161. writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
  162. &regs->lcdc_basecfg1);
  163. break;
  164. default:
  165. BUG();
  166. break;
  167. }
  168. writel(LCDC_BASECFG2_XSTRIDE(0), &regs->lcdc_basecfg2);
  169. writel(0, &regs->lcdc_basecfg3);
  170. writel(LCDC_BASECFG4_DMA, &regs->lcdc_basecfg4);
  171. /* Disable all interrupts */
  172. writel(~0UL, &regs->lcdc_lcdidr);
  173. writel(~0UL, &regs->lcdc_baseidr);
  174. /* Setup the DMA descriptor, this descriptor will loop to itself */
  175. desc = (struct lcd_dma_desc *)(lcdbase - 16);
  176. desc->address = (u32)lcdbase;
  177. /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
  178. desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
  179. | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
  180. desc->next = (u32)desc;
  181. /* Flush the DMA descriptor if we enabled dcache */
  182. flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
  183. writel(desc->address, &regs->lcdc_baseaddr);
  184. writel(desc->control, &regs->lcdc_basectrl);
  185. writel(desc->next, &regs->lcdc_basenext);
  186. writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
  187. &regs->lcdc_basecher);
  188. /* Enable LCD */
  189. value = readl(&regs->lcdc_lcden);
  190. writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
  191. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  192. true, 1000, false);
  193. if (ret)
  194. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  195. value = readl(&regs->lcdc_lcden);
  196. writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
  197. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  198. true, 1000, false);
  199. if (ret)
  200. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  201. value = readl(&regs->lcdc_lcden);
  202. writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
  203. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  204. true, 1000, false);
  205. if (ret)
  206. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  207. value = readl(&regs->lcdc_lcden);
  208. writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
  209. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  210. true, 1000, false);
  211. if (ret)
  212. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  213. /* Enable flushing if we enabled dcache */
  214. lcd_set_flush_dcache(1);
  215. }
  216. #else
  217. enum {
  218. LCD_MAX_WIDTH = 1024,
  219. LCD_MAX_HEIGHT = 768,
  220. LCD_MAX_LOG2_BPP = VIDEO_BPP16,
  221. };
  222. struct atmel_hlcdc_priv {
  223. struct atmel_hlcd_regs *regs;
  224. struct display_timing timing;
  225. unsigned int vl_bpix;
  226. unsigned int output_mode;
  227. unsigned int guard_time;
  228. ulong clk_rate;
  229. };
  230. static int at91_hlcdc_enable_clk(struct udevice *dev)
  231. {
  232. struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
  233. struct clk clk;
  234. ulong clk_rate;
  235. int ret;
  236. ret = clk_get_by_index(dev, 0, &clk);
  237. if (ret)
  238. return -EINVAL;
  239. ret = clk_enable(&clk);
  240. if (ret)
  241. return ret;
  242. clk_rate = clk_get_rate(&clk);
  243. if (!clk_rate) {
  244. clk_disable(&clk);
  245. return -ENODEV;
  246. }
  247. priv->clk_rate = clk_rate;
  248. clk_free(&clk);
  249. return 0;
  250. }
  251. static void atmel_hlcdc_init(struct udevice *dev)
  252. {
  253. struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
  254. struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
  255. struct atmel_hlcd_regs *regs = priv->regs;
  256. struct display_timing *timing = &priv->timing;
  257. struct lcd_dma_desc *desc;
  258. unsigned long value, vl_clk_pol;
  259. int ret;
  260. /* Disable DISP signal */
  261. writel(LCDC_LCDDIS_DISPDIS, &regs->lcdc_lcddis);
  262. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  263. false, 1000, false);
  264. if (ret)
  265. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  266. /* Disable synchronization */
  267. writel(LCDC_LCDDIS_SYNCDIS, &regs->lcdc_lcddis);
  268. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  269. false, 1000, false);
  270. if (ret)
  271. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  272. /* Disable pixel clock */
  273. writel(LCDC_LCDDIS_CLKDIS, &regs->lcdc_lcddis);
  274. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  275. false, 1000, false);
  276. if (ret)
  277. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  278. /* Disable PWM */
  279. writel(LCDC_LCDDIS_PWMDIS, &regs->lcdc_lcddis);
  280. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  281. false, 1000, false);
  282. if (ret)
  283. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  284. /* Set pixel clock */
  285. value = priv->clk_rate / timing->pixelclock.typ;
  286. if (priv->clk_rate % timing->pixelclock.typ)
  287. value++;
  288. vl_clk_pol = 0;
  289. if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
  290. vl_clk_pol = LCDC_LCDCFG0_CLKPOL;
  291. if (value < 1) {
  292. /* Using system clock as pixel clock */
  293. writel(LCDC_LCDCFG0_CLKDIV(0)
  294. | LCDC_LCDCFG0_CGDISHCR
  295. | LCDC_LCDCFG0_CGDISHEO
  296. | LCDC_LCDCFG0_CGDISOVR1
  297. | LCDC_LCDCFG0_CGDISBASE
  298. | vl_clk_pol
  299. | LCDC_LCDCFG0_CLKSEL,
  300. &regs->lcdc_lcdcfg0);
  301. } else {
  302. writel(LCDC_LCDCFG0_CLKDIV(value - 2)
  303. | LCDC_LCDCFG0_CGDISHCR
  304. | LCDC_LCDCFG0_CGDISHEO
  305. | LCDC_LCDCFG0_CGDISOVR1
  306. | LCDC_LCDCFG0_CGDISBASE
  307. | vl_clk_pol,
  308. &regs->lcdc_lcdcfg0);
  309. }
  310. /* Initialize control register 5 */
  311. value = 0;
  312. if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))
  313. value |= LCDC_LCDCFG5_HSPOL;
  314. if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))
  315. value |= LCDC_LCDCFG5_VSPOL;
  316. switch (priv->output_mode) {
  317. case 12:
  318. value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP;
  319. break;
  320. case 16:
  321. value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP;
  322. break;
  323. case 18:
  324. value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP;
  325. break;
  326. case 24:
  327. value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP;
  328. break;
  329. default:
  330. BUG();
  331. break;
  332. }
  333. value |= LCDC_LCDCFG5_GUARDTIME(priv->guard_time);
  334. value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS);
  335. writel(value, &regs->lcdc_lcdcfg5);
  336. /* Vertical & Horizontal Timing */
  337. value = LCDC_LCDCFG1_VSPW(timing->vsync_len.typ - 1);
  338. value |= LCDC_LCDCFG1_HSPW(timing->hsync_len.typ - 1);
  339. writel(value, &regs->lcdc_lcdcfg1);
  340. value = LCDC_LCDCFG2_VBPW(timing->vback_porch.typ);
  341. value |= LCDC_LCDCFG2_VFPW(timing->vfront_porch.typ - 1);
  342. writel(value, &regs->lcdc_lcdcfg2);
  343. value = LCDC_LCDCFG3_HBPW(timing->hback_porch.typ - 1);
  344. value |= LCDC_LCDCFG3_HFPW(timing->hfront_porch.typ - 1);
  345. writel(value, &regs->lcdc_lcdcfg3);
  346. /* Display size */
  347. value = LCDC_LCDCFG4_RPF(timing->vactive.typ - 1);
  348. value |= LCDC_LCDCFG4_PPL(timing->hactive.typ - 1);
  349. writel(value, &regs->lcdc_lcdcfg4);
  350. writel(LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO,
  351. &regs->lcdc_basecfg0);
  352. switch (VNBITS(priv->vl_bpix)) {
  353. case 16:
  354. writel(LCDC_BASECFG1_RGBMODE_16BPP_RGB_565,
  355. &regs->lcdc_basecfg1);
  356. break;
  357. case 32:
  358. writel(LCDC_BASECFG1_RGBMODE_24BPP_RGB_888,
  359. &regs->lcdc_basecfg1);
  360. break;
  361. default:
  362. BUG();
  363. break;
  364. }
  365. writel(LCDC_BASECFG2_XSTRIDE(0), &regs->lcdc_basecfg2);
  366. writel(0, &regs->lcdc_basecfg3);
  367. writel(LCDC_BASECFG4_DMA, &regs->lcdc_basecfg4);
  368. /* Disable all interrupts */
  369. writel(~0UL, &regs->lcdc_lcdidr);
  370. writel(~0UL, &regs->lcdc_baseidr);
  371. /* Setup the DMA descriptor, this descriptor will loop to itself */
  372. desc = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*desc));
  373. if (!desc)
  374. return;
  375. desc->address = (u32)uc_plat->base;
  376. /* Disable DMA transfer interrupt & descriptor loaded interrupt. */
  377. desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN
  378. | LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
  379. desc->next = (u32)desc;
  380. /* Flush the DMA descriptor if we enabled dcache */
  381. flush_dcache_range((u32)desc,
  382. ALIGN(((u32)desc + sizeof(*desc)),
  383. CONFIG_SYS_CACHELINE_SIZE));
  384. writel(desc->address, &regs->lcdc_baseaddr);
  385. writel(desc->control, &regs->lcdc_basectrl);
  386. writel(desc->next, &regs->lcdc_basenext);
  387. writel(LCDC_BASECHER_CHEN | LCDC_BASECHER_UPDATEEN,
  388. &regs->lcdc_basecher);
  389. /* Enable LCD */
  390. value = readl(&regs->lcdc_lcden);
  391. writel(value | LCDC_LCDEN_CLKEN, &regs->lcdc_lcden);
  392. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_CLKSTS,
  393. true, 1000, false);
  394. if (ret)
  395. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  396. value = readl(&regs->lcdc_lcden);
  397. writel(value | LCDC_LCDEN_SYNCEN, &regs->lcdc_lcden);
  398. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_LCDSTS,
  399. true, 1000, false);
  400. if (ret)
  401. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  402. value = readl(&regs->lcdc_lcden);
  403. writel(value | LCDC_LCDEN_DISPEN, &regs->lcdc_lcden);
  404. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_DISPSTS,
  405. true, 1000, false);
  406. if (ret)
  407. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  408. value = readl(&regs->lcdc_lcden);
  409. writel(value | LCDC_LCDEN_PWMEN, &regs->lcdc_lcden);
  410. ret = wait_for_bit_le32(&regs->lcdc_lcdsr, LCDC_LCDSR_PWMSTS,
  411. true, 1000, false);
  412. if (ret)
  413. printf("%s: %d: Timeout!\n", __func__, __LINE__);
  414. }
  415. static int atmel_hlcdc_probe(struct udevice *dev)
  416. {
  417. struct video_priv *uc_priv = dev_get_uclass_priv(dev);
  418. struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
  419. int ret;
  420. ret = at91_hlcdc_enable_clk(dev);
  421. if (ret)
  422. return ret;
  423. atmel_hlcdc_init(dev);
  424. uc_priv->xsize = priv->timing.hactive.typ;
  425. uc_priv->ysize = priv->timing.vactive.typ;
  426. uc_priv->bpix = priv->vl_bpix;
  427. /* Enable flushing if we enabled dcache */
  428. video_set_flush_dcache(dev, true);
  429. return 0;
  430. }
  431. static int atmel_hlcdc_of_to_plat(struct udevice *dev)
  432. {
  433. struct atmel_hlcdc_priv *priv = dev_get_priv(dev);
  434. const void *blob = gd->fdt_blob;
  435. int node = dev_of_offset(dev);
  436. priv->regs = dev_read_addr_ptr(dev);
  437. if (!priv->regs) {
  438. debug("%s: No display controller address\n", __func__);
  439. return -EINVAL;
  440. }
  441. if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
  442. 0, &priv->timing)) {
  443. debug("%s: Failed to decode display timing\n", __func__);
  444. return -EINVAL;
  445. }
  446. if (priv->timing.hactive.typ > LCD_MAX_WIDTH)
  447. priv->timing.hactive.typ = LCD_MAX_WIDTH;
  448. if (priv->timing.vactive.typ > LCD_MAX_HEIGHT)
  449. priv->timing.vactive.typ = LCD_MAX_HEIGHT;
  450. priv->vl_bpix = fdtdec_get_int(blob, node, "atmel,vl-bpix", 0);
  451. if (!priv->vl_bpix) {
  452. debug("%s: Failed to get bits per pixel\n", __func__);
  453. return -EINVAL;
  454. }
  455. priv->output_mode = fdtdec_get_int(blob, node, "atmel,output-mode", 24);
  456. priv->guard_time = fdtdec_get_int(blob, node, "atmel,guard-time", 1);
  457. return 0;
  458. }
  459. static int atmel_hlcdc_bind(struct udevice *dev)
  460. {
  461. struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
  462. uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
  463. (1 << LCD_MAX_LOG2_BPP) / 8;
  464. debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);
  465. return 0;
  466. }
  467. static const struct udevice_id atmel_hlcdc_ids[] = {
  468. { .compatible = "atmel,sama5d2-hlcdc" },
  469. { .compatible = "atmel,at91sam9x5-hlcdc" },
  470. { }
  471. };
  472. U_BOOT_DRIVER(atmel_hlcdfb) = {
  473. .name = "atmel_hlcdfb",
  474. .id = UCLASS_VIDEO,
  475. .of_match = atmel_hlcdc_ids,
  476. .bind = atmel_hlcdc_bind,
  477. .probe = atmel_hlcdc_probe,
  478. .of_to_plat = atmel_hlcdc_of_to_plat,
  479. .priv_auto = sizeof(struct atmel_hlcdc_priv),
  480. };
  481. #endif