ufs.c 49 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**
  3. * ufs.c - Universal Flash Subsystem (UFS) driver
  4. *
  5. * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported
  6. * to u-boot.
  7. *
  8. * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
  9. */
  10. #include <charset.h>
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <log.h>
  14. #include <dm/device_compat.h>
  15. #include <dm/devres.h>
  16. #include <dm/lists.h>
  17. #include <dm/device-internal.h>
  18. #include <malloc.h>
  19. #include <hexdump.h>
  20. #include <scsi.h>
  21. #include <asm/io.h>
  22. #include <asm/dma-mapping.h>
  23. #include <linux/bitops.h>
  24. #include <linux/delay.h>
  25. #include <linux/dma-mapping.h>
  26. #include "ufs.h"
  27. #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
  28. UTP_TASK_REQ_COMPL |\
  29. UFSHCD_ERROR_MASK)
  30. /* maximum number of link-startup retries */
  31. #define DME_LINKSTARTUP_RETRIES 3
  32. /* maximum number of retries for a general UIC command */
  33. #define UFS_UIC_COMMAND_RETRIES 3
  34. /* Query request retries */
  35. #define QUERY_REQ_RETRIES 3
  36. /* Query request timeout */
  37. #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
  38. /* maximum timeout in ms for a general UIC command */
  39. #define UFS_UIC_CMD_TIMEOUT 1000
  40. /* NOP OUT retries waiting for NOP IN response */
  41. #define NOP_OUT_RETRIES 10
  42. /* Timeout after 30 msecs if NOP OUT hangs without response */
  43. #define NOP_OUT_TIMEOUT 30 /* msecs */
  44. /* Only use one Task Tag for all requests */
  45. #define TASK_TAG 0
  46. /* Expose the flag value from utp_upiu_query.value */
  47. #define MASK_QUERY_UPIU_FLAG_LOC 0xFF
  48. #define MAX_PRDT_ENTRY 262144
  49. /* maximum bytes per request */
  50. #define UFS_MAX_BYTES (128 * 256 * 1024)
  51. static inline bool ufshcd_is_hba_active(struct ufs_hba *hba);
  52. static inline void ufshcd_hba_stop(struct ufs_hba *hba);
  53. static int ufshcd_hba_enable(struct ufs_hba *hba);
  54. /*
  55. * ufshcd_wait_for_register - wait for register value to change
  56. */
  57. static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
  58. u32 val, unsigned long timeout_ms)
  59. {
  60. int err = 0;
  61. unsigned long start = get_timer(0);
  62. /* ignore bits that we don't intend to wait on */
  63. val = val & mask;
  64. while ((ufshcd_readl(hba, reg) & mask) != val) {
  65. if (get_timer(start) > timeout_ms) {
  66. if ((ufshcd_readl(hba, reg) & mask) != val)
  67. err = -ETIMEDOUT;
  68. break;
  69. }
  70. }
  71. return err;
  72. }
  73. /**
  74. * ufshcd_init_pwr_info - setting the POR (power on reset)
  75. * values in hba power info
  76. */
  77. static void ufshcd_init_pwr_info(struct ufs_hba *hba)
  78. {
  79. hba->pwr_info.gear_rx = UFS_PWM_G1;
  80. hba->pwr_info.gear_tx = UFS_PWM_G1;
  81. hba->pwr_info.lane_rx = 1;
  82. hba->pwr_info.lane_tx = 1;
  83. hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
  84. hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
  85. hba->pwr_info.hs_rate = 0;
  86. }
  87. /**
  88. * ufshcd_print_pwr_info - print power params as saved in hba
  89. * power info
  90. */
  91. static void ufshcd_print_pwr_info(struct ufs_hba *hba)
  92. {
  93. static const char * const names[] = {
  94. "INVALID MODE",
  95. "FAST MODE",
  96. "SLOW_MODE",
  97. "INVALID MODE",
  98. "FASTAUTO_MODE",
  99. "SLOWAUTO_MODE",
  100. "INVALID MODE",
  101. };
  102. dev_err(hba->dev, "[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
  103. hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
  104. hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
  105. names[hba->pwr_info.pwr_rx],
  106. names[hba->pwr_info.pwr_tx],
  107. hba->pwr_info.hs_rate);
  108. }
  109. /**
  110. * ufshcd_ready_for_uic_cmd - Check if controller is ready
  111. * to accept UIC commands
  112. */
  113. static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
  114. {
  115. if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
  116. return true;
  117. else
  118. return false;
  119. }
  120. /**
  121. * ufshcd_get_uic_cmd_result - Get the UIC command result
  122. */
  123. static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
  124. {
  125. return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
  126. MASK_UIC_COMMAND_RESULT;
  127. }
  128. /**
  129. * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
  130. */
  131. static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
  132. {
  133. return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
  134. }
  135. /**
  136. * ufshcd_is_device_present - Check if any device connected to
  137. * the host controller
  138. */
  139. static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
  140. {
  141. return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
  142. DEVICE_PRESENT) ? true : false;
  143. }
  144. /**
  145. * ufshcd_send_uic_cmd - UFS Interconnect layer command API
  146. *
  147. */
  148. static int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
  149. {
  150. unsigned long start = 0;
  151. u32 intr_status;
  152. u32 enabled_intr_status;
  153. if (!ufshcd_ready_for_uic_cmd(hba)) {
  154. dev_err(hba->dev,
  155. "Controller not ready to accept UIC commands\n");
  156. return -EIO;
  157. }
  158. debug("sending uic command:%d\n", uic_cmd->command);
  159. /* Write Args */
  160. ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
  161. ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
  162. ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
  163. /* Write UIC Cmd */
  164. ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
  165. REG_UIC_COMMAND);
  166. start = get_timer(0);
  167. do {
  168. intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
  169. enabled_intr_status = intr_status & hba->intr_mask;
  170. ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
  171. if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) {
  172. dev_err(hba->dev,
  173. "Timedout waiting for UIC response\n");
  174. return -ETIMEDOUT;
  175. }
  176. if (enabled_intr_status & UFSHCD_ERROR_MASK) {
  177. dev_err(hba->dev, "Error in status:%08x\n",
  178. enabled_intr_status);
  179. return -1;
  180. }
  181. } while (!(enabled_intr_status & UFSHCD_UIC_MASK));
  182. uic_cmd->argument2 = ufshcd_get_uic_cmd_result(hba);
  183. uic_cmd->argument3 = ufshcd_get_dme_attr_val(hba);
  184. debug("Sent successfully\n");
  185. return 0;
  186. }
  187. /**
  188. * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
  189. *
  190. */
  191. int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, u8 attr_set,
  192. u32 mib_val, u8 peer)
  193. {
  194. struct uic_command uic_cmd = {0};
  195. static const char *const action[] = {
  196. "dme-set",
  197. "dme-peer-set"
  198. };
  199. const char *set = action[!!peer];
  200. int ret;
  201. int retries = UFS_UIC_COMMAND_RETRIES;
  202. uic_cmd.command = peer ?
  203. UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
  204. uic_cmd.argument1 = attr_sel;
  205. uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
  206. uic_cmd.argument3 = mib_val;
  207. do {
  208. /* for peer attributes we retry upon failure */
  209. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  210. if (ret)
  211. dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
  212. set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
  213. } while (ret && peer && --retries);
  214. if (ret)
  215. dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
  216. set, UIC_GET_ATTR_ID(attr_sel), mib_val,
  217. UFS_UIC_COMMAND_RETRIES - retries);
  218. return ret;
  219. }
  220. /**
  221. * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
  222. *
  223. */
  224. int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
  225. u32 *mib_val, u8 peer)
  226. {
  227. struct uic_command uic_cmd = {0};
  228. static const char *const action[] = {
  229. "dme-get",
  230. "dme-peer-get"
  231. };
  232. const char *get = action[!!peer];
  233. int ret;
  234. int retries = UFS_UIC_COMMAND_RETRIES;
  235. uic_cmd.command = peer ?
  236. UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
  237. uic_cmd.argument1 = attr_sel;
  238. do {
  239. /* for peer attributes we retry upon failure */
  240. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  241. if (ret)
  242. dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
  243. get, UIC_GET_ATTR_ID(attr_sel), ret);
  244. } while (ret && peer && --retries);
  245. if (ret)
  246. dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
  247. get, UIC_GET_ATTR_ID(attr_sel),
  248. UFS_UIC_COMMAND_RETRIES - retries);
  249. if (mib_val && !ret)
  250. *mib_val = uic_cmd.argument3;
  251. return ret;
  252. }
  253. static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
  254. {
  255. u32 tx_lanes, i, err = 0;
  256. if (!peer)
  257. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  258. &tx_lanes);
  259. else
  260. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  261. &tx_lanes);
  262. for (i = 0; i < tx_lanes; i++) {
  263. if (!peer)
  264. err = ufshcd_dme_set(hba,
  265. UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
  266. UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
  267. 0);
  268. else
  269. err = ufshcd_dme_peer_set(hba,
  270. UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
  271. UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
  272. 0);
  273. if (err) {
  274. dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
  275. __func__, peer, i, err);
  276. break;
  277. }
  278. }
  279. return err;
  280. }
  281. static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
  282. {
  283. return ufshcd_disable_tx_lcc(hba, true);
  284. }
  285. /**
  286. * ufshcd_dme_link_startup - Notify Unipro to perform link startup
  287. *
  288. */
  289. static int ufshcd_dme_link_startup(struct ufs_hba *hba)
  290. {
  291. struct uic_command uic_cmd = {0};
  292. int ret;
  293. uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
  294. ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
  295. if (ret)
  296. dev_dbg(hba->dev,
  297. "dme-link-startup: error code %d\n", ret);
  298. return ret;
  299. }
  300. /**
  301. * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
  302. *
  303. */
  304. static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
  305. {
  306. ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
  307. }
  308. /**
  309. * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
  310. */
  311. static inline int ufshcd_get_lists_status(u32 reg)
  312. {
  313. return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
  314. }
  315. /**
  316. * ufshcd_enable_run_stop_reg - Enable run-stop registers,
  317. * When run-stop registers are set to 1, it indicates the
  318. * host controller that it can process the requests
  319. */
  320. static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
  321. {
  322. ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
  323. REG_UTP_TASK_REQ_LIST_RUN_STOP);
  324. ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
  325. REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
  326. }
  327. /**
  328. * ufshcd_enable_intr - enable interrupts
  329. */
  330. static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
  331. {
  332. u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
  333. u32 rw;
  334. if (hba->version == UFSHCI_VERSION_10) {
  335. rw = set & INTERRUPT_MASK_RW_VER_10;
  336. set = rw | ((set ^ intrs) & intrs);
  337. } else {
  338. set |= intrs;
  339. }
  340. ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
  341. hba->intr_mask = set;
  342. }
  343. /**
  344. * ufshcd_make_hba_operational - Make UFS controller operational
  345. *
  346. * To bring UFS host controller to operational state,
  347. * 1. Enable required interrupts
  348. * 2. Configure interrupt aggregation
  349. * 3. Program UTRL and UTMRL base address
  350. * 4. Configure run-stop-registers
  351. *
  352. */
  353. static int ufshcd_make_hba_operational(struct ufs_hba *hba)
  354. {
  355. int err = 0;
  356. u32 reg;
  357. /* Enable required interrupts */
  358. ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
  359. /* Disable interrupt aggregation */
  360. ufshcd_disable_intr_aggr(hba);
  361. /* Configure UTRL and UTMRL base address registers */
  362. ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utrdl),
  363. REG_UTP_TRANSFER_REQ_LIST_BASE_L);
  364. ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utrdl),
  365. REG_UTP_TRANSFER_REQ_LIST_BASE_H);
  366. ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utmrdl),
  367. REG_UTP_TASK_REQ_LIST_BASE_L);
  368. ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl),
  369. REG_UTP_TASK_REQ_LIST_BASE_H);
  370. /*
  371. * UCRDY, UTMRLDY and UTRLRDY bits must be 1
  372. */
  373. reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
  374. if (!(ufshcd_get_lists_status(reg))) {
  375. ufshcd_enable_run_stop_reg(hba);
  376. } else {
  377. dev_err(hba->dev,
  378. "Host controller not ready to process requests");
  379. err = -EIO;
  380. goto out;
  381. }
  382. out:
  383. return err;
  384. }
  385. /**
  386. * ufshcd_link_startup - Initialize unipro link startup
  387. */
  388. static int ufshcd_link_startup(struct ufs_hba *hba)
  389. {
  390. int ret;
  391. int retries = DME_LINKSTARTUP_RETRIES;
  392. bool link_startup_again = true;
  393. link_startup:
  394. do {
  395. ufshcd_ops_link_startup_notify(hba, PRE_CHANGE);
  396. ret = ufshcd_dme_link_startup(hba);
  397. /* check if device is detected by inter-connect layer */
  398. if (!ret && !ufshcd_is_device_present(hba)) {
  399. dev_err(hba->dev, "%s: Device not present\n", __func__);
  400. ret = -ENXIO;
  401. goto out;
  402. }
  403. /*
  404. * DME link lost indication is only received when link is up,
  405. * but we can't be sure if the link is up until link startup
  406. * succeeds. So reset the local Uni-Pro and try again.
  407. */
  408. if (ret && ufshcd_hba_enable(hba))
  409. goto out;
  410. } while (ret && retries--);
  411. if (ret)
  412. /* failed to get the link up... retire */
  413. goto out;
  414. if (link_startup_again) {
  415. link_startup_again = false;
  416. retries = DME_LINKSTARTUP_RETRIES;
  417. goto link_startup;
  418. }
  419. /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
  420. ufshcd_init_pwr_info(hba);
  421. if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
  422. ret = ufshcd_disable_device_tx_lcc(hba);
  423. if (ret)
  424. goto out;
  425. }
  426. /* Include any host controller configuration via UIC commands */
  427. ret = ufshcd_ops_link_startup_notify(hba, POST_CHANGE);
  428. if (ret)
  429. goto out;
  430. ret = ufshcd_make_hba_operational(hba);
  431. out:
  432. if (ret)
  433. dev_err(hba->dev, "link startup failed %d\n", ret);
  434. return ret;
  435. }
  436. /**
  437. * ufshcd_hba_stop - Send controller to reset state
  438. */
  439. static inline void ufshcd_hba_stop(struct ufs_hba *hba)
  440. {
  441. int err;
  442. ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
  443. err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
  444. CONTROLLER_ENABLE, CONTROLLER_DISABLE,
  445. 10);
  446. if (err)
  447. dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
  448. }
  449. /**
  450. * ufshcd_is_hba_active - Get controller state
  451. */
  452. static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
  453. {
  454. return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
  455. ? false : true;
  456. }
  457. /**
  458. * ufshcd_hba_start - Start controller initialization sequence
  459. */
  460. static inline void ufshcd_hba_start(struct ufs_hba *hba)
  461. {
  462. ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
  463. }
  464. /**
  465. * ufshcd_hba_enable - initialize the controller
  466. */
  467. static int ufshcd_hba_enable(struct ufs_hba *hba)
  468. {
  469. int retry;
  470. if (!ufshcd_is_hba_active(hba))
  471. /* change controller state to "reset state" */
  472. ufshcd_hba_stop(hba);
  473. ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE);
  474. /* start controller initialization sequence */
  475. ufshcd_hba_start(hba);
  476. /*
  477. * To initialize a UFS host controller HCE bit must be set to 1.
  478. * During initialization the HCE bit value changes from 1->0->1.
  479. * When the host controller completes initialization sequence
  480. * it sets the value of HCE bit to 1. The same HCE bit is read back
  481. * to check if the controller has completed initialization sequence.
  482. * So without this delay the value HCE = 1, set in the previous
  483. * instruction might be read back.
  484. * This delay can be changed based on the controller.
  485. */
  486. mdelay(1);
  487. /* wait for the host controller to complete initialization */
  488. retry = 10;
  489. while (ufshcd_is_hba_active(hba)) {
  490. if (retry) {
  491. retry--;
  492. } else {
  493. dev_err(hba->dev, "Controller enable failed\n");
  494. return -EIO;
  495. }
  496. mdelay(5);
  497. }
  498. /* enable UIC related interrupts */
  499. ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
  500. ufshcd_ops_hce_enable_notify(hba, POST_CHANGE);
  501. return 0;
  502. }
  503. /**
  504. * ufshcd_host_memory_configure - configure local reference block with
  505. * memory offsets
  506. */
  507. static void ufshcd_host_memory_configure(struct ufs_hba *hba)
  508. {
  509. struct utp_transfer_req_desc *utrdlp;
  510. dma_addr_t cmd_desc_dma_addr;
  511. u16 response_offset;
  512. u16 prdt_offset;
  513. utrdlp = hba->utrdl;
  514. cmd_desc_dma_addr = (dma_addr_t)hba->ucdl;
  515. utrdlp->command_desc_base_addr_lo =
  516. cpu_to_le32(lower_32_bits(cmd_desc_dma_addr));
  517. utrdlp->command_desc_base_addr_hi =
  518. cpu_to_le32(upper_32_bits(cmd_desc_dma_addr));
  519. response_offset = offsetof(struct utp_transfer_cmd_desc, response_upiu);
  520. prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
  521. utrdlp->response_upiu_offset = cpu_to_le16(response_offset >> 2);
  522. utrdlp->prd_table_offset = cpu_to_le16(prdt_offset >> 2);
  523. utrdlp->response_upiu_length = cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
  524. hba->ucd_req_ptr = (struct utp_upiu_req *)hba->ucdl;
  525. hba->ucd_rsp_ptr =
  526. (struct utp_upiu_rsp *)&hba->ucdl->response_upiu;
  527. hba->ucd_prdt_ptr =
  528. (struct ufshcd_sg_entry *)&hba->ucdl->prd_table;
  529. }
  530. /**
  531. * ufshcd_memory_alloc - allocate memory for host memory space data structures
  532. */
  533. static int ufshcd_memory_alloc(struct ufs_hba *hba)
  534. {
  535. /* Allocate one Transfer Request Descriptor
  536. * Should be aligned to 1k boundary.
  537. */
  538. hba->utrdl = memalign(1024, sizeof(struct utp_transfer_req_desc));
  539. if (!hba->utrdl) {
  540. dev_err(hba->dev, "Transfer Descriptor memory allocation failed\n");
  541. return -ENOMEM;
  542. }
  543. /* Allocate one Command Descriptor
  544. * Should be aligned to 1k boundary.
  545. */
  546. hba->ucdl = memalign(1024, sizeof(struct utp_transfer_cmd_desc));
  547. if (!hba->ucdl) {
  548. dev_err(hba->dev, "Command descriptor memory allocation failed\n");
  549. return -ENOMEM;
  550. }
  551. return 0;
  552. }
  553. /**
  554. * ufshcd_get_intr_mask - Get the interrupt bit mask
  555. */
  556. static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
  557. {
  558. u32 intr_mask = 0;
  559. switch (hba->version) {
  560. case UFSHCI_VERSION_10:
  561. intr_mask = INTERRUPT_MASK_ALL_VER_10;
  562. break;
  563. case UFSHCI_VERSION_11:
  564. case UFSHCI_VERSION_20:
  565. intr_mask = INTERRUPT_MASK_ALL_VER_11;
  566. break;
  567. case UFSHCI_VERSION_21:
  568. default:
  569. intr_mask = INTERRUPT_MASK_ALL_VER_21;
  570. break;
  571. }
  572. return intr_mask;
  573. }
  574. /**
  575. * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
  576. */
  577. static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
  578. {
  579. return ufshcd_readl(hba, REG_UFS_VERSION);
  580. }
  581. /**
  582. * ufshcd_get_upmcrs - Get the power mode change request status
  583. */
  584. static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
  585. {
  586. return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
  587. }
  588. /**
  589. * ufshcd_prepare_req_desc_hdr() - Fills the requests header
  590. * descriptor according to request
  591. */
  592. static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc,
  593. u32 *upiu_flags,
  594. enum dma_data_direction cmd_dir)
  595. {
  596. u32 data_direction;
  597. u32 dword_0;
  598. if (cmd_dir == DMA_FROM_DEVICE) {
  599. data_direction = UTP_DEVICE_TO_HOST;
  600. *upiu_flags = UPIU_CMD_FLAGS_READ;
  601. } else if (cmd_dir == DMA_TO_DEVICE) {
  602. data_direction = UTP_HOST_TO_DEVICE;
  603. *upiu_flags = UPIU_CMD_FLAGS_WRITE;
  604. } else {
  605. data_direction = UTP_NO_DATA_TRANSFER;
  606. *upiu_flags = UPIU_CMD_FLAGS_NONE;
  607. }
  608. dword_0 = data_direction | (0x1 << UPIU_COMMAND_TYPE_OFFSET);
  609. /* Enable Interrupt for command */
  610. dword_0 |= UTP_REQ_DESC_INT_CMD;
  611. /* Transfer request descriptor header fields */
  612. req_desc->header.dword_0 = cpu_to_le32(dword_0);
  613. /* dword_1 is reserved, hence it is set to 0 */
  614. req_desc->header.dword_1 = 0;
  615. /*
  616. * assigning invalid value for command status. Controller
  617. * updates OCS on command completion, with the command
  618. * status
  619. */
  620. req_desc->header.dword_2 =
  621. cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
  622. /* dword_3 is reserved, hence it is set to 0 */
  623. req_desc->header.dword_3 = 0;
  624. req_desc->prd_table_length = 0;
  625. }
  626. static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
  627. u32 upiu_flags)
  628. {
  629. struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
  630. struct ufs_query *query = &hba->dev_cmd.query;
  631. u16 len = be16_to_cpu(query->request.upiu_req.length);
  632. /* Query request header */
  633. ucd_req_ptr->header.dword_0 =
  634. UPIU_HEADER_DWORD(UPIU_TRANSACTION_QUERY_REQ,
  635. upiu_flags, 0, TASK_TAG);
  636. ucd_req_ptr->header.dword_1 =
  637. UPIU_HEADER_DWORD(0, query->request.query_func,
  638. 0, 0);
  639. /* Data segment length only need for WRITE_DESC */
  640. if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
  641. ucd_req_ptr->header.dword_2 =
  642. UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
  643. else
  644. ucd_req_ptr->header.dword_2 = 0;
  645. /* Copy the Query Request buffer as is */
  646. memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, QUERY_OSF_SIZE);
  647. /* Copy the Descriptor */
  648. if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
  649. memcpy(ucd_req_ptr + 1, query->descriptor, len);
  650. memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
  651. }
  652. static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba)
  653. {
  654. struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
  655. memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
  656. /* command descriptor fields */
  657. ucd_req_ptr->header.dword_0 =
  658. UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT, 0, 0, 0x1f);
  659. /* clear rest of the fields of basic header */
  660. ucd_req_ptr->header.dword_1 = 0;
  661. ucd_req_ptr->header.dword_2 = 0;
  662. memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
  663. }
  664. /**
  665. * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
  666. * for Device Management Purposes
  667. */
  668. static int ufshcd_comp_devman_upiu(struct ufs_hba *hba,
  669. enum dev_cmd_type cmd_type)
  670. {
  671. u32 upiu_flags;
  672. int ret = 0;
  673. struct utp_transfer_req_desc *req_desc = hba->utrdl;
  674. hba->dev_cmd.type = cmd_type;
  675. ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, DMA_NONE);
  676. switch (cmd_type) {
  677. case DEV_CMD_TYPE_QUERY:
  678. ufshcd_prepare_utp_query_req_upiu(hba, upiu_flags);
  679. break;
  680. case DEV_CMD_TYPE_NOP:
  681. ufshcd_prepare_utp_nop_upiu(hba);
  682. break;
  683. default:
  684. ret = -EINVAL;
  685. }
  686. return ret;
  687. }
  688. static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
  689. {
  690. unsigned long start;
  691. u32 intr_status;
  692. u32 enabled_intr_status;
  693. ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
  694. start = get_timer(0);
  695. do {
  696. intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
  697. enabled_intr_status = intr_status & hba->intr_mask;
  698. ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
  699. if (get_timer(start) > QUERY_REQ_TIMEOUT) {
  700. dev_err(hba->dev,
  701. "Timedout waiting for UTP response\n");
  702. return -ETIMEDOUT;
  703. }
  704. if (enabled_intr_status & UFSHCD_ERROR_MASK) {
  705. dev_err(hba->dev, "Error in status:%08x\n",
  706. enabled_intr_status);
  707. return -1;
  708. }
  709. } while (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL));
  710. return 0;
  711. }
  712. /**
  713. * ufshcd_get_req_rsp - returns the TR response transaction type
  714. */
  715. static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
  716. {
  717. return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
  718. }
  719. /**
  720. * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
  721. *
  722. */
  723. static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba)
  724. {
  725. return le32_to_cpu(hba->utrdl->header.dword_2) & MASK_OCS;
  726. }
  727. static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
  728. {
  729. return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
  730. }
  731. static int ufshcd_check_query_response(struct ufs_hba *hba)
  732. {
  733. struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
  734. /* Get the UPIU response */
  735. query_res->response = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr) >>
  736. UPIU_RSP_CODE_OFFSET;
  737. return query_res->response;
  738. }
  739. /**
  740. * ufshcd_copy_query_response() - Copy the Query Response and the data
  741. * descriptor
  742. */
  743. static int ufshcd_copy_query_response(struct ufs_hba *hba)
  744. {
  745. struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
  746. memcpy(&query_res->upiu_res, &hba->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
  747. /* Get the descriptor */
  748. if (hba->dev_cmd.query.descriptor &&
  749. hba->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
  750. u8 *descp = (u8 *)hba->ucd_rsp_ptr +
  751. GENERAL_UPIU_REQUEST_SIZE;
  752. u16 resp_len;
  753. u16 buf_len;
  754. /* data segment length */
  755. resp_len = be32_to_cpu(hba->ucd_rsp_ptr->header.dword_2) &
  756. MASK_QUERY_DATA_SEG_LEN;
  757. buf_len =
  758. be16_to_cpu(hba->dev_cmd.query.request.upiu_req.length);
  759. if (likely(buf_len >= resp_len)) {
  760. memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
  761. } else {
  762. dev_warn(hba->dev,
  763. "%s: Response size is bigger than buffer",
  764. __func__);
  765. return -EINVAL;
  766. }
  767. }
  768. return 0;
  769. }
  770. /**
  771. * ufshcd_exec_dev_cmd - API for sending device management requests
  772. */
  773. static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, enum dev_cmd_type cmd_type,
  774. int timeout)
  775. {
  776. int err;
  777. int resp;
  778. err = ufshcd_comp_devman_upiu(hba, cmd_type);
  779. if (err)
  780. return err;
  781. err = ufshcd_send_command(hba, TASK_TAG);
  782. if (err)
  783. return err;
  784. err = ufshcd_get_tr_ocs(hba);
  785. if (err) {
  786. dev_err(hba->dev, "Error in OCS:%d\n", err);
  787. return -EINVAL;
  788. }
  789. resp = ufshcd_get_req_rsp(hba->ucd_rsp_ptr);
  790. switch (resp) {
  791. case UPIU_TRANSACTION_NOP_IN:
  792. break;
  793. case UPIU_TRANSACTION_QUERY_RSP:
  794. err = ufshcd_check_query_response(hba);
  795. if (!err)
  796. err = ufshcd_copy_query_response(hba);
  797. break;
  798. case UPIU_TRANSACTION_REJECT_UPIU:
  799. /* TODO: handle Reject UPIU Response */
  800. err = -EPERM;
  801. dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
  802. __func__);
  803. break;
  804. default:
  805. err = -EINVAL;
  806. dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
  807. __func__, resp);
  808. }
  809. return err;
  810. }
  811. /**
  812. * ufshcd_init_query() - init the query response and request parameters
  813. */
  814. static inline void ufshcd_init_query(struct ufs_hba *hba,
  815. struct ufs_query_req **request,
  816. struct ufs_query_res **response,
  817. enum query_opcode opcode,
  818. u8 idn, u8 index, u8 selector)
  819. {
  820. *request = &hba->dev_cmd.query.request;
  821. *response = &hba->dev_cmd.query.response;
  822. memset(*request, 0, sizeof(struct ufs_query_req));
  823. memset(*response, 0, sizeof(struct ufs_query_res));
  824. (*request)->upiu_req.opcode = opcode;
  825. (*request)->upiu_req.idn = idn;
  826. (*request)->upiu_req.index = index;
  827. (*request)->upiu_req.selector = selector;
  828. }
  829. /**
  830. * ufshcd_query_flag() - API function for sending flag query requests
  831. */
  832. int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
  833. enum flag_idn idn, bool *flag_res)
  834. {
  835. struct ufs_query_req *request = NULL;
  836. struct ufs_query_res *response = NULL;
  837. int err, index = 0, selector = 0;
  838. int timeout = QUERY_REQ_TIMEOUT;
  839. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  840. selector);
  841. switch (opcode) {
  842. case UPIU_QUERY_OPCODE_SET_FLAG:
  843. case UPIU_QUERY_OPCODE_CLEAR_FLAG:
  844. case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
  845. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  846. break;
  847. case UPIU_QUERY_OPCODE_READ_FLAG:
  848. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  849. if (!flag_res) {
  850. /* No dummy reads */
  851. dev_err(hba->dev, "%s: Invalid argument for read request\n",
  852. __func__);
  853. err = -EINVAL;
  854. goto out;
  855. }
  856. break;
  857. default:
  858. dev_err(hba->dev,
  859. "%s: Expected query flag opcode but got = %d\n",
  860. __func__, opcode);
  861. err = -EINVAL;
  862. goto out;
  863. }
  864. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
  865. if (err) {
  866. dev_err(hba->dev,
  867. "%s: Sending flag query for idn %d failed, err = %d\n",
  868. __func__, idn, err);
  869. goto out;
  870. }
  871. if (flag_res)
  872. *flag_res = (be32_to_cpu(response->upiu_res.value) &
  873. MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
  874. out:
  875. return err;
  876. }
  877. static int ufshcd_query_flag_retry(struct ufs_hba *hba,
  878. enum query_opcode opcode,
  879. enum flag_idn idn, bool *flag_res)
  880. {
  881. int ret;
  882. int retries;
  883. for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
  884. ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
  885. if (ret)
  886. dev_dbg(hba->dev,
  887. "%s: failed with error %d, retries %d\n",
  888. __func__, ret, retries);
  889. else
  890. break;
  891. }
  892. if (ret)
  893. dev_err(hba->dev,
  894. "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
  895. __func__, opcode, idn, ret, retries);
  896. return ret;
  897. }
  898. static int __ufshcd_query_descriptor(struct ufs_hba *hba,
  899. enum query_opcode opcode,
  900. enum desc_idn idn, u8 index, u8 selector,
  901. u8 *desc_buf, int *buf_len)
  902. {
  903. struct ufs_query_req *request = NULL;
  904. struct ufs_query_res *response = NULL;
  905. int err;
  906. if (!desc_buf) {
  907. dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
  908. __func__, opcode);
  909. err = -EINVAL;
  910. goto out;
  911. }
  912. if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
  913. dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
  914. __func__, *buf_len);
  915. err = -EINVAL;
  916. goto out;
  917. }
  918. ufshcd_init_query(hba, &request, &response, opcode, idn, index,
  919. selector);
  920. hba->dev_cmd.query.descriptor = desc_buf;
  921. request->upiu_req.length = cpu_to_be16(*buf_len);
  922. switch (opcode) {
  923. case UPIU_QUERY_OPCODE_WRITE_DESC:
  924. request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
  925. break;
  926. case UPIU_QUERY_OPCODE_READ_DESC:
  927. request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
  928. break;
  929. default:
  930. dev_err(hba->dev, "%s: Expected query descriptor opcode but got = 0x%.2x\n",
  931. __func__, opcode);
  932. err = -EINVAL;
  933. goto out;
  934. }
  935. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
  936. if (err) {
  937. dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
  938. __func__, opcode, idn, index, err);
  939. goto out;
  940. }
  941. hba->dev_cmd.query.descriptor = NULL;
  942. *buf_len = be16_to_cpu(response->upiu_res.length);
  943. out:
  944. return err;
  945. }
  946. /**
  947. * ufshcd_query_descriptor_retry - API function for sending descriptor requests
  948. */
  949. int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode,
  950. enum desc_idn idn, u8 index, u8 selector,
  951. u8 *desc_buf, int *buf_len)
  952. {
  953. int err;
  954. int retries;
  955. for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
  956. err = __ufshcd_query_descriptor(hba, opcode, idn, index,
  957. selector, desc_buf, buf_len);
  958. if (!err || err == -EINVAL)
  959. break;
  960. }
  961. return err;
  962. }
  963. /**
  964. * ufshcd_read_desc_length - read the specified descriptor length from header
  965. */
  966. static int ufshcd_read_desc_length(struct ufs_hba *hba, enum desc_idn desc_id,
  967. int desc_index, int *desc_length)
  968. {
  969. int ret;
  970. u8 header[QUERY_DESC_HDR_SIZE];
  971. int header_len = QUERY_DESC_HDR_SIZE;
  972. if (desc_id >= QUERY_DESC_IDN_MAX)
  973. return -EINVAL;
  974. ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
  975. desc_id, desc_index, 0, header,
  976. &header_len);
  977. if (ret) {
  978. dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
  979. __func__, desc_id);
  980. return ret;
  981. } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
  982. dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
  983. __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
  984. desc_id);
  985. ret = -EINVAL;
  986. }
  987. *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
  988. return ret;
  989. }
  990. static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
  991. {
  992. int err;
  993. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
  994. &hba->desc_size.dev_desc);
  995. if (err)
  996. hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
  997. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
  998. &hba->desc_size.pwr_desc);
  999. if (err)
  1000. hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
  1001. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
  1002. &hba->desc_size.interc_desc);
  1003. if (err)
  1004. hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
  1005. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
  1006. &hba->desc_size.conf_desc);
  1007. if (err)
  1008. hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
  1009. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
  1010. &hba->desc_size.unit_desc);
  1011. if (err)
  1012. hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
  1013. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
  1014. &hba->desc_size.geom_desc);
  1015. if (err)
  1016. hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
  1017. err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
  1018. &hba->desc_size.hlth_desc);
  1019. if (err)
  1020. hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
  1021. }
  1022. /**
  1023. * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
  1024. *
  1025. */
  1026. int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
  1027. int *desc_len)
  1028. {
  1029. switch (desc_id) {
  1030. case QUERY_DESC_IDN_DEVICE:
  1031. *desc_len = hba->desc_size.dev_desc;
  1032. break;
  1033. case QUERY_DESC_IDN_POWER:
  1034. *desc_len = hba->desc_size.pwr_desc;
  1035. break;
  1036. case QUERY_DESC_IDN_GEOMETRY:
  1037. *desc_len = hba->desc_size.geom_desc;
  1038. break;
  1039. case QUERY_DESC_IDN_CONFIGURATION:
  1040. *desc_len = hba->desc_size.conf_desc;
  1041. break;
  1042. case QUERY_DESC_IDN_UNIT:
  1043. *desc_len = hba->desc_size.unit_desc;
  1044. break;
  1045. case QUERY_DESC_IDN_INTERCONNECT:
  1046. *desc_len = hba->desc_size.interc_desc;
  1047. break;
  1048. case QUERY_DESC_IDN_STRING:
  1049. *desc_len = QUERY_DESC_MAX_SIZE;
  1050. break;
  1051. case QUERY_DESC_IDN_HEALTH:
  1052. *desc_len = hba->desc_size.hlth_desc;
  1053. break;
  1054. case QUERY_DESC_IDN_RFU_0:
  1055. case QUERY_DESC_IDN_RFU_1:
  1056. *desc_len = 0;
  1057. break;
  1058. default:
  1059. *desc_len = 0;
  1060. return -EINVAL;
  1061. }
  1062. return 0;
  1063. }
  1064. EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
  1065. /**
  1066. * ufshcd_read_desc_param - read the specified descriptor parameter
  1067. *
  1068. */
  1069. int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id,
  1070. int desc_index, u8 param_offset, u8 *param_read_buf,
  1071. u8 param_size)
  1072. {
  1073. int ret;
  1074. u8 *desc_buf;
  1075. int buff_len;
  1076. bool is_kmalloc = true;
  1077. /* Safety check */
  1078. if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
  1079. return -EINVAL;
  1080. /* Get the max length of descriptor from structure filled up at probe
  1081. * time.
  1082. */
  1083. ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
  1084. /* Sanity checks */
  1085. if (ret || !buff_len) {
  1086. dev_err(hba->dev, "%s: Failed to get full descriptor length",
  1087. __func__);
  1088. return ret;
  1089. }
  1090. /* Check whether we need temp memory */
  1091. if (param_offset != 0 || param_size < buff_len) {
  1092. desc_buf = kmalloc(buff_len, GFP_KERNEL);
  1093. if (!desc_buf)
  1094. return -ENOMEM;
  1095. } else {
  1096. desc_buf = param_read_buf;
  1097. is_kmalloc = false;
  1098. }
  1099. /* Request for full descriptor */
  1100. ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
  1101. desc_id, desc_index, 0, desc_buf,
  1102. &buff_len);
  1103. if (ret) {
  1104. dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
  1105. __func__, desc_id, desc_index, param_offset, ret);
  1106. goto out;
  1107. }
  1108. /* Sanity check */
  1109. if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
  1110. dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
  1111. __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
  1112. ret = -EINVAL;
  1113. goto out;
  1114. }
  1115. /* Check wherher we will not copy more data, than available */
  1116. if (is_kmalloc && param_size > buff_len)
  1117. param_size = buff_len;
  1118. if (is_kmalloc)
  1119. memcpy(param_read_buf, &desc_buf[param_offset], param_size);
  1120. out:
  1121. if (is_kmalloc)
  1122. kfree(desc_buf);
  1123. return ret;
  1124. }
  1125. /* replace non-printable or non-ASCII characters with spaces */
  1126. static inline void ufshcd_remove_non_printable(uint8_t *val)
  1127. {
  1128. if (!val)
  1129. return;
  1130. if (*val < 0x20 || *val > 0x7e)
  1131. *val = ' ';
  1132. }
  1133. /**
  1134. * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
  1135. * state) and waits for it to take effect.
  1136. *
  1137. */
  1138. static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
  1139. {
  1140. unsigned long start = 0;
  1141. u8 status;
  1142. int ret;
  1143. ret = ufshcd_send_uic_cmd(hba, cmd);
  1144. if (ret) {
  1145. dev_err(hba->dev,
  1146. "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
  1147. cmd->command, cmd->argument3, ret);
  1148. return ret;
  1149. }
  1150. start = get_timer(0);
  1151. do {
  1152. status = ufshcd_get_upmcrs(hba);
  1153. if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) {
  1154. dev_err(hba->dev,
  1155. "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
  1156. cmd->command, status);
  1157. ret = (status != PWR_OK) ? status : -1;
  1158. break;
  1159. }
  1160. } while (status != PWR_LOCAL);
  1161. return ret;
  1162. }
  1163. /**
  1164. * ufshcd_uic_change_pwr_mode - Perform the UIC power mode change
  1165. * using DME_SET primitives.
  1166. */
  1167. static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
  1168. {
  1169. struct uic_command uic_cmd = {0};
  1170. int ret;
  1171. uic_cmd.command = UIC_CMD_DME_SET;
  1172. uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
  1173. uic_cmd.argument3 = mode;
  1174. ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
  1175. return ret;
  1176. }
  1177. static
  1178. void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba,
  1179. struct scsi_cmd *pccb, u32 upiu_flags)
  1180. {
  1181. struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
  1182. unsigned int cdb_len;
  1183. /* command descriptor fields */
  1184. ucd_req_ptr->header.dword_0 =
  1185. UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND, upiu_flags,
  1186. pccb->lun, TASK_TAG);
  1187. ucd_req_ptr->header.dword_1 =
  1188. UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
  1189. /* Total EHS length and Data segment length will be zero */
  1190. ucd_req_ptr->header.dword_2 = 0;
  1191. ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(pccb->datalen);
  1192. cdb_len = min_t(unsigned short, pccb->cmdlen, UFS_CDB_SIZE);
  1193. memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
  1194. memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len);
  1195. memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
  1196. }
  1197. static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry,
  1198. unsigned char *buf, ulong len)
  1199. {
  1200. entry->size = cpu_to_le32(len) | GENMASK(1, 0);
  1201. entry->base_addr = cpu_to_le32(lower_32_bits((unsigned long)buf));
  1202. entry->upper_addr = cpu_to_le32(upper_32_bits((unsigned long)buf));
  1203. }
  1204. static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb)
  1205. {
  1206. struct utp_transfer_req_desc *req_desc = hba->utrdl;
  1207. struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr;
  1208. ulong datalen = pccb->datalen;
  1209. int table_length;
  1210. u8 *buf;
  1211. int i;
  1212. if (!datalen) {
  1213. req_desc->prd_table_length = 0;
  1214. return;
  1215. }
  1216. table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY);
  1217. buf = pccb->pdata;
  1218. i = table_length;
  1219. while (--i) {
  1220. prepare_prdt_desc(&prd_table[table_length - i - 1], buf,
  1221. MAX_PRDT_ENTRY - 1);
  1222. buf += MAX_PRDT_ENTRY;
  1223. datalen -= MAX_PRDT_ENTRY;
  1224. }
  1225. prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1);
  1226. req_desc->prd_table_length = table_length;
  1227. }
  1228. static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb)
  1229. {
  1230. struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent);
  1231. struct utp_transfer_req_desc *req_desc = hba->utrdl;
  1232. u32 upiu_flags;
  1233. int ocs, result = 0;
  1234. u8 scsi_status;
  1235. ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, pccb->dma_dir);
  1236. ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags);
  1237. prepare_prdt_table(hba, pccb);
  1238. ufshcd_send_command(hba, TASK_TAG);
  1239. ocs = ufshcd_get_tr_ocs(hba);
  1240. switch (ocs) {
  1241. case OCS_SUCCESS:
  1242. result = ufshcd_get_req_rsp(hba->ucd_rsp_ptr);
  1243. switch (result) {
  1244. case UPIU_TRANSACTION_RESPONSE:
  1245. result = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr);
  1246. scsi_status = result & MASK_SCSI_STATUS;
  1247. if (scsi_status)
  1248. return -EINVAL;
  1249. break;
  1250. case UPIU_TRANSACTION_REJECT_UPIU:
  1251. /* TODO: handle Reject UPIU Response */
  1252. dev_err(hba->dev,
  1253. "Reject UPIU not fully implemented\n");
  1254. return -EINVAL;
  1255. default:
  1256. dev_err(hba->dev,
  1257. "Unexpected request response code = %x\n",
  1258. result);
  1259. return -EINVAL;
  1260. }
  1261. break;
  1262. default:
  1263. dev_err(hba->dev, "OCS error from controller = %x\n", ocs);
  1264. return -EINVAL;
  1265. }
  1266. return 0;
  1267. }
  1268. static inline int ufshcd_read_desc(struct ufs_hba *hba, enum desc_idn desc_id,
  1269. int desc_index, u8 *buf, u32 size)
  1270. {
  1271. return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
  1272. }
  1273. static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
  1274. {
  1275. return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
  1276. }
  1277. /**
  1278. * ufshcd_read_string_desc - read string descriptor
  1279. *
  1280. */
  1281. int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
  1282. u8 *buf, u32 size, bool ascii)
  1283. {
  1284. int err = 0;
  1285. err = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING, desc_index, buf,
  1286. size);
  1287. if (err) {
  1288. dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
  1289. __func__, QUERY_REQ_RETRIES, err);
  1290. goto out;
  1291. }
  1292. if (ascii) {
  1293. int desc_len;
  1294. int ascii_len;
  1295. int i;
  1296. u8 *buff_ascii;
  1297. desc_len = buf[0];
  1298. /* remove header and divide by 2 to move from UTF16 to UTF8 */
  1299. ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
  1300. if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
  1301. dev_err(hba->dev, "%s: buffer allocated size is too small\n",
  1302. __func__);
  1303. err = -ENOMEM;
  1304. goto out;
  1305. }
  1306. buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
  1307. if (!buff_ascii) {
  1308. err = -ENOMEM;
  1309. goto out;
  1310. }
  1311. /*
  1312. * the descriptor contains string in UTF16 format
  1313. * we need to convert to utf-8 so it can be displayed
  1314. */
  1315. utf16_to_utf8(buff_ascii,
  1316. (uint16_t *)&buf[QUERY_DESC_HDR_SIZE], ascii_len);
  1317. /* replace non-printable or non-ASCII characters with spaces */
  1318. for (i = 0; i < ascii_len; i++)
  1319. ufshcd_remove_non_printable(&buff_ascii[i]);
  1320. memset(buf + QUERY_DESC_HDR_SIZE, 0,
  1321. size - QUERY_DESC_HDR_SIZE);
  1322. memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
  1323. buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
  1324. kfree(buff_ascii);
  1325. }
  1326. out:
  1327. return err;
  1328. }
  1329. static int ufs_get_device_desc(struct ufs_hba *hba,
  1330. struct ufs_dev_desc *dev_desc)
  1331. {
  1332. int err;
  1333. size_t buff_len;
  1334. u8 model_index;
  1335. u8 *desc_buf;
  1336. buff_len = max_t(size_t, hba->desc_size.dev_desc,
  1337. QUERY_DESC_MAX_SIZE + 1);
  1338. desc_buf = kmalloc(buff_len, GFP_KERNEL);
  1339. if (!desc_buf) {
  1340. err = -ENOMEM;
  1341. goto out;
  1342. }
  1343. err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
  1344. if (err) {
  1345. dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
  1346. __func__, err);
  1347. goto out;
  1348. }
  1349. /*
  1350. * getting vendor (manufacturerID) and Bank Index in big endian
  1351. * format
  1352. */
  1353. dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
  1354. desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
  1355. model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
  1356. /* Zero-pad entire buffer for string termination. */
  1357. memset(desc_buf, 0, buff_len);
  1358. err = ufshcd_read_string_desc(hba, model_index, desc_buf,
  1359. QUERY_DESC_MAX_SIZE, true/*ASCII*/);
  1360. if (err) {
  1361. dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
  1362. __func__, err);
  1363. goto out;
  1364. }
  1365. desc_buf[QUERY_DESC_MAX_SIZE] = '\0';
  1366. strlcpy(dev_desc->model, (char *)(desc_buf + QUERY_DESC_HDR_SIZE),
  1367. min_t(u8, desc_buf[QUERY_DESC_LENGTH_OFFSET],
  1368. MAX_MODEL_LEN));
  1369. /* Null terminate the model string */
  1370. dev_desc->model[MAX_MODEL_LEN] = '\0';
  1371. out:
  1372. kfree(desc_buf);
  1373. return err;
  1374. }
  1375. /**
  1376. * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
  1377. */
  1378. static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
  1379. {
  1380. struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
  1381. if (hba->max_pwr_info.is_valid)
  1382. return 0;
  1383. pwr_info->pwr_tx = FAST_MODE;
  1384. pwr_info->pwr_rx = FAST_MODE;
  1385. pwr_info->hs_rate = PA_HS_MODE_B;
  1386. /* Get the connected lane count */
  1387. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
  1388. &pwr_info->lane_rx);
  1389. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
  1390. &pwr_info->lane_tx);
  1391. if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
  1392. dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
  1393. __func__, pwr_info->lane_rx, pwr_info->lane_tx);
  1394. return -EINVAL;
  1395. }
  1396. /*
  1397. * First, get the maximum gears of HS speed.
  1398. * If a zero value, it means there is no HSGEAR capability.
  1399. * Then, get the maximum gears of PWM speed.
  1400. */
  1401. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
  1402. if (!pwr_info->gear_rx) {
  1403. ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
  1404. &pwr_info->gear_rx);
  1405. if (!pwr_info->gear_rx) {
  1406. dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
  1407. __func__, pwr_info->gear_rx);
  1408. return -EINVAL;
  1409. }
  1410. pwr_info->pwr_rx = SLOW_MODE;
  1411. }
  1412. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
  1413. &pwr_info->gear_tx);
  1414. if (!pwr_info->gear_tx) {
  1415. ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
  1416. &pwr_info->gear_tx);
  1417. if (!pwr_info->gear_tx) {
  1418. dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
  1419. __func__, pwr_info->gear_tx);
  1420. return -EINVAL;
  1421. }
  1422. pwr_info->pwr_tx = SLOW_MODE;
  1423. }
  1424. hba->max_pwr_info.is_valid = true;
  1425. return 0;
  1426. }
  1427. static int ufshcd_change_power_mode(struct ufs_hba *hba,
  1428. struct ufs_pa_layer_attr *pwr_mode)
  1429. {
  1430. int ret;
  1431. /* if already configured to the requested pwr_mode */
  1432. if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
  1433. pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
  1434. pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
  1435. pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
  1436. pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
  1437. pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
  1438. pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
  1439. dev_dbg(hba->dev, "%s: power already configured\n", __func__);
  1440. return 0;
  1441. }
  1442. /*
  1443. * Configure attributes for power mode change with below.
  1444. * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
  1445. * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
  1446. * - PA_HSSERIES
  1447. */
  1448. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
  1449. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
  1450. pwr_mode->lane_rx);
  1451. if (pwr_mode->pwr_rx == FASTAUTO_MODE || pwr_mode->pwr_rx == FAST_MODE)
  1452. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
  1453. else
  1454. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
  1455. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
  1456. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
  1457. pwr_mode->lane_tx);
  1458. if (pwr_mode->pwr_tx == FASTAUTO_MODE || pwr_mode->pwr_tx == FAST_MODE)
  1459. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
  1460. else
  1461. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
  1462. if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
  1463. pwr_mode->pwr_tx == FASTAUTO_MODE ||
  1464. pwr_mode->pwr_rx == FAST_MODE ||
  1465. pwr_mode->pwr_tx == FAST_MODE)
  1466. ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
  1467. pwr_mode->hs_rate);
  1468. ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 |
  1469. pwr_mode->pwr_tx);
  1470. if (ret) {
  1471. dev_err(hba->dev,
  1472. "%s: power mode change failed %d\n", __func__, ret);
  1473. return ret;
  1474. }
  1475. /* Copy new Power Mode to power info */
  1476. memcpy(&hba->pwr_info, pwr_mode, sizeof(struct ufs_pa_layer_attr));
  1477. return ret;
  1478. }
  1479. /**
  1480. * ufshcd_verify_dev_init() - Verify device initialization
  1481. *
  1482. */
  1483. static int ufshcd_verify_dev_init(struct ufs_hba *hba)
  1484. {
  1485. int retries;
  1486. int err;
  1487. for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
  1488. err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
  1489. NOP_OUT_TIMEOUT);
  1490. if (!err || err == -ETIMEDOUT)
  1491. break;
  1492. dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
  1493. }
  1494. if (err)
  1495. dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
  1496. return err;
  1497. }
  1498. /**
  1499. * ufshcd_complete_dev_init() - checks device readiness
  1500. */
  1501. static int ufshcd_complete_dev_init(struct ufs_hba *hba)
  1502. {
  1503. int i;
  1504. int err;
  1505. bool flag_res = 1;
  1506. err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
  1507. QUERY_FLAG_IDN_FDEVICEINIT, NULL);
  1508. if (err) {
  1509. dev_err(hba->dev,
  1510. "%s setting fDeviceInit flag failed with error %d\n",
  1511. __func__, err);
  1512. goto out;
  1513. }
  1514. /* poll for max. 1000 iterations for fDeviceInit flag to clear */
  1515. for (i = 0; i < 1000 && !err && flag_res; i++)
  1516. err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
  1517. QUERY_FLAG_IDN_FDEVICEINIT,
  1518. &flag_res);
  1519. if (err)
  1520. dev_err(hba->dev,
  1521. "%s reading fDeviceInit flag failed with error %d\n",
  1522. __func__, err);
  1523. else if (flag_res)
  1524. dev_err(hba->dev,
  1525. "%s fDeviceInit was not cleared by the device\n",
  1526. __func__);
  1527. out:
  1528. return err;
  1529. }
  1530. static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
  1531. {
  1532. hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
  1533. hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
  1534. hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
  1535. hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
  1536. hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
  1537. hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
  1538. hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
  1539. }
  1540. int ufs_start(struct ufs_hba *hba)
  1541. {
  1542. struct ufs_dev_desc card = {0};
  1543. int ret;
  1544. ret = ufshcd_link_startup(hba);
  1545. if (ret)
  1546. return ret;
  1547. ret = ufshcd_verify_dev_init(hba);
  1548. if (ret)
  1549. return ret;
  1550. ret = ufshcd_complete_dev_init(hba);
  1551. if (ret)
  1552. return ret;
  1553. /* Init check for device descriptor sizes */
  1554. ufshcd_init_desc_sizes(hba);
  1555. ret = ufs_get_device_desc(hba, &card);
  1556. if (ret) {
  1557. dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
  1558. __func__, ret);
  1559. return ret;
  1560. }
  1561. if (ufshcd_get_max_pwr_mode(hba)) {
  1562. dev_err(hba->dev,
  1563. "%s: Failed getting max supported power mode\n",
  1564. __func__);
  1565. } else {
  1566. ret = ufshcd_change_power_mode(hba, &hba->max_pwr_info.info);
  1567. if (ret) {
  1568. dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
  1569. __func__, ret);
  1570. return ret;
  1571. }
  1572. printf("Device at %s up at:", hba->dev->name);
  1573. ufshcd_print_pwr_info(hba);
  1574. }
  1575. return 0;
  1576. }
  1577. int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
  1578. {
  1579. struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev);
  1580. struct scsi_plat *scsi_plat;
  1581. struct udevice *scsi_dev;
  1582. int err;
  1583. device_find_first_child(ufs_dev, &scsi_dev);
  1584. if (!scsi_dev)
  1585. return -ENODEV;
  1586. scsi_plat = dev_get_uclass_plat(scsi_dev);
  1587. scsi_plat->max_id = UFSHCD_MAX_ID;
  1588. scsi_plat->max_lun = UFS_MAX_LUNS;
  1589. scsi_plat->max_bytes_per_req = UFS_MAX_BYTES;
  1590. hba->dev = ufs_dev;
  1591. hba->ops = hba_ops;
  1592. hba->mmio_base = (void *)dev_read_addr(ufs_dev);
  1593. /* Set descriptor lengths to specification defaults */
  1594. ufshcd_def_desc_sizes(hba);
  1595. ufshcd_ops_init(hba);
  1596. /* Read capabilties registers */
  1597. hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
  1598. /* Get UFS version supported by the controller */
  1599. hba->version = ufshcd_get_ufs_version(hba);
  1600. if (hba->version != UFSHCI_VERSION_10 &&
  1601. hba->version != UFSHCI_VERSION_11 &&
  1602. hba->version != UFSHCI_VERSION_20 &&
  1603. hba->version != UFSHCI_VERSION_21)
  1604. dev_err(hba->dev, "invalid UFS version 0x%x\n",
  1605. hba->version);
  1606. /* Get Interrupt bit mask per version */
  1607. hba->intr_mask = ufshcd_get_intr_mask(hba);
  1608. /* Allocate memory for host memory space */
  1609. err = ufshcd_memory_alloc(hba);
  1610. if (err) {
  1611. dev_err(hba->dev, "Memory allocation failed\n");
  1612. return err;
  1613. }
  1614. /* Configure Local data structures */
  1615. ufshcd_host_memory_configure(hba);
  1616. /*
  1617. * In order to avoid any spurious interrupt immediately after
  1618. * registering UFS controller interrupt handler, clear any pending UFS
  1619. * interrupt status and disable all the UFS interrupts.
  1620. */
  1621. ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
  1622. REG_INTERRUPT_STATUS);
  1623. ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
  1624. err = ufshcd_hba_enable(hba);
  1625. if (err) {
  1626. dev_err(hba->dev, "Host controller enable failed\n");
  1627. return err;
  1628. }
  1629. err = ufs_start(hba);
  1630. if (err)
  1631. return err;
  1632. return 0;
  1633. }
  1634. int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp)
  1635. {
  1636. int ret = device_bind_driver(ufs_dev, "ufs_scsi", "ufs_scsi",
  1637. scsi_devp);
  1638. return ret;
  1639. }
  1640. static struct scsi_ops ufs_ops = {
  1641. .exec = ufs_scsi_exec,
  1642. };
  1643. int ufs_probe_dev(int index)
  1644. {
  1645. struct udevice *dev;
  1646. return uclass_get_device(UCLASS_UFS, index, &dev);
  1647. }
  1648. int ufs_probe(void)
  1649. {
  1650. struct udevice *dev;
  1651. int ret, i;
  1652. for (i = 0;; i++) {
  1653. ret = uclass_get_device(UCLASS_UFS, i, &dev);
  1654. if (ret == -ENODEV)
  1655. break;
  1656. }
  1657. return 0;
  1658. }
  1659. U_BOOT_DRIVER(ufs_scsi) = {
  1660. .id = UCLASS_SCSI,
  1661. .name = "ufs_scsi",
  1662. .ops = &ufs_ops,
  1663. };