serial_stm32.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
  4. * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
  5. */
  6. #define LOG_CATEGORY UCLASS_SERIAL
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <reset.h>
  12. #include <serial.h>
  13. #include <watchdog.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/stm32.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. #include "serial_stm32.h"
  20. #include <dm/device_compat.h>
  21. static void _stm32_serial_setbrg(fdt_addr_t base,
  22. struct stm32_uart_info *uart_info,
  23. u32 clock_rate,
  24. int baudrate)
  25. {
  26. bool stm32f4 = uart_info->stm32f4;
  27. u32 int_div, mantissa, fraction, oversampling;
  28. int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate);
  29. if (int_div < 16) {
  30. oversampling = 8;
  31. setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
  32. } else {
  33. oversampling = 16;
  34. clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
  35. }
  36. mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
  37. fraction = int_div % oversampling;
  38. writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
  39. }
  40. static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
  41. {
  42. struct stm32x7_serial_plat *plat = dev_get_plat(dev);
  43. _stm32_serial_setbrg(plat->base, plat->uart_info,
  44. plat->clock_rate, baudrate);
  45. return 0;
  46. }
  47. static int stm32_serial_setconfig(struct udevice *dev, uint serial_config)
  48. {
  49. struct stm32x7_serial_plat *plat = dev_get_plat(dev);
  50. bool stm32f4 = plat->uart_info->stm32f4;
  51. u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
  52. u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
  53. u32 config = 0;
  54. uint parity = SERIAL_GET_PARITY(serial_config);
  55. uint bits = SERIAL_GET_BITS(serial_config);
  56. uint stop = SERIAL_GET_STOP(serial_config);
  57. /*
  58. * only parity config is implemented, check if other serial settings
  59. * are the default one.
  60. * (STM32F4 serial IP didn't support parity setting)
  61. */
  62. if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP || stm32f4)
  63. return -ENOTSUPP; /* not supported in driver*/
  64. clrbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
  65. /* update usart configuration (uart need to be disable)
  66. * PCE: parity check enable
  67. * PS : '0' : Even / '1' : Odd
  68. * M[1:0] = '00' : 8 Data bits
  69. * M[1:0] = '01' : 9 Data bits with parity
  70. */
  71. switch (parity) {
  72. default:
  73. case SERIAL_PAR_NONE:
  74. config = 0;
  75. break;
  76. case SERIAL_PAR_ODD:
  77. config = USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0;
  78. break;
  79. case SERIAL_PAR_EVEN:
  80. config = USART_CR1_PCE | USART_CR1_M0;
  81. break;
  82. }
  83. clrsetbits_le32(cr1,
  84. USART_CR1_PCE | USART_CR1_PS | USART_CR1_M1 |
  85. USART_CR1_M0,
  86. config);
  87. setbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
  88. return 0;
  89. }
  90. static int stm32_serial_getc(struct udevice *dev)
  91. {
  92. struct stm32x7_serial_plat *plat = dev_get_plat(dev);
  93. bool stm32f4 = plat->uart_info->stm32f4;
  94. fdt_addr_t base = plat->base;
  95. u32 isr = readl(base + ISR_OFFSET(stm32f4));
  96. if ((isr & USART_ISR_RXNE) == 0)
  97. return -EAGAIN;
  98. if (isr & (USART_ISR_PE | USART_ISR_ORE | USART_ISR_FE)) {
  99. if (!stm32f4)
  100. setbits_le32(base + ICR_OFFSET,
  101. USART_ICR_PCECF | USART_ICR_ORECF |
  102. USART_ICR_FECF);
  103. else
  104. readl(base + RDR_OFFSET(stm32f4));
  105. return -EIO;
  106. }
  107. return readl(base + RDR_OFFSET(stm32f4));
  108. }
  109. static int _stm32_serial_putc(fdt_addr_t base,
  110. struct stm32_uart_info *uart_info,
  111. const char c)
  112. {
  113. bool stm32f4 = uart_info->stm32f4;
  114. if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_TXE) == 0)
  115. return -EAGAIN;
  116. writel(c, base + TDR_OFFSET(stm32f4));
  117. return 0;
  118. }
  119. static int stm32_serial_putc(struct udevice *dev, const char c)
  120. {
  121. struct stm32x7_serial_plat *plat = dev_get_plat(dev);
  122. return _stm32_serial_putc(plat->base, plat->uart_info, c);
  123. }
  124. static int stm32_serial_pending(struct udevice *dev, bool input)
  125. {
  126. struct stm32x7_serial_plat *plat = dev_get_plat(dev);
  127. bool stm32f4 = plat->uart_info->stm32f4;
  128. fdt_addr_t base = plat->base;
  129. if (input)
  130. return readl(base + ISR_OFFSET(stm32f4)) &
  131. USART_ISR_RXNE ? 1 : 0;
  132. else
  133. return readl(base + ISR_OFFSET(stm32f4)) &
  134. USART_ISR_TXE ? 0 : 1;
  135. }
  136. static void _stm32_serial_init(fdt_addr_t base,
  137. struct stm32_uart_info *uart_info)
  138. {
  139. bool stm32f4 = uart_info->stm32f4;
  140. u8 uart_enable_bit = uart_info->uart_enable_bit;
  141. /* Disable uart-> enable fifo -> enable uart */
  142. clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
  143. BIT(uart_enable_bit));
  144. if (uart_info->has_fifo)
  145. setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
  146. setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
  147. BIT(uart_enable_bit));
  148. }
  149. static int stm32_serial_probe(struct udevice *dev)
  150. {
  151. struct stm32x7_serial_plat *plat = dev_get_plat(dev);
  152. struct clk clk;
  153. struct reset_ctl reset;
  154. int ret;
  155. plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
  156. ret = clk_get_by_index(dev, 0, &clk);
  157. if (ret < 0)
  158. return ret;
  159. ret = clk_enable(&clk);
  160. if (ret) {
  161. dev_err(dev, "failed to enable clock\n");
  162. return ret;
  163. }
  164. ret = reset_get_by_index(dev, 0, &reset);
  165. if (!ret) {
  166. reset_assert(&reset);
  167. udelay(2);
  168. reset_deassert(&reset);
  169. }
  170. plat->clock_rate = clk_get_rate(&clk);
  171. if (!plat->clock_rate) {
  172. clk_disable(&clk);
  173. return -EINVAL;
  174. };
  175. _stm32_serial_init(plat->base, plat->uart_info);
  176. return 0;
  177. }
  178. static const struct udevice_id stm32_serial_id[] = {
  179. { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
  180. { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
  181. { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
  182. {}
  183. };
  184. static int stm32_serial_of_to_plat(struct udevice *dev)
  185. {
  186. struct stm32x7_serial_plat *plat = dev_get_plat(dev);
  187. plat->base = dev_read_addr(dev);
  188. if (plat->base == FDT_ADDR_T_NONE)
  189. return -EINVAL;
  190. return 0;
  191. }
  192. static const struct dm_serial_ops stm32_serial_ops = {
  193. .putc = stm32_serial_putc,
  194. .pending = stm32_serial_pending,
  195. .getc = stm32_serial_getc,
  196. .setbrg = stm32_serial_setbrg,
  197. .setconfig = stm32_serial_setconfig
  198. };
  199. U_BOOT_DRIVER(serial_stm32) = {
  200. .name = "serial_stm32",
  201. .id = UCLASS_SERIAL,
  202. .of_match = of_match_ptr(stm32_serial_id),
  203. .of_to_plat = of_match_ptr(stm32_serial_of_to_plat),
  204. .plat_auto = sizeof(struct stm32x7_serial_plat),
  205. .ops = &stm32_serial_ops,
  206. .probe = stm32_serial_probe,
  207. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  208. .flags = DM_FLAG_PRE_RELOC,
  209. #endif
  210. };
  211. #ifdef CONFIG_DEBUG_UART_STM32
  212. #include <debug_uart.h>
  213. static inline struct stm32_uart_info *_debug_uart_info(void)
  214. {
  215. struct stm32_uart_info *uart_info;
  216. #if defined(CONFIG_STM32F4)
  217. uart_info = &stm32f4_info;
  218. #elif defined(CONFIG_STM32F7)
  219. uart_info = &stm32f7_info;
  220. #else
  221. uart_info = &stm32h7_info;
  222. #endif
  223. return uart_info;
  224. }
  225. static inline void _debug_uart_init(void)
  226. {
  227. fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
  228. struct stm32_uart_info *uart_info = _debug_uart_info();
  229. _stm32_serial_init(base, uart_info);
  230. _stm32_serial_setbrg(base, uart_info,
  231. CONFIG_DEBUG_UART_CLOCK,
  232. CONFIG_BAUDRATE);
  233. }
  234. static inline void _debug_uart_putc(int c)
  235. {
  236. fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
  237. struct stm32_uart_info *uart_info = _debug_uart_info();
  238. while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
  239. ;
  240. }
  241. DEBUG_UART_FUNCS
  242. #endif