serial_bcm6345.c 8.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
  4. *
  5. * Derived from linux/drivers/tty/serial/bcm63xx_uart.c:
  6. * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  7. */
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <debug_uart.h>
  11. #include <errno.h>
  12. #include <malloc.h>
  13. #include <serial.h>
  14. #include <asm/io.h>
  15. #include <asm/types.h>
  16. /* UART Control register */
  17. #define UART_CTL_REG 0x0
  18. #define UART_CTL_RXTIMEOUT_MASK 0x1f
  19. #define UART_CTL_RXTIMEOUT_5 0x5
  20. #define UART_CTL_RSTRXFIFO_SHIFT 6
  21. #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
  22. #define UART_CTL_RSTTXFIFO_SHIFT 7
  23. #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
  24. #define UART_CTL_STOPBITS_SHIFT 8
  25. #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
  26. #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
  27. #define UART_CTL_BITSPERSYM_SHIFT 12
  28. #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
  29. #define UART_CTL_BITSPERSYM_8 (0x3 << UART_CTL_BITSPERSYM_SHIFT)
  30. #define UART_CTL_XMITBRK_SHIFT 14
  31. #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
  32. #define UART_CTL_RSVD_SHIFT 15
  33. #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
  34. #define UART_CTL_RXPAREVEN_SHIFT 16
  35. #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
  36. #define UART_CTL_RXPAREN_SHIFT 17
  37. #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
  38. #define UART_CTL_TXPAREVEN_SHIFT 18
  39. #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
  40. #define UART_CTL_TXPAREN_SHIFT 19
  41. #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
  42. #define UART_CTL_LOOPBACK_SHIFT 20
  43. #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
  44. #define UART_CTL_RXEN_SHIFT 21
  45. #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
  46. #define UART_CTL_TXEN_SHIFT 22
  47. #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
  48. #define UART_CTL_BRGEN_SHIFT 23
  49. #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
  50. /* UART Baudword register */
  51. #define UART_BAUD_REG 0x4
  52. /* UART FIFO Config register */
  53. #define UART_FIFO_CFG_REG 0x8
  54. #define UART_FIFO_CFG_RX_SHIFT 8
  55. #define UART_FIFO_CFG_RX_MASK (0xf << UART_FIFO_CFG_RX_SHIFT)
  56. #define UART_FIFO_CFG_RX_4 (0x4 << UART_FIFO_CFG_RX_SHIFT)
  57. #define UART_FIFO_CFG_TX_SHIFT 12
  58. #define UART_FIFO_CFG_TX_MASK (0xf << UART_FIFO_CFG_TX_SHIFT)
  59. #define UART_FIFO_CFG_TX_4 (0x4 << UART_FIFO_CFG_TX_SHIFT)
  60. /* UART Interrupt register */
  61. #define UART_IR_REG 0x10
  62. #define UART_IR_STAT(x) (1 << (x))
  63. #define UART_IR_TXEMPTY 5
  64. #define UART_IR_RXOVER 7
  65. #define UART_IR_RXNOTEMPTY 11
  66. /* UART FIFO register */
  67. #define UART_FIFO_REG 0x14
  68. #define UART_FIFO_VALID_MASK 0xff
  69. #define UART_FIFO_FRAMEERR_SHIFT 8
  70. #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
  71. #define UART_FIFO_PARERR_SHIFT 9
  72. #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
  73. #define UART_FIFO_BRKDET_SHIFT 10
  74. #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
  75. #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
  76. UART_FIFO_PARERR_MASK | \
  77. UART_FIFO_BRKDET_MASK)
  78. struct bcm6345_serial_priv {
  79. void __iomem *base;
  80. ulong uartclk;
  81. };
  82. /* enable rx & tx operation on uart */
  83. static void bcm6345_serial_enable(void __iomem *base)
  84. {
  85. setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
  86. UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
  87. }
  88. /* disable rx & tx operation on uart */
  89. static void bcm6345_serial_disable(void __iomem *base)
  90. {
  91. clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
  92. UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
  93. }
  94. /* clear all unread data in rx fifo and unsent data in tx fifo */
  95. static void bcm6345_serial_flush(void __iomem *base)
  96. {
  97. /* empty rx and tx fifo */
  98. setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK |
  99. UART_CTL_RSTTXFIFO_MASK);
  100. /* read any pending char to make sure all irq status are cleared */
  101. readl(base + UART_FIFO_REG);
  102. }
  103. static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate)
  104. {
  105. u32 val;
  106. /* mask all irq and flush port */
  107. bcm6345_serial_disable(base);
  108. bcm6345_serial_flush(base);
  109. /* set uart control config */
  110. clrsetbits_32(base + UART_CTL_REG,
  111. /* clear rx timeout */
  112. UART_CTL_RXTIMEOUT_MASK |
  113. /* clear stop bits */
  114. UART_CTL_STOPBITS_MASK |
  115. /* clear bits per symbol */
  116. UART_CTL_BITSPERSYM_MASK |
  117. /* clear xmit break */
  118. UART_CTL_XMITBRK_MASK |
  119. /* clear reserved bit */
  120. UART_CTL_RSVD_MASK |
  121. /* disable parity */
  122. UART_CTL_RXPAREN_MASK |
  123. UART_CTL_TXPAREN_MASK |
  124. /* disable loopback */
  125. UART_CTL_LOOPBACK_MASK,
  126. /* set timeout to 5 */
  127. UART_CTL_RXTIMEOUT_5 |
  128. /* set 8 bits/symbol */
  129. UART_CTL_BITSPERSYM_8 |
  130. /* set 1 stop bit */
  131. UART_CTL_STOPBITS_1 |
  132. /* set parity to even */
  133. UART_CTL_RXPAREVEN_MASK |
  134. UART_CTL_TXPAREVEN_MASK);
  135. /* set uart fifo config */
  136. clrsetbits_32(base + UART_FIFO_CFG_REG,
  137. /* clear fifo config */
  138. UART_FIFO_CFG_RX_MASK |
  139. UART_FIFO_CFG_TX_MASK,
  140. /* set fifo config to 4 */
  141. UART_FIFO_CFG_RX_4 |
  142. UART_FIFO_CFG_TX_4);
  143. /* set baud rate */
  144. val = ((clk / baudrate) >> 4);
  145. if (val & 0x1)
  146. val = (val >> 1);
  147. else
  148. val = (val >> 1) - 1;
  149. writel(val, base + UART_BAUD_REG);
  150. /* clear interrupts */
  151. writel(0, base + UART_IR_REG);
  152. /* enable uart */
  153. bcm6345_serial_enable(base);
  154. return 0;
  155. }
  156. static int bcm6345_serial_pending(struct udevice *dev, bool input)
  157. {
  158. struct bcm6345_serial_priv *priv = dev_get_priv(dev);
  159. u32 val = readl(priv->base + UART_IR_REG);
  160. if (input)
  161. return !!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY));
  162. else
  163. return !(val & UART_IR_STAT(UART_IR_TXEMPTY));
  164. }
  165. static int bcm6345_serial_setbrg(struct udevice *dev, int baudrate)
  166. {
  167. struct bcm6345_serial_priv *priv = dev_get_priv(dev);
  168. return bcm6345_serial_init(priv->base, priv->uartclk, baudrate);
  169. }
  170. static int bcm6345_serial_putc(struct udevice *dev, const char ch)
  171. {
  172. struct bcm6345_serial_priv *priv = dev_get_priv(dev);
  173. u32 val;
  174. val = readl(priv->base + UART_IR_REG);
  175. if (!(val & UART_IR_STAT(UART_IR_TXEMPTY)))
  176. return -EAGAIN;
  177. writel(ch, priv->base + UART_FIFO_REG);
  178. return 0;
  179. }
  180. static int bcm6345_serial_getc(struct udevice *dev)
  181. {
  182. struct bcm6345_serial_priv *priv = dev_get_priv(dev);
  183. u32 val;
  184. val = readl(priv->base + UART_IR_REG);
  185. if (val & UART_IR_STAT(UART_IR_RXOVER))
  186. setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK);
  187. if (!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
  188. return -EAGAIN;
  189. val = readl(priv->base + UART_FIFO_REG);
  190. if (val & UART_FIFO_ANYERR_MASK)
  191. return -EAGAIN;
  192. return val & UART_FIFO_VALID_MASK;
  193. }
  194. static int bcm6345_serial_probe(struct udevice *dev)
  195. {
  196. struct bcm6345_serial_priv *priv = dev_get_priv(dev);
  197. struct clk clk;
  198. int ret;
  199. /* get address */
  200. priv->base = dev_remap_addr(dev);
  201. if (!priv->base)
  202. return -EINVAL;
  203. /* get clock rate */
  204. ret = clk_get_by_index(dev, 0, &clk);
  205. if (ret < 0)
  206. return ret;
  207. priv->uartclk = clk_get_rate(&clk);
  208. clk_free(&clk);
  209. /* initialize serial */
  210. return bcm6345_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
  211. }
  212. static const struct dm_serial_ops bcm6345_serial_ops = {
  213. .putc = bcm6345_serial_putc,
  214. .pending = bcm6345_serial_pending,
  215. .getc = bcm6345_serial_getc,
  216. .setbrg = bcm6345_serial_setbrg,
  217. };
  218. static const struct udevice_id bcm6345_serial_ids[] = {
  219. { .compatible = "brcm,bcm6345-uart" },
  220. { /* sentinel */ }
  221. };
  222. U_BOOT_DRIVER(bcm6345_serial) = {
  223. .name = "bcm6345-uart",
  224. .id = UCLASS_SERIAL,
  225. .of_match = bcm6345_serial_ids,
  226. .probe = bcm6345_serial_probe,
  227. .priv_auto = sizeof(struct bcm6345_serial_priv),
  228. .ops = &bcm6345_serial_ops,
  229. };
  230. #ifdef CONFIG_DEBUG_UART_BCM6345
  231. static inline void _debug_uart_init(void)
  232. {
  233. void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
  234. bcm6345_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
  235. }
  236. static inline void wait_xfered(void __iomem *base)
  237. {
  238. do {
  239. u32 val = readl(base + UART_IR_REG);
  240. if (val & UART_IR_STAT(UART_IR_TXEMPTY))
  241. break;
  242. } while (1);
  243. }
  244. static inline void _debug_uart_putc(int ch)
  245. {
  246. void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
  247. wait_xfered(base);
  248. writel(ch, base + UART_FIFO_REG);
  249. wait_xfered(base);
  250. }
  251. DEBUG_UART_FUNCS
  252. #endif