sti_usb_phy.c 4.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  4. * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
  5. */
  6. #include <common.h>
  7. #include <log.h>
  8. #include <asm/global_data.h>
  9. #include <asm/io.h>
  10. #include <bitfield.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <fdtdec.h>
  14. #include <generic-phy.h>
  15. #include <linux/libfdt.h>
  16. #include <regmap.h>
  17. #include <reset-uclass.h>
  18. #include <syscon.h>
  19. #include <wait_bit.h>
  20. #include <linux/bitops.h>
  21. #include <linux/compat.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. /* Default PHY_SEL and REFCLKSEL configuration */
  24. #define STIH407_USB_PICOPHY_CTRL_PORT_CONF 0x6
  25. /* ports parameters overriding */
  26. #define STIH407_USB_PICOPHY_PARAM_DEF 0x39a4dc
  27. #define PHYPARAM_REG 1
  28. #define PHYCTRL_REG 2
  29. #define PHYPARAM_NB 3
  30. struct sti_usb_phy {
  31. struct regmap *regmap;
  32. struct reset_ctl global_ctl;
  33. struct reset_ctl port_ctl;
  34. int param;
  35. int ctrl;
  36. };
  37. static int sti_usb_phy_deassert(struct sti_usb_phy *phy)
  38. {
  39. int ret;
  40. ret = reset_deassert(&phy->global_ctl);
  41. if (ret < 0) {
  42. pr_err("PHY global deassert failed: %d", ret);
  43. return ret;
  44. }
  45. ret = reset_deassert(&phy->port_ctl);
  46. if (ret < 0)
  47. pr_err("PHY port deassert failed: %d", ret);
  48. return ret;
  49. }
  50. static int sti_usb_phy_init(struct phy *usb_phy)
  51. {
  52. struct udevice *dev = usb_phy->dev;
  53. struct sti_usb_phy *phy = dev_get_priv(dev);
  54. void __iomem *reg;
  55. /* set ctrl picophy value */
  56. reg = (void __iomem *)phy->regmap->ranges[0].start + phy->ctrl;
  57. /* CTRL_PORT mask is 0x1f */
  58. clrsetbits_le32(reg, 0x1f, STIH407_USB_PICOPHY_CTRL_PORT_CONF);
  59. /* set ports parameters overriding */
  60. reg = (void __iomem *)phy->regmap->ranges[0].start + phy->param;
  61. /* PARAM_DEF mask is 0xffffffff */
  62. clrsetbits_le32(reg, 0xffffffff, STIH407_USB_PICOPHY_PARAM_DEF);
  63. return sti_usb_phy_deassert(phy);
  64. }
  65. static int sti_usb_phy_exit(struct phy *usb_phy)
  66. {
  67. struct udevice *dev = usb_phy->dev;
  68. struct sti_usb_phy *phy = dev_get_priv(dev);
  69. int ret;
  70. ret = reset_assert(&phy->port_ctl);
  71. if (ret < 0) {
  72. pr_err("PHY port assert failed: %d", ret);
  73. return ret;
  74. }
  75. ret = reset_assert(&phy->global_ctl);
  76. if (ret < 0)
  77. pr_err("PHY global assert failed: %d", ret);
  78. return ret;
  79. }
  80. struct phy_ops sti_usb_phy_ops = {
  81. .init = sti_usb_phy_init,
  82. .exit = sti_usb_phy_exit,
  83. };
  84. int sti_usb_phy_probe(struct udevice *dev)
  85. {
  86. struct sti_usb_phy *priv = dev_get_priv(dev);
  87. struct udevice *syscon;
  88. struct ofnode_phandle_args syscfg_phandle;
  89. u32 cells[PHYPARAM_NB];
  90. int ret, count;
  91. /* get corresponding syscon phandle */
  92. ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
  93. &syscfg_phandle);
  94. if (ret < 0) {
  95. pr_err("Can't get syscfg phandle: %d\n", ret);
  96. return ret;
  97. }
  98. ret = uclass_get_device_by_ofnode(UCLASS_SYSCON, syscfg_phandle.node,
  99. &syscon);
  100. if (ret) {
  101. pr_err("unable to find syscon device (%d)\n", ret);
  102. return ret;
  103. }
  104. priv->regmap = syscon_get_regmap(syscon);
  105. if (!priv->regmap) {
  106. pr_err("unable to find regmap\n");
  107. return -ENODEV;
  108. }
  109. /* get phy param offset */
  110. count = fdtdec_get_int_array_count(gd->fdt_blob, dev_of_offset(dev),
  111. "st,syscfg", cells,
  112. ARRAY_SIZE(cells));
  113. if (count < 0) {
  114. pr_err("Bad PHY st,syscfg property %d\n", count);
  115. return -EINVAL;
  116. }
  117. if (count > PHYPARAM_NB) {
  118. pr_err("Unsupported PHY param count %d\n", count);
  119. return -EINVAL;
  120. }
  121. priv->param = cells[PHYPARAM_REG];
  122. priv->ctrl = cells[PHYCTRL_REG];
  123. /* get global reset control */
  124. ret = reset_get_by_name(dev, "global", &priv->global_ctl);
  125. if (ret) {
  126. pr_err("can't get global reset for %s (%d)", dev->name, ret);
  127. return ret;
  128. }
  129. /* get port reset control */
  130. ret = reset_get_by_name(dev, "port", &priv->port_ctl);
  131. if (ret) {
  132. pr_err("can't get port reset for %s (%d)", dev->name, ret);
  133. return ret;
  134. }
  135. return 0;
  136. }
  137. static const struct udevice_id sti_usb_phy_ids[] = {
  138. { .compatible = "st,stih407-usb2-phy" },
  139. { }
  140. };
  141. U_BOOT_DRIVER(sti_usb_phy) = {
  142. .name = "sti_usb_phy",
  143. .id = UCLASS_PHY,
  144. .of_match = sti_usb_phy_ids,
  145. .probe = sti_usb_phy_probe,
  146. .ops = &sti_usb_phy_ops,
  147. .priv_auto = sizeof(struct sti_usb_phy),
  148. };