phy-ti-am654.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**
  3. * PCIe SERDES driver for AM654x SoC
  4. *
  5. * Copyright (C) 2018 Texas Instruments
  6. * Author: Kishon Vijay Abraham I <kishon@ti.com>
  7. */
  8. #include <common.h>
  9. #include <clk-uclass.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <dm/device.h>
  13. #include <dm/device_compat.h>
  14. #include <dm/lists.h>
  15. #include <dt-bindings/phy/phy.h>
  16. #include <generic-phy.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <power-domain.h>
  20. #include <regmap.h>
  21. #include <syscon.h>
  22. #include <linux/bitops.h>
  23. #include <linux/delay.h>
  24. #include <linux/err.h>
  25. #define CMU_R07C 0x7c
  26. #define CMU_MASTER_CDN_O BIT(24)
  27. #define COMLANE_R138 0xb38
  28. #define CONFIG_VERSION_REG_MASK GENMASK(23, 16)
  29. #define CONFIG_VERSION_REG_SHIFT 16
  30. #define VERSION 0x70
  31. #define COMLANE_R190 0xb90
  32. #define L1_MASTER_CDN_O BIT(9)
  33. #define COMLANE_R194 0xb94
  34. #define CMU_OK_I_0 BIT(19)
  35. #define SERDES_CTRL 0x1fd0
  36. #define POR_EN BIT(29)
  37. #define WIZ_LANEXCTL_STS 0x1fe0
  38. #define TX0_ENABLE_OVL BIT(31)
  39. #define TX0_ENABLE_MASK GENMASK(30, 29)
  40. #define TX0_ENABLE_SHIFT 29
  41. #define TX0_DISABLE_STATE 0x0
  42. #define TX0_SLEEP_STATE 0x1
  43. #define TX0_SNOOZE_STATE 0x2
  44. #define TX0_ENABLE_STATE 0x3
  45. #define RX0_ENABLE_OVL BIT(15)
  46. #define RX0_ENABLE_MASK GENMASK(14, 13)
  47. #define RX0_ENABLE_SHIFT 13
  48. #define RX0_DISABLE_STATE 0x0
  49. #define RX0_SLEEP_STATE 0x1
  50. #define RX0_SNOOZE_STATE 0x2
  51. #define RX0_ENABLE_STATE 0x3
  52. #define WIZ_PLL_CTRL 0x1ff4
  53. #define PLL_ENABLE_OVL BIT(31)
  54. #define PLL_ENABLE_MASK GENMASK(30, 29)
  55. #define PLL_ENABLE_SHIFT 29
  56. #define PLL_DISABLE_STATE 0x0
  57. #define PLL_SLEEP_STATE 0x1
  58. #define PLL_SNOOZE_STATE 0x2
  59. #define PLL_ENABLE_STATE 0x3
  60. #define PLL_OK BIT(28)
  61. #define PLL_LOCK_TIME 1000 /* in milliseconds */
  62. #define SLEEP_TIME 100 /* in microseconds */
  63. #define LANE_USB3 0x0
  64. #define LANE_PCIE0_LANE0 0x1
  65. #define LANE_PCIE1_LANE0 0x0
  66. #define LANE_PCIE0_LANE1 0x1
  67. #define SERDES_NUM_CLOCKS 3
  68. /* SERDES control MMR bit offsets */
  69. #define SERDES_CTL_LANE_FUNC_SEL_SHIFT 0
  70. #define SERDES_CTL_LANE_FUNC_SEL_MASK GENMASK(1, 0)
  71. #define SERDES_CTL_CLK_SEL_SHIFT 4
  72. #define SERDES_CTL_CLK_SEL_MASK GENMASK(7, 4)
  73. /**
  74. * struct serdes_am654_mux_clk_data - clock controller information structure
  75. */
  76. struct serdes_am654_mux_clk_data {
  77. struct regmap *regmap;
  78. struct clk_bulk parents;
  79. };
  80. static int serdes_am654_mux_clk_probe(struct udevice *dev)
  81. {
  82. struct serdes_am654_mux_clk_data *data = dev_get_priv(dev);
  83. struct udevice *syscon;
  84. struct regmap *regmap;
  85. int ret;
  86. debug("%s(dev=%s)\n", __func__, dev->name);
  87. if (!data)
  88. return -ENOMEM;
  89. ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
  90. "ti,serdes-clk", &syscon);
  91. if (ret) {
  92. dev_err(dev, "unable to find syscon device\n");
  93. return ret;
  94. }
  95. regmap = syscon_get_regmap(syscon);
  96. if (IS_ERR(regmap)) {
  97. dev_err(dev, "Fail to get Syscon regmap\n");
  98. return PTR_ERR(regmap);
  99. }
  100. data->regmap = regmap;
  101. ret = clk_get_bulk(dev, &data->parents);
  102. if (ret) {
  103. dev_err(dev, "Failed to obtain parent clocks\n");
  104. return ret;
  105. }
  106. return 0;
  107. }
  108. static int mux_table[SERDES_NUM_CLOCKS][3] = {
  109. /*
  110. * The entries represent values for selecting between
  111. * {left input, external reference clock, right input}
  112. * Only one of Left Output or Right Output should be used since
  113. * both left and right output clock uses the same bits and modifying
  114. * one clock will impact the other.
  115. */
  116. { BIT(2), 0, BIT(0) }, /* Mux of CMU refclk */
  117. { -1, BIT(3), BIT(1) }, /* Mux of Left Output */
  118. { BIT(1), BIT(3) | BIT(1), -1 }, /* Mux of Right Output */
  119. };
  120. static int serdes_am654_mux_clk_set_parent(struct clk *clk, struct clk *parent)
  121. {
  122. struct serdes_am654_mux_clk_data *data = dev_get_priv(clk->dev);
  123. u32 val;
  124. int i;
  125. debug("%s(clk=%s, parent=%s)\n", __func__, clk->dev->name,
  126. parent->dev->name);
  127. /*
  128. * Since we have the same device-tree node represent both the
  129. * clock and serdes device, we have two devices associated with
  130. * the serdes node. assigned-clocks for this node is processed twice,
  131. * once for the clock device and another time for the serdes
  132. * device. When it is processed for the clock device, it is before
  133. * the probe for clock device has been called. We ignore this case
  134. * and rely on assigned-clocks to be processed correctly for the
  135. * serdes case.
  136. */
  137. if (!data->regmap)
  138. return 0;
  139. for (i = 0; i < data->parents.count; i++) {
  140. if (clk_is_match(&data->parents.clks[i], parent))
  141. break;
  142. }
  143. if (i >= data->parents.count)
  144. return -EINVAL;
  145. val = mux_table[clk->id][i];
  146. val <<= SERDES_CTL_CLK_SEL_SHIFT;
  147. regmap_update_bits(data->regmap, 0, SERDES_CTL_CLK_SEL_MASK, val);
  148. return 0;
  149. }
  150. static struct clk_ops serdes_am654_mux_clk_ops = {
  151. .set_parent = serdes_am654_mux_clk_set_parent,
  152. };
  153. U_BOOT_DRIVER(serdes_am654_mux_clk) = {
  154. .name = "ti-serdes-am654-mux-clk",
  155. .id = UCLASS_CLK,
  156. .probe = serdes_am654_mux_clk_probe,
  157. .priv_auto = sizeof(struct serdes_am654_mux_clk_data),
  158. .ops = &serdes_am654_mux_clk_ops,
  159. };
  160. struct serdes_am654 {
  161. struct regmap *regmap;
  162. struct regmap *serdes_ctl;
  163. };
  164. static int serdes_am654_enable_pll(struct serdes_am654 *phy)
  165. {
  166. u32 mask = PLL_ENABLE_OVL | PLL_ENABLE_MASK;
  167. u32 val = PLL_ENABLE_OVL | (PLL_ENABLE_STATE << PLL_ENABLE_SHIFT);
  168. regmap_update_bits(phy->regmap, WIZ_PLL_CTRL, mask, val);
  169. return regmap_read_poll_timeout(phy->regmap, WIZ_PLL_CTRL, val,
  170. val & PLL_OK, 1000, PLL_LOCK_TIME);
  171. }
  172. static void serdes_am654_disable_pll(struct serdes_am654 *phy)
  173. {
  174. u32 mask = PLL_ENABLE_OVL | PLL_ENABLE_MASK;
  175. regmap_update_bits(phy->regmap, WIZ_PLL_CTRL, mask, 0);
  176. }
  177. static int serdes_am654_enable_txrx(struct serdes_am654 *phy)
  178. {
  179. u32 mask;
  180. u32 val;
  181. /* Enable TX */
  182. mask = TX0_ENABLE_OVL | TX0_ENABLE_MASK;
  183. val = TX0_ENABLE_OVL | (TX0_ENABLE_STATE << TX0_ENABLE_SHIFT);
  184. regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, val);
  185. /* Enable RX */
  186. mask = RX0_ENABLE_OVL | RX0_ENABLE_MASK;
  187. val = RX0_ENABLE_OVL | (RX0_ENABLE_STATE << RX0_ENABLE_SHIFT);
  188. regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, val);
  189. return 0;
  190. }
  191. static int serdes_am654_disable_txrx(struct serdes_am654 *phy)
  192. {
  193. u32 mask;
  194. /* Disable TX */
  195. mask = TX0_ENABLE_OVL | TX0_ENABLE_MASK;
  196. regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, 0);
  197. /* Disable RX */
  198. mask = RX0_ENABLE_OVL | RX0_ENABLE_MASK;
  199. regmap_update_bits(phy->regmap, WIZ_LANEXCTL_STS, mask, 0);
  200. return 0;
  201. }
  202. static int serdes_am654_power_on(struct phy *x)
  203. {
  204. struct serdes_am654 *phy = dev_get_priv(x->dev);
  205. int ret;
  206. u32 val;
  207. ret = serdes_am654_enable_pll(phy);
  208. if (ret) {
  209. dev_err(x->dev, "Failed to enable PLL\n");
  210. return ret;
  211. }
  212. ret = serdes_am654_enable_txrx(phy);
  213. if (ret) {
  214. dev_err(x->dev, "Failed to enable TX RX\n");
  215. return ret;
  216. }
  217. return regmap_read_poll_timeout(phy->regmap, COMLANE_R194, val,
  218. val & CMU_OK_I_0, SLEEP_TIME,
  219. PLL_LOCK_TIME);
  220. }
  221. static int serdes_am654_power_off(struct phy *x)
  222. {
  223. struct serdes_am654 *phy = dev_get_priv(x->dev);
  224. serdes_am654_disable_txrx(phy);
  225. serdes_am654_disable_pll(phy);
  226. return 0;
  227. }
  228. static int serdes_am654_init(struct phy *x)
  229. {
  230. struct serdes_am654 *phy = dev_get_priv(x->dev);
  231. u32 mask;
  232. u32 val;
  233. mask = CONFIG_VERSION_REG_MASK;
  234. val = VERSION << CONFIG_VERSION_REG_SHIFT;
  235. regmap_update_bits(phy->regmap, COMLANE_R138, mask, val);
  236. val = CMU_MASTER_CDN_O;
  237. regmap_update_bits(phy->regmap, CMU_R07C, val, val);
  238. val = L1_MASTER_CDN_O;
  239. regmap_update_bits(phy->regmap, COMLANE_R190, val, val);
  240. return 0;
  241. }
  242. static int serdes_am654_reset(struct phy *x)
  243. {
  244. struct serdes_am654 *phy = dev_get_priv(x->dev);
  245. u32 val;
  246. val = POR_EN;
  247. regmap_update_bits(phy->regmap, SERDES_CTRL, val, val);
  248. mdelay(1);
  249. regmap_update_bits(phy->regmap, SERDES_CTRL, val, 0);
  250. return 0;
  251. }
  252. static int serdes_am654_of_xlate(struct phy *x,
  253. struct ofnode_phandle_args *args)
  254. {
  255. struct serdes_am654 *phy = dev_get_priv(x->dev);
  256. if (args->args_count != 2) {
  257. dev_err(x->dev, "Invalid DT PHY argument count: %d\n",
  258. args->args_count);
  259. return -EINVAL;
  260. }
  261. if (args->args[0] != PHY_TYPE_PCIE) {
  262. dev_err(x->dev, "Unrecognized PHY type: %d\n",
  263. args->args[0]);
  264. return -EINVAL;
  265. }
  266. x->id = args->args[0] | (args->args[1] << 16);
  267. /* Setup mux mode using second argument */
  268. regmap_update_bits(phy->serdes_ctl, 0, SERDES_CTL_LANE_FUNC_SEL_MASK,
  269. args->args[1]);
  270. return 0;
  271. }
  272. static int serdes_am654_bind(struct udevice *dev)
  273. {
  274. int ret;
  275. ret = device_bind_driver_to_node(dev->parent,
  276. "ti-serdes-am654-mux-clk",
  277. dev_read_name(dev), dev_ofnode(dev),
  278. NULL);
  279. if (ret) {
  280. dev_err(dev, "%s: not able to bind clock driver\n", __func__);
  281. return ret;
  282. }
  283. return 0;
  284. }
  285. static int serdes_am654_probe(struct udevice *dev)
  286. {
  287. struct serdes_am654 *phy = dev_get_priv(dev);
  288. struct power_domain serdes_pwrdmn;
  289. struct regmap *serdes_ctl;
  290. struct regmap *map;
  291. int ret;
  292. ret = regmap_init_mem(dev_ofnode(dev), &map);
  293. if (ret)
  294. return ret;
  295. phy->regmap = map;
  296. serdes_ctl = syscon_regmap_lookup_by_phandle(dev, "ti,serdes-clk");
  297. if (IS_ERR(serdes_ctl)) {
  298. dev_err(dev, "unable to find syscon device\n");
  299. return PTR_ERR(serdes_ctl);
  300. }
  301. phy->serdes_ctl = serdes_ctl;
  302. ret = power_domain_get_by_index(dev, &serdes_pwrdmn, 0);
  303. if (ret) {
  304. dev_err(dev, "failed to get power domain\n");
  305. return ret;
  306. }
  307. ret = power_domain_on(&serdes_pwrdmn);
  308. if (ret) {
  309. dev_err(dev, "Power domain on failed\n");
  310. return ret;
  311. }
  312. return 0;
  313. }
  314. static const struct udevice_id serdes_am654_phy_ids[] = {
  315. {
  316. .compatible = "ti,phy-am654-serdes",
  317. },
  318. };
  319. static const struct phy_ops serdes_am654_phy_ops = {
  320. .reset = serdes_am654_reset,
  321. .init = serdes_am654_init,
  322. .power_on = serdes_am654_power_on,
  323. .power_off = serdes_am654_power_off,
  324. .of_xlate = serdes_am654_of_xlate,
  325. };
  326. U_BOOT_DRIVER(am654_serdes_phy) = {
  327. .name = "am654_serdes_phy",
  328. .id = UCLASS_PHY,
  329. .of_match = serdes_am654_phy_ids,
  330. .bind = serdes_am654_bind,
  331. .ops = &serdes_am654_phy_ops,
  332. .probe = serdes_am654_probe,
  333. .priv_auto = sizeof(struct serdes_am654),
  334. };