phy-stm32-usbphyc.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #define LOG_CATEGORY UCLASS_PHY
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <div64.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <generic-phy.h>
  12. #include <log.h>
  13. #include <reset.h>
  14. #include <syscon.h>
  15. #include <usb.h>
  16. #include <asm/io.h>
  17. #include <dm/device_compat.h>
  18. #include <linux/bitops.h>
  19. #include <linux/delay.h>
  20. #include <power/regulator.h>
  21. /* USBPHYC registers */
  22. #define STM32_USBPHYC_PLL 0x0
  23. #define STM32_USBPHYC_MISC 0x8
  24. /* STM32_USBPHYC_PLL bit fields */
  25. #define PLLNDIV GENMASK(6, 0)
  26. #define PLLNDIV_SHIFT 0
  27. #define PLLFRACIN GENMASK(25, 10)
  28. #define PLLFRACIN_SHIFT 10
  29. #define PLLEN BIT(26)
  30. #define PLLSTRB BIT(27)
  31. #define PLLSTRBYP BIT(28)
  32. #define PLLFRACCTL BIT(29)
  33. #define PLLDITHEN0 BIT(30)
  34. #define PLLDITHEN1 BIT(31)
  35. /* STM32_USBPHYC_MISC bit fields */
  36. #define SWITHOST BIT(0)
  37. #define MAX_PHYS 2
  38. /* max 100 us for PLL lock and 100 us for PHY init */
  39. #define PLL_INIT_TIME_US 200
  40. #define PLL_PWR_DOWN_TIME_US 5
  41. #define PLL_FVCO 2880 /* in MHz */
  42. #define PLL_INFF_MIN_RATE 19200000 /* in Hz */
  43. #define PLL_INFF_MAX_RATE 38400000 /* in Hz */
  44. struct pll_params {
  45. u8 ndiv;
  46. u16 frac;
  47. };
  48. struct stm32_usbphyc {
  49. fdt_addr_t base;
  50. struct clk clk;
  51. struct udevice *vdda1v1;
  52. struct udevice *vdda1v8;
  53. struct stm32_usbphyc_phy {
  54. struct udevice *vdd;
  55. struct udevice *vbus;
  56. bool init;
  57. bool powered;
  58. } phys[MAX_PHYS];
  59. };
  60. static void stm32_usbphyc_get_pll_params(u32 clk_rate,
  61. struct pll_params *pll_params)
  62. {
  63. unsigned long long fvco, ndiv, frac;
  64. /*
  65. * | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
  66. * | FVCO = 2880MHz
  67. * | NDIV = integer part of input bits to set the LDF
  68. * | FRACT = fractional part of input bits to set the LDF
  69. * => PLLNDIV = integer part of (FVCO / (INFF*2))
  70. * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
  71. * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
  72. */
  73. fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
  74. ndiv = fvco;
  75. do_div(ndiv, (clk_rate * 2));
  76. pll_params->ndiv = (u8)ndiv;
  77. frac = fvco * (1 << 16);
  78. do_div(frac, (clk_rate * 2));
  79. frac = frac - (ndiv * (1 << 16));
  80. pll_params->frac = (u16)frac;
  81. }
  82. static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
  83. {
  84. struct pll_params pll_params;
  85. u32 clk_rate = clk_get_rate(&usbphyc->clk);
  86. u32 usbphyc_pll;
  87. if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
  88. log_debug("input clk freq (%dHz) out of range\n",
  89. clk_rate);
  90. return -EINVAL;
  91. }
  92. stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
  93. usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
  94. usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
  95. if (pll_params.frac) {
  96. usbphyc_pll |= PLLFRACCTL;
  97. usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
  98. & PLLFRACIN);
  99. }
  100. writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
  101. log_debug("input clk freq=%dHz, ndiv=%d, frac=%d\n",
  102. clk_rate, pll_params.ndiv, pll_params.frac);
  103. return 0;
  104. }
  105. static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
  106. {
  107. int i;
  108. for (i = 0; i < MAX_PHYS; i++) {
  109. if (usbphyc->phys[i].init)
  110. return true;
  111. }
  112. return false;
  113. }
  114. static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
  115. {
  116. int i;
  117. for (i = 0; i < MAX_PHYS; i++) {
  118. if (usbphyc->phys[i].powered)
  119. return true;
  120. }
  121. return false;
  122. }
  123. static int stm32_usbphyc_phy_init(struct phy *phy)
  124. {
  125. struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
  126. struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
  127. bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
  128. true : false;
  129. int ret;
  130. dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
  131. /* Check if one phy port has already configured the pll */
  132. if (pllen && stm32_usbphyc_is_init(usbphyc))
  133. goto initialized;
  134. if (usbphyc->vdda1v1) {
  135. ret = regulator_set_enable(usbphyc->vdda1v1, true);
  136. if (ret)
  137. return ret;
  138. }
  139. if (usbphyc->vdda1v8) {
  140. ret = regulator_set_enable(usbphyc->vdda1v8, true);
  141. if (ret)
  142. return ret;
  143. }
  144. if (pllen) {
  145. clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
  146. udelay(PLL_PWR_DOWN_TIME_US);
  147. }
  148. ret = stm32_usbphyc_pll_init(usbphyc);
  149. if (ret)
  150. return ret;
  151. setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
  152. /* We must wait PLL_INIT_TIME_US before using PHY */
  153. udelay(PLL_INIT_TIME_US);
  154. if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
  155. return -EIO;
  156. initialized:
  157. usbphyc_phy->init = true;
  158. return 0;
  159. }
  160. static int stm32_usbphyc_phy_exit(struct phy *phy)
  161. {
  162. struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
  163. struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
  164. int ret;
  165. dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
  166. usbphyc_phy->init = false;
  167. /* Check if other phy port requires pllen */
  168. if (stm32_usbphyc_is_init(usbphyc))
  169. return 0;
  170. clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
  171. /*
  172. * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
  173. * bit is still clear
  174. */
  175. udelay(PLL_PWR_DOWN_TIME_US);
  176. if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
  177. return -EIO;
  178. if (usbphyc->vdda1v1) {
  179. ret = regulator_set_enable(usbphyc->vdda1v1, false);
  180. if (ret)
  181. return ret;
  182. }
  183. if (usbphyc->vdda1v8) {
  184. ret = regulator_set_enable(usbphyc->vdda1v8, false);
  185. if (ret)
  186. return ret;
  187. }
  188. return 0;
  189. }
  190. static int stm32_usbphyc_phy_power_on(struct phy *phy)
  191. {
  192. struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
  193. struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
  194. int ret;
  195. dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
  196. if (usbphyc_phy->vdd) {
  197. ret = regulator_set_enable(usbphyc_phy->vdd, true);
  198. if (ret)
  199. return ret;
  200. }
  201. if (usbphyc_phy->vbus) {
  202. ret = regulator_set_enable(usbphyc_phy->vbus, true);
  203. if (ret)
  204. return ret;
  205. }
  206. usbphyc_phy->powered = true;
  207. return 0;
  208. }
  209. static int stm32_usbphyc_phy_power_off(struct phy *phy)
  210. {
  211. struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
  212. struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
  213. int ret;
  214. dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
  215. usbphyc_phy->powered = false;
  216. if (stm32_usbphyc_is_powered(usbphyc))
  217. return 0;
  218. if (usbphyc_phy->vbus) {
  219. ret = regulator_set_enable(usbphyc_phy->vbus, false);
  220. if (ret)
  221. return ret;
  222. }
  223. if (usbphyc_phy->vdd) {
  224. ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false);
  225. if (ret)
  226. return ret;
  227. }
  228. return 0;
  229. }
  230. static int stm32_usbphyc_get_regulator(ofnode node,
  231. char *supply_name,
  232. struct udevice **regulator)
  233. {
  234. struct ofnode_phandle_args regulator_phandle;
  235. int ret;
  236. ret = ofnode_parse_phandle_with_args(node, supply_name,
  237. NULL, 0, 0,
  238. &regulator_phandle);
  239. if (ret)
  240. return ret;
  241. ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
  242. regulator_phandle.node,
  243. regulator);
  244. if (ret)
  245. return ret;
  246. return 0;
  247. }
  248. static int stm32_usbphyc_of_xlate(struct phy *phy,
  249. struct ofnode_phandle_args *args)
  250. {
  251. if (args->args_count < 1)
  252. return -ENODEV;
  253. if (args->args[0] >= MAX_PHYS)
  254. return -ENODEV;
  255. phy->id = args->args[0];
  256. if ((phy->id == 0 && args->args_count != 1) ||
  257. (phy->id == 1 && args->args_count != 2)) {
  258. dev_err(phy->dev, "invalid number of cells for phy port%ld\n",
  259. phy->id);
  260. return -EINVAL;
  261. }
  262. return 0;
  263. }
  264. static const struct phy_ops stm32_usbphyc_phy_ops = {
  265. .init = stm32_usbphyc_phy_init,
  266. .exit = stm32_usbphyc_phy_exit,
  267. .power_on = stm32_usbphyc_phy_power_on,
  268. .power_off = stm32_usbphyc_phy_power_off,
  269. .of_xlate = stm32_usbphyc_of_xlate,
  270. };
  271. static int stm32_usbphyc_probe(struct udevice *dev)
  272. {
  273. struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
  274. struct reset_ctl reset;
  275. ofnode node;
  276. int i, ret;
  277. usbphyc->base = dev_read_addr(dev);
  278. if (usbphyc->base == FDT_ADDR_T_NONE)
  279. return -EINVAL;
  280. /* Enable clock */
  281. ret = clk_get_by_index(dev, 0, &usbphyc->clk);
  282. if (ret)
  283. return ret;
  284. ret = clk_enable(&usbphyc->clk);
  285. if (ret)
  286. return ret;
  287. /* Reset */
  288. ret = reset_get_by_index(dev, 0, &reset);
  289. if (!ret) {
  290. reset_assert(&reset);
  291. udelay(2);
  292. reset_deassert(&reset);
  293. }
  294. /* get usbphyc regulator */
  295. ret = device_get_supply_regulator(dev, "vdda1v1-supply",
  296. &usbphyc->vdda1v1);
  297. if (ret) {
  298. dev_err(dev, "Can't get vdda1v1-supply regulator\n");
  299. return ret;
  300. }
  301. ret = device_get_supply_regulator(dev, "vdda1v8-supply",
  302. &usbphyc->vdda1v8);
  303. if (ret) {
  304. dev_err(dev, "Can't get vdda1v8-supply regulator\n");
  305. return ret;
  306. }
  307. /*
  308. * parse all PHY subnodes in order to populate regulator associated
  309. * to each PHY port
  310. */
  311. node = dev_read_first_subnode(dev);
  312. for (i = 0; i < MAX_PHYS; i++) {
  313. struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
  314. usbphyc_phy->init = false;
  315. usbphyc_phy->powered = false;
  316. ret = stm32_usbphyc_get_regulator(node, "phy-supply",
  317. &usbphyc_phy->vdd);
  318. if (ret) {
  319. dev_err(dev, "Can't get phy-supply regulator\n");
  320. return ret;
  321. }
  322. ret = stm32_usbphyc_get_regulator(node, "vbus-supply",
  323. &usbphyc_phy->vbus);
  324. if (ret)
  325. usbphyc_phy->vbus = NULL;
  326. node = dev_read_next_subnode(node);
  327. }
  328. /* Check if second port has to be used for host controller */
  329. if (dev_read_bool(dev, "st,port2-switch-to-host"))
  330. setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
  331. return 0;
  332. }
  333. static const struct udevice_id stm32_usbphyc_of_match[] = {
  334. { .compatible = "st,stm32mp1-usbphyc", },
  335. { },
  336. };
  337. U_BOOT_DRIVER(stm32_usb_phyc) = {
  338. .name = "stm32-usbphyc",
  339. .id = UCLASS_PHY,
  340. .of_match = stm32_usbphyc_of_match,
  341. .ops = &stm32_usbphyc_phy_ops,
  342. .probe = stm32_usbphyc_probe,
  343. .priv_auto = sizeof(struct stm32_usbphyc),
  344. };