phy-mtk-tphy.c 22 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2015 - 2019 MediaTek Inc.
  4. * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
  5. * Ryder Lee <ryder.lee@mediatek.com>
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <generic-phy.h>
  11. #include <malloc.h>
  12. #include <mapmem.h>
  13. #include <asm/io.h>
  14. #include <dm/device_compat.h>
  15. #include <dm/devres.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. #include <dt-bindings/phy/phy.h>
  19. /* version V1 sub-banks offset base address */
  20. /* banks shared by multiple phys */
  21. #define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */
  22. #define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */
  23. #define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */
  24. /* u2 phy bank */
  25. #define SSUSB_SIFSLV_V1_U2PHY_COM 0x000
  26. /* u3/pcie/sata phy banks */
  27. #define SSUSB_SIFSLV_V1_U3PHYD 0x000
  28. #define SSUSB_SIFSLV_V1_U3PHYA 0x200
  29. /* version V2 sub-banks offset base address */
  30. /* u2 phy banks */
  31. #define SSUSB_SIFSLV_V2_MISC 0x000
  32. #define SSUSB_SIFSLV_V2_U2FREQ 0x100
  33. #define SSUSB_SIFSLV_V2_U2PHY_COM 0x300
  34. /* u3/pcie/sata phy banks */
  35. #define SSUSB_SIFSLV_V2_SPLLC 0x000
  36. #define SSUSB_SIFSLV_V2_CHIP 0x100
  37. #define SSUSB_SIFSLV_V2_U3PHYD 0x200
  38. #define SSUSB_SIFSLV_V2_U3PHYA 0x400
  39. #define U3P_USBPHYACR0 0x000
  40. #define PA0_RG_U2PLL_FORCE_ON BIT(15)
  41. #define PA0_RG_USB20_INTR_EN BIT(5)
  42. #define U3P_USBPHYACR5 0x014
  43. #define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
  44. #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12)
  45. #define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
  46. #define PA5_RG_U2_HS_100U_U3_EN BIT(11)
  47. #define U3P_USBPHYACR6 0x018
  48. #define PA6_RG_U2_BC11_SW_EN BIT(23)
  49. #define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
  50. #define PA6_RG_U2_SQTH GENMASK(3, 0)
  51. #define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
  52. #define U3P_U2PHYACR4 0x020
  53. #define P2C_RG_USB20_GPIO_CTL BIT(9)
  54. #define P2C_USB20_GPIO_MODE BIT(8)
  55. #define P2C_U2_GPIO_CTR_MSK \
  56. (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE)
  57. #define U3P_U2PHYDTM0 0x068
  58. #define P2C_FORCE_UART_EN BIT(26)
  59. #define P2C_FORCE_DATAIN BIT(23)
  60. #define P2C_FORCE_DM_PULLDOWN BIT(21)
  61. #define P2C_FORCE_DP_PULLDOWN BIT(20)
  62. #define P2C_FORCE_XCVRSEL BIT(19)
  63. #define P2C_FORCE_SUSPENDM BIT(18)
  64. #define P2C_FORCE_TERMSEL BIT(17)
  65. #define P2C_RG_DATAIN GENMASK(13, 10)
  66. #define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
  67. #define P2C_RG_DMPULLDOWN BIT(7)
  68. #define P2C_RG_DPPULLDOWN BIT(6)
  69. #define P2C_RG_XCVRSEL GENMASK(5, 4)
  70. #define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
  71. #define P2C_RG_SUSPENDM BIT(3)
  72. #define P2C_RG_TERMSEL BIT(2)
  73. #define P2C_DTM0_PART_MASK \
  74. (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \
  75. P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \
  76. P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \
  77. P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL)
  78. #define U3P_U2PHYDTM1 0x06C
  79. #define P2C_RG_UART_EN BIT(16)
  80. #define P2C_FORCE_IDDIG BIT(9)
  81. #define P2C_RG_VBUSVALID BIT(5)
  82. #define P2C_RG_SESSEND BIT(4)
  83. #define P2C_RG_AVALID BIT(2)
  84. #define P2C_RG_IDDIG BIT(1)
  85. #define U3P_U3_CHIP_GPIO_CTLD 0x0c
  86. #define P3C_REG_IP_SW_RST BIT(31)
  87. #define P3C_MCU_BUS_CK_GATE_EN BIT(30)
  88. #define P3C_FORCE_IP_SW_RST BIT(29)
  89. #define U3P_U3_CHIP_GPIO_CTLE 0x10
  90. #define P3C_RG_SWRST_U3_PHYD BIT(25)
  91. #define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24)
  92. #define U3P_U3_PHYA_REG0 0x000
  93. #define P3A_RG_CLKDRV_OFF GENMASK(3, 2)
  94. #define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2)
  95. #define U3P_U3_PHYA_REG1 0x004
  96. #define P3A_RG_CLKDRV_AMP GENMASK(31, 29)
  97. #define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29)
  98. #define U3P_U3_PHYA_REG6 0x018
  99. #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
  100. #define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
  101. #define U3P_U3_PHYA_REG9 0x024
  102. #define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
  103. #define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
  104. #define U3P_U3_PHYA_DA_REG0 0x100
  105. #define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16)
  106. #define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16)
  107. #define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12)
  108. #define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12)
  109. #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
  110. #define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
  111. #define U3P_U3_PHYA_DA_REG4 0x108
  112. #define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19)
  113. #define P3A_RG_PLL_BC_PE2H GENMASK(7, 6)
  114. #define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6)
  115. #define U3P_U3_PHYA_DA_REG5 0x10c
  116. #define P3A_RG_PLL_BR_PE2H GENMASK(29, 28)
  117. #define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28)
  118. #define P3A_RG_PLL_IC_PE2H GENMASK(15, 12)
  119. #define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12)
  120. #define U3P_U3_PHYA_DA_REG6 0x110
  121. #define P3A_RG_PLL_IR_PE2H GENMASK(19, 16)
  122. #define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16)
  123. #define U3P_U3_PHYA_DA_REG7 0x114
  124. #define P3A_RG_PLL_BP_PE2H GENMASK(19, 16)
  125. #define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16)
  126. #define U3P_U3_PHYA_DA_REG20 0x13c
  127. #define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16)
  128. #define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16)
  129. #define U3P_U3_PHYA_DA_REG25 0x148
  130. #define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0)
  131. #define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x))
  132. #define U3P_U3_PHYD_LFPS1 0x00c
  133. #define P3D_RG_FWAKE_TH GENMASK(21, 16)
  134. #define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16)
  135. #define U3P_U3_PHYD_CDR1 0x05c
  136. #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)
  137. #define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
  138. #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)
  139. #define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
  140. #define U3P_U3_PHYD_RXDET1 0x128
  141. #define P3D_RG_RXDET_STB2_SET GENMASK(17, 9)
  142. #define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9)
  143. #define U3P_U3_PHYD_RXDET2 0x12c
  144. #define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0)
  145. #define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
  146. #define U3P_SPLLC_XTALCTL3 0x018
  147. #define XC3_RG_U3_XTAL_RX_PWD BIT(9)
  148. #define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8)
  149. /* SATA register setting */
  150. #define PHYD_CTRL_SIGNAL_MODE4 0x1c
  151. /* CDR Charge Pump P-path current adjustment */
  152. #define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20)
  153. #define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20)
  154. #define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8)
  155. #define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8)
  156. #define PHYD_DESIGN_OPTION2 0x24
  157. /* Symbol lock count selection */
  158. #define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4)
  159. #define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4)
  160. #define PHYD_DESIGN_OPTION9 0x40
  161. /* COMWAK GAP width window */
  162. #define RG_TG_MAX_MSK GENMASK(20, 16)
  163. #define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16)
  164. /* COMINIT GAP width window */
  165. #define RG_T2_MAX_MSK GENMASK(13, 8)
  166. #define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8)
  167. /* COMWAK GAP width window */
  168. #define RG_TG_MIN_MSK GENMASK(7, 5)
  169. #define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5)
  170. /* COMINIT GAP width window */
  171. #define RG_T2_MIN_MSK GENMASK(4, 0)
  172. #define RG_T2_MIN_VAL(x) (0x1f & (x))
  173. #define ANA_RG_CTRL_SIGNAL1 0x4c
  174. /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
  175. #define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8)
  176. #define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8)
  177. #define ANA_RG_CTRL_SIGNAL4 0x58
  178. #define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20)
  179. #define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20)
  180. /* Loop filter R1 resistance adjustment for Gen1 speed */
  181. #define RG_CDR_BR_GEN2_MSK GENMASK(10, 8)
  182. #define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8)
  183. #define ANA_RG_CTRL_SIGNAL6 0x60
  184. /* I-path capacitance adjustment for Gen1 */
  185. #define RG_CDR_BC_GEN1_MSK GENMASK(28, 24)
  186. #define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24)
  187. #define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0)
  188. #define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x))
  189. #define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c
  190. /* RX Gen1 LEQ tuning step */
  191. #define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8)
  192. #define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8)
  193. #define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8
  194. #define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16)
  195. #define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16)
  196. #define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc
  197. #define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0)
  198. #define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x))
  199. enum mtk_phy_version {
  200. MTK_TPHY_V1 = 1,
  201. MTK_TPHY_V2,
  202. };
  203. struct u2phy_banks {
  204. void __iomem *misc;
  205. void __iomem *fmreg;
  206. void __iomem *com;
  207. };
  208. struct u3phy_banks {
  209. void __iomem *spllc;
  210. void __iomem *chip;
  211. void __iomem *phyd; /* include u3phyd_bank2 */
  212. void __iomem *phya; /* include u3phya_da */
  213. };
  214. struct mtk_phy_instance {
  215. void __iomem *port_base;
  216. const struct device_node *np;
  217. union {
  218. struct u2phy_banks u2_banks;
  219. struct u3phy_banks u3_banks;
  220. };
  221. struct clk ref_clk; /* reference clock of (digital) phy */
  222. struct clk da_ref_clk; /* reference clock of analog phy */
  223. u32 index;
  224. u32 type;
  225. };
  226. struct mtk_tphy {
  227. struct udevice *dev;
  228. void __iomem *sif_base;
  229. enum mtk_phy_version version;
  230. struct mtk_phy_instance **phys;
  231. int nphys;
  232. };
  233. static void u2_phy_instance_init(struct mtk_tphy *tphy,
  234. struct mtk_phy_instance *instance)
  235. {
  236. struct u2phy_banks *u2_banks = &instance->u2_banks;
  237. /* switch to USB function, and enable usb pll */
  238. clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM0,
  239. P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM,
  240. P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0));
  241. clrbits_le32(u2_banks->com + U3P_U2PHYDTM1, P2C_RG_UART_EN);
  242. setbits_le32(u2_banks->com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN);
  243. /* disable switch 100uA current to SSUSB */
  244. clrbits_le32(u2_banks->com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN);
  245. clrbits_le32(u2_banks->com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK);
  246. /* DP/DM BC1.1 path Disable */
  247. clrsetbits_le32(u2_banks->com + U3P_USBPHYACR6,
  248. PA6_RG_U2_BC11_SW_EN | PA6_RG_U2_SQTH,
  249. PA6_RG_U2_SQTH_VAL(2));
  250. /* set HS slew rate */
  251. clrsetbits_le32(u2_banks->com + U3P_USBPHYACR5,
  252. PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
  253. dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
  254. }
  255. static void u2_phy_instance_power_on(struct mtk_tphy *tphy,
  256. struct mtk_phy_instance *instance)
  257. {
  258. struct u2phy_banks *u2_banks = &instance->u2_banks;
  259. clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
  260. P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
  261. /* OTG Enable */
  262. setbits_le32(u2_banks->com + U3P_USBPHYACR6,
  263. PA6_RG_U2_OTG_VBUSCMP_EN);
  264. clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
  265. P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID);
  266. dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
  267. }
  268. static void u2_phy_instance_power_off(struct mtk_tphy *tphy,
  269. struct mtk_phy_instance *instance)
  270. {
  271. struct u2phy_banks *u2_banks = &instance->u2_banks;
  272. clrbits_le32(u2_banks->com + U3P_U2PHYDTM0,
  273. P2C_RG_XCVRSEL | P2C_RG_DATAIN);
  274. /* OTG Disable */
  275. clrbits_le32(u2_banks->com + U3P_USBPHYACR6,
  276. PA6_RG_U2_OTG_VBUSCMP_EN);
  277. clrsetbits_le32(u2_banks->com + U3P_U2PHYDTM1,
  278. P2C_RG_VBUSVALID | P2C_RG_AVALID, P2C_RG_SESSEND);
  279. dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
  280. }
  281. static void u3_phy_instance_init(struct mtk_tphy *tphy,
  282. struct mtk_phy_instance *instance)
  283. {
  284. struct u3phy_banks *u3_banks = &instance->u3_banks;
  285. /* gating PCIe Analog XTAL clock */
  286. setbits_le32(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
  287. XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD);
  288. /* gating XSQ */
  289. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
  290. P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));
  291. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG9,
  292. P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));
  293. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG6,
  294. P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));
  295. clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_CDR1,
  296. P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1,
  297. P3D_RG_CDR_BIR_LTD0_VAL(0xc) |
  298. P3D_RG_CDR_BIR_LTD1_VAL(0x3));
  299. clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_LFPS1,
  300. P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34));
  301. clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
  302. P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10));
  303. clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
  304. P3D_RG_RXDET_STB2_SET_P3,
  305. P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
  306. dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
  307. }
  308. static void pcie_phy_instance_init(struct mtk_tphy *tphy,
  309. struct mtk_phy_instance *instance)
  310. {
  311. struct u3phy_banks *u3_banks = &instance->u3_banks;
  312. if (tphy->version != MTK_TPHY_V1)
  313. return;
  314. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
  315. P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
  316. P3A_RG_XTAL_EXT_PE1H_VAL(0x2) |
  317. P3A_RG_XTAL_EXT_PE2H_VAL(0x2));
  318. /* ref clk drive */
  319. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP,
  320. P3A_RG_CLKDRV_AMP_VAL(0x4));
  321. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF,
  322. P3A_RG_CLKDRV_OFF_VAL(0x1));
  323. /* SSC delta -5000ppm */
  324. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG20,
  325. P3A_RG_PLL_DELTA1_PE2H,
  326. P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c));
  327. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG25,
  328. P3A_RG_PLL_DELTA_PE2H,
  329. P3A_RG_PLL_DELTA_PE2H_VAL(0x36));
  330. /* change pll BW 0.6M */
  331. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG5,
  332. P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H,
  333. P3A_RG_PLL_BR_PE2H_VAL(0x1) |
  334. P3A_RG_PLL_IC_PE2H_VAL(0x1));
  335. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG4,
  336. P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H,
  337. P3A_RG_PLL_BC_PE2H_VAL(0x3));
  338. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG6,
  339. P3A_RG_PLL_IR_PE2H, P3A_RG_PLL_IR_PE2H_VAL(0x2));
  340. clrsetbits_le32(u3_banks->phya + U3P_U3_PHYA_DA_REG7,
  341. P3A_RG_PLL_BP_PE2H, P3A_RG_PLL_BP_PE2H_VAL(0xa));
  342. /* Tx Detect Rx Timing: 10us -> 5us */
  343. clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
  344. P3D_RG_RXDET_STB2_SET,
  345. P3D_RG_RXDET_STB2_SET_VAL(0x10));
  346. clrsetbits_le32(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
  347. P3D_RG_RXDET_STB2_SET_P3,
  348. P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
  349. /* wait for PCIe subsys register to active */
  350. udelay(3000);
  351. }
  352. static void sata_phy_instance_init(struct mtk_tphy *tphy,
  353. struct mtk_phy_instance *instance)
  354. {
  355. struct u3phy_banks *u3_banks = &instance->u3_banks;
  356. clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL6,
  357. RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK,
  358. RG_CDR_BIRLTR_GEN1_VAL(0x6) |
  359. RG_CDR_BC_GEN1_VAL(0x1a));
  360. clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL4,
  361. RG_CDR_BIRLTD0_GEN1_MSK,
  362. RG_CDR_BIRLTD0_GEN1_VAL(0x18));
  363. clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL5,
  364. RG_CDR_BIRLTD0_GEN3_MSK,
  365. RG_CDR_BIRLTD0_GEN3_VAL(0x06));
  366. clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL4,
  367. RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK,
  368. RG_CDR_BICLTR_GEN1_VAL(0x0c) |
  369. RG_CDR_BR_GEN2_VAL(0x07));
  370. clrsetbits_le32(u3_banks->phyd + PHYD_CTRL_SIGNAL_MODE4,
  371. RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK,
  372. RG_CDR_BICLTD0_GEN1_VAL(0x08) |
  373. RG_CDR_BICLTD1_GEN1_VAL(0x02));
  374. clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION2,
  375. RG_LOCK_CNT_SEL_MSK,
  376. RG_LOCK_CNT_SEL_VAL(0x02));
  377. clrsetbits_le32(u3_banks->phyd + PHYD_DESIGN_OPTION9,
  378. RG_T2_MIN_MSK | RG_TG_MIN_MSK |
  379. RG_T2_MAX_MSK | RG_TG_MAX_MSK,
  380. RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) |
  381. RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e));
  382. clrsetbits_le32(u3_banks->phyd + ANA_RG_CTRL_SIGNAL1,
  383. RG_IDRV_0DB_GEN1_MSK,
  384. RG_IDRV_0DB_GEN1_VAL(0x20));
  385. clrsetbits_le32(u3_banks->phyd + ANA_EQ_EYE_CTRL_SIGNAL1,
  386. RG_EQ_DLEQ_LFI_GEN1_MSK,
  387. RG_EQ_DLEQ_LFI_GEN1_VAL(0x03));
  388. }
  389. static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
  390. struct mtk_phy_instance *instance)
  391. {
  392. struct u3phy_banks *bank = &instance->u3_banks;
  393. clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
  394. P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
  395. clrbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
  396. P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
  397. }
  398. static void pcie_phy_instance_power_off(struct mtk_tphy *tphy,
  399. struct mtk_phy_instance *instance)
  400. {
  401. struct u3phy_banks *bank = &instance->u3_banks;
  402. setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLD,
  403. P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
  404. setbits_le32(bank->chip + U3P_U3_CHIP_GPIO_CTLE,
  405. P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
  406. }
  407. static void phy_v1_banks_init(struct mtk_tphy *tphy,
  408. struct mtk_phy_instance *instance)
  409. {
  410. struct u2phy_banks *u2_banks = &instance->u2_banks;
  411. struct u3phy_banks *u3_banks = &instance->u3_banks;
  412. switch (instance->type) {
  413. case PHY_TYPE_USB2:
  414. u2_banks->misc = NULL;
  415. u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ;
  416. u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM;
  417. break;
  418. case PHY_TYPE_USB3:
  419. case PHY_TYPE_PCIE:
  420. u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
  421. u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
  422. u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
  423. u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
  424. break;
  425. case PHY_TYPE_SATA:
  426. u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
  427. break;
  428. default:
  429. dev_err(tphy->dev, "incompatible PHY type\n");
  430. return;
  431. }
  432. }
  433. static void phy_v2_banks_init(struct mtk_tphy *tphy,
  434. struct mtk_phy_instance *instance)
  435. {
  436. struct u2phy_banks *u2_banks = &instance->u2_banks;
  437. struct u3phy_banks *u3_banks = &instance->u3_banks;
  438. switch (instance->type) {
  439. case PHY_TYPE_USB2:
  440. u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC;
  441. u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ;
  442. u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM;
  443. break;
  444. case PHY_TYPE_USB3:
  445. case PHY_TYPE_PCIE:
  446. u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC;
  447. u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP;
  448. u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD;
  449. u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA;
  450. break;
  451. default:
  452. dev_err(tphy->dev, "incompatible PHY type\n");
  453. return;
  454. }
  455. }
  456. static int mtk_phy_init(struct phy *phy)
  457. {
  458. struct mtk_tphy *tphy = dev_get_priv(phy->dev);
  459. struct mtk_phy_instance *instance = tphy->phys[phy->id];
  460. int ret;
  461. ret = clk_enable(&instance->ref_clk);
  462. if (ret < 0) {
  463. dev_err(tphy->dev, "failed to enable ref_clk\n");
  464. return ret;
  465. }
  466. ret = clk_enable(&instance->da_ref_clk);
  467. if (ret < 0) {
  468. dev_err(tphy->dev, "failed to enable da_ref_clk %d\n", ret);
  469. clk_disable(&instance->ref_clk);
  470. return ret;
  471. }
  472. switch (instance->type) {
  473. case PHY_TYPE_USB2:
  474. u2_phy_instance_init(tphy, instance);
  475. break;
  476. case PHY_TYPE_USB3:
  477. u3_phy_instance_init(tphy, instance);
  478. break;
  479. case PHY_TYPE_PCIE:
  480. pcie_phy_instance_init(tphy, instance);
  481. break;
  482. case PHY_TYPE_SATA:
  483. sata_phy_instance_init(tphy, instance);
  484. break;
  485. default:
  486. dev_err(tphy->dev, "incompatible PHY type\n");
  487. return -EINVAL;
  488. }
  489. return 0;
  490. }
  491. static int mtk_phy_power_on(struct phy *phy)
  492. {
  493. struct mtk_tphy *tphy = dev_get_priv(phy->dev);
  494. struct mtk_phy_instance *instance = tphy->phys[phy->id];
  495. if (instance->type == PHY_TYPE_USB2)
  496. u2_phy_instance_power_on(tphy, instance);
  497. else if (instance->type == PHY_TYPE_PCIE)
  498. pcie_phy_instance_power_on(tphy, instance);
  499. return 0;
  500. }
  501. static int mtk_phy_power_off(struct phy *phy)
  502. {
  503. struct mtk_tphy *tphy = dev_get_priv(phy->dev);
  504. struct mtk_phy_instance *instance = tphy->phys[phy->id];
  505. if (instance->type == PHY_TYPE_USB2)
  506. u2_phy_instance_power_off(tphy, instance);
  507. else if (instance->type == PHY_TYPE_PCIE)
  508. pcie_phy_instance_power_off(tphy, instance);
  509. return 0;
  510. }
  511. static int mtk_phy_exit(struct phy *phy)
  512. {
  513. struct mtk_tphy *tphy = dev_get_priv(phy->dev);
  514. struct mtk_phy_instance *instance = tphy->phys[phy->id];
  515. clk_disable(&instance->da_ref_clk);
  516. clk_disable(&instance->ref_clk);
  517. return 0;
  518. }
  519. static int mtk_phy_xlate(struct phy *phy,
  520. struct ofnode_phandle_args *args)
  521. {
  522. struct mtk_tphy *tphy = dev_get_priv(phy->dev);
  523. struct mtk_phy_instance *instance = NULL;
  524. const struct device_node *phy_np = ofnode_to_np(args->node);
  525. u32 index;
  526. if (!phy_np) {
  527. dev_err(phy->dev, "null pointer phy node\n");
  528. return -EINVAL;
  529. }
  530. if (args->args_count < 1) {
  531. dev_err(phy->dev, "invalid number of cells in 'phy' property\n");
  532. return -EINVAL;
  533. }
  534. for (index = 0; index < tphy->nphys; index++)
  535. if (phy_np == tphy->phys[index]->np) {
  536. instance = tphy->phys[index];
  537. break;
  538. }
  539. if (!instance) {
  540. dev_err(phy->dev, "failed to find appropriate phy\n");
  541. return -EINVAL;
  542. }
  543. phy->id = index;
  544. instance->type = args->args[1];
  545. if (!(instance->type == PHY_TYPE_USB2 ||
  546. instance->type == PHY_TYPE_USB3 ||
  547. instance->type == PHY_TYPE_SATA ||
  548. instance->type == PHY_TYPE_PCIE)) {
  549. dev_err(phy->dev, "unsupported device type\n");
  550. return -EINVAL;
  551. }
  552. if (tphy->version == MTK_TPHY_V1) {
  553. phy_v1_banks_init(tphy, instance);
  554. } else if (tphy->version == MTK_TPHY_V2) {
  555. phy_v2_banks_init(tphy, instance);
  556. } else {
  557. dev_err(phy->dev, "phy version is not supported\n");
  558. return -EINVAL;
  559. }
  560. return 0;
  561. }
  562. static const struct phy_ops mtk_tphy_ops = {
  563. .init = mtk_phy_init,
  564. .exit = mtk_phy_exit,
  565. .power_on = mtk_phy_power_on,
  566. .power_off = mtk_phy_power_off,
  567. .of_xlate = mtk_phy_xlate,
  568. };
  569. static int mtk_tphy_probe(struct udevice *dev)
  570. {
  571. struct mtk_tphy *tphy = dev_get_priv(dev);
  572. ofnode subnode;
  573. int index = 0;
  574. tphy->nphys = dev_get_child_count(dev);
  575. tphy->phys = devm_kcalloc(dev, tphy->nphys, sizeof(*tphy->phys),
  576. GFP_KERNEL);
  577. if (!tphy->phys)
  578. return -ENOMEM;
  579. tphy->dev = dev;
  580. tphy->version = dev_get_driver_data(dev);
  581. /* v1 has shared banks for usb/pcie mode, */
  582. /* but not for sata mode */
  583. if (tphy->version == MTK_TPHY_V1) {
  584. tphy->sif_base = dev_read_addr_ptr(dev);
  585. }
  586. dev_for_each_subnode(subnode, dev) {
  587. struct mtk_phy_instance *instance;
  588. fdt_addr_t addr;
  589. int err;
  590. instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL);
  591. if (!instance)
  592. return -ENOMEM;
  593. addr = ofnode_get_addr(subnode);
  594. if (addr == FDT_ADDR_T_NONE)
  595. return -ENOMEM;
  596. instance->port_base = map_sysmem(addr, 0);
  597. instance->index = index;
  598. instance->np = ofnode_to_np(subnode);
  599. tphy->phys[index] = instance;
  600. index++;
  601. err = clk_get_optional_nodev(subnode, "ref",
  602. &instance->ref_clk);
  603. if (err)
  604. return err;
  605. err = clk_get_optional_nodev(subnode, "da_ref",
  606. &instance->da_ref_clk);
  607. if (err)
  608. return err;
  609. }
  610. return 0;
  611. }
  612. static const struct udevice_id mtk_tphy_id_table[] = {
  613. { .compatible = "mediatek,generic-tphy-v1", .data = MTK_TPHY_V1, },
  614. { .compatible = "mediatek,generic-tphy-v2", .data = MTK_TPHY_V2, },
  615. { }
  616. };
  617. U_BOOT_DRIVER(mtk_tphy) = {
  618. .name = "mtk-tphy",
  619. .id = UCLASS_PHY,
  620. .of_match = mtk_tphy_id_table,
  621. .ops = &mtk_tphy_ops,
  622. .probe = mtk_tphy_probe,
  623. .priv_auto = sizeof(struct mtk_tphy),
  624. };