phy-imx8mq-usb.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2021 NXP
  4. *
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <generic-phy.h>
  11. #include <linux/bitops.h>
  12. #include <linux/err.h>
  13. #include <clk.h>
  14. #define PHY_CTRL0 0x0
  15. #define PHY_CTRL0_REF_SSP_EN BIT(2)
  16. #define PHY_CTRL0_FSEL_MASK GENMASK(10, 5)
  17. #define PHY_CTRL0_FSEL_24M 0x2a
  18. #define PHY_CTRL0_FSEL_100M 0x27
  19. #define PHY_CTRL0_SSC_RANGE_MASK GENMASK(23, 21)
  20. #define PHY_CTRL0_SSC_RANGE_4003PPM (0x2 << 21)
  21. #define PHY_CTRL1 0x4
  22. #define PHY_CTRL1_RESET BIT(0)
  23. #define PHY_CTRL1_COMMONONN BIT(1)
  24. #define PHY_CTRL1_ATERESET BIT(3)
  25. #define PHY_CTRL1_DCDENB BIT(17)
  26. #define PHY_CTRL1_CHRGSEL BIT(18)
  27. #define PHY_CTRL1_VDATSRCENB0 BIT(19)
  28. #define PHY_CTRL1_VDATDETENB0 BIT(20)
  29. #define PHY_CTRL2 0x8
  30. #define PHY_CTRL2_TXENABLEN0 BIT(8)
  31. #define PHY_CTRL2_OTG_DISABLE BIT(9)
  32. #define PHY_CTRL3 0xc
  33. #define PHY_CTRL3_COMPDISTUNE_MASK GENMASK(2, 0)
  34. #define PHY_CTRL3_TXPREEMP_TUNE_MASK GENMASK(16, 15)
  35. #define PHY_CTRL3_TXPREEMP_TUNE_SHIFT 15
  36. #define PHY_CTRL3_TXRISE_TUNE_MASK GENMASK(21, 20)
  37. #define PHY_CTRL3_TXRISE_TUNE_SHIFT 20
  38. /* 1111: +24% ... 0000: -6% step: 2% */
  39. #define PHY_CTRL3_TXVREF_TUNE_MASK GENMASK(25, 22)
  40. #define PHY_CTRL3_TXVREF_TUNE_SHIFT 22
  41. #define PHY_CTRL3_TX_VBOOST_LEVEL_MASK GENMASK(31, 29)
  42. #define PHY_CTRL3_TX_VBOOST_LEVEL_SHIFT 29
  43. #define PHY_CTRL4 0x10
  44. #define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(20, 15)
  45. #define PHY_CTRL4_PCS_TX_DEEMPH_3P5DB_SHIFT 15
  46. #define PHY_CTRL5 0x14
  47. #define PHY_CTRL5_DMPWD_OVERRIDE_SEL BIT(23)
  48. #define PHY_CTRL5_DMPWD_OVERRIDE BIT(22)
  49. #define PHY_CTRL5_DPPWD_OVERRIDE_SEL BIT(21)
  50. #define PHY_CTRL5_DPPWD_OVERRIDE BIT(20)
  51. #define PHY_CTRL5_PCS_TX_SWING_FULL_MASK GENMASK(6, 0)
  52. #define PHY_CTRL6 0x18
  53. #define PHY_CTRL6_RXTERM_OVERRIDE_SEL BIT(29)
  54. #define PHY_CTRL6_ALT_CLK_EN BIT(1)
  55. #define PHY_CTRL6_ALT_CLK_SEL BIT(0)
  56. #define PHY_STS0 0x40
  57. #define PHY_STS0_OTGSESSVLD BIT(7)
  58. #define PHY_STS0_CHGDET BIT(4)
  59. #define PHY_STS0_FSVPLUS BIT(3)
  60. #define PHY_STS0_FSVMINUS BIT(2)
  61. struct imx8mq_usb_phy {
  62. #if CONFIG_IS_ENABLED(CLK)
  63. struct clk phy_clk;
  64. #endif
  65. void __iomem *base;
  66. };
  67. static const struct udevice_id imx8mq_usb_phy_of_match[] = {
  68. {
  69. .compatible = "fsl,imx8mq-usb-phy",
  70. },
  71. {},
  72. };
  73. static int imx8mq_usb_phy_init(struct phy *usb_phy)
  74. {
  75. struct udevice *dev = usb_phy->dev;
  76. struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev);
  77. u32 value;
  78. value = readl(imx_phy->base + PHY_CTRL1);
  79. value &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0 |
  80. PHY_CTRL1_COMMONONN);
  81. value |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET;
  82. writel(value, imx_phy->base + PHY_CTRL1);
  83. value = readl(imx_phy->base + PHY_CTRL0);
  84. value |= PHY_CTRL0_REF_SSP_EN;
  85. value &= ~PHY_CTRL0_SSC_RANGE_MASK;
  86. value |= PHY_CTRL0_SSC_RANGE_4003PPM;
  87. writel(value, imx_phy->base + PHY_CTRL0);
  88. value = readl(imx_phy->base + PHY_CTRL2);
  89. value |= PHY_CTRL2_TXENABLEN0;
  90. writel(value, imx_phy->base + PHY_CTRL2);
  91. value = readl(imx_phy->base + PHY_CTRL1);
  92. value &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET);
  93. writel(value, imx_phy->base + PHY_CTRL1);
  94. return 0;
  95. }
  96. static int imx8mq_usb_phy_power_on(struct phy *usb_phy)
  97. {
  98. struct udevice *dev = usb_phy->dev;
  99. struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev);
  100. u32 value;
  101. #if CONFIG_IS_ENABLED(CLK)
  102. int ret;
  103. ret = clk_enable(&imx_phy->phy_clk);
  104. if (ret) {
  105. printf("Failed to enable usb phy clock\n");
  106. return ret;
  107. }
  108. #endif
  109. /* Disable rx term override */
  110. value = readl(imx_phy->base + PHY_CTRL6);
  111. value &= ~PHY_CTRL6_RXTERM_OVERRIDE_SEL;
  112. writel(value, imx_phy->base + PHY_CTRL6);
  113. return 0;
  114. }
  115. static int imx8mq_usb_phy_power_off(struct phy *usb_phy)
  116. {
  117. struct udevice *dev = usb_phy->dev;
  118. struct imx8mq_usb_phy *imx_phy = dev_get_priv(dev);
  119. u32 value;
  120. /* Override rx term to be 0 */
  121. value = readl(imx_phy->base + PHY_CTRL6);
  122. value |= PHY_CTRL6_RXTERM_OVERRIDE_SEL;
  123. writel(value, imx_phy->base + PHY_CTRL6);
  124. #if CONFIG_IS_ENABLED(CLK)
  125. clk_disable(&imx_phy->phy_clk);
  126. #endif
  127. return 0;
  128. }
  129. static int imx8mq_usb_phy_exit(struct phy *usb_phy)
  130. {
  131. return imx8mq_usb_phy_power_off(usb_phy);
  132. }
  133. struct phy_ops imx8mq_usb_phy_ops = {
  134. .init = imx8mq_usb_phy_init,
  135. .power_on = imx8mq_usb_phy_power_on,
  136. .power_off = imx8mq_usb_phy_power_off,
  137. .exit = imx8mq_usb_phy_exit,
  138. };
  139. int imx8mq_usb_phy_probe(struct udevice *dev)
  140. {
  141. struct imx8mq_usb_phy *priv = dev_get_priv(dev);
  142. priv->base = dev_read_addr_ptr(dev);
  143. if (!priv->base)
  144. return -EINVAL;
  145. #if CONFIG_IS_ENABLED(CLK)
  146. int ret;
  147. /* Assigned clock already set clock */
  148. ret = clk_get_by_name(dev, "phy", &priv->phy_clk);
  149. if (ret) {
  150. printf("Failed to get usb phy clock\n");
  151. return ret;
  152. }
  153. #endif
  154. return 0;
  155. }
  156. U_BOOT_DRIVER(nxp_imx8mq_usb_phy) = {
  157. .name = "nxp_imx8mq_usb_phy",
  158. .id = UCLASS_PHY,
  159. .of_match = imx8mq_usb_phy_of_match,
  160. .probe = imx8mq_usb_phy_probe,
  161. .ops = &imx8mq_usb_phy_ops,
  162. .priv_auto = sizeof(struct imx8mq_usb_phy),
  163. };