meson-g12a-usb3-pcie.c 9.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Meson G12A USB3+PCIE Combo PHY driver
  4. *
  5. * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  6. * Copyright (C) 2019 BayLibre, SAS
  7. * Author: Neil Armstrong <narmstron@baylibre.com>
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <malloc.h>
  13. #include <regmap.h>
  14. #include <errno.h>
  15. #include <asm/io.h>
  16. #include <reset.h>
  17. #include <bitfield.h>
  18. #include <generic-phy.h>
  19. #include <linux/delay.h>
  20. #include <linux/bitops.h>
  21. #include <linux/compat.h>
  22. #include <linux/bitfield.h>
  23. #define PHY_TYPE_PCIE 2
  24. #define PHY_TYPE_USB3 4
  25. #define PHY_R0 0x00
  26. #define PHY_R0_PCIE_POWER_STATE GENMASK(4, 0)
  27. #define PHY_R0_PCIE_USB3_SWITCH GENMASK(6, 5)
  28. #define PHY_R1 0x04
  29. #define PHY_R1_PHY_TX1_TERM_OFFSET GENMASK(4, 0)
  30. #define PHY_R1_PHY_TX0_TERM_OFFSET GENMASK(9, 5)
  31. #define PHY_R1_PHY_RX1_EQ GENMASK(12, 10)
  32. #define PHY_R1_PHY_RX0_EQ GENMASK(15, 13)
  33. #define PHY_R1_PHY_LOS_LEVEL GENMASK(20, 16)
  34. #define PHY_R1_PHY_LOS_BIAS GENMASK(23, 21)
  35. #define PHY_R1_PHY_REF_CLKDIV2 BIT(24)
  36. #define PHY_R1_PHY_MPLL_MULTIPLIER GENMASK(31, 25)
  37. #define PHY_R2 0x08
  38. #define PHY_R2_PCS_TX_DEEMPH_GEN2_6DB GENMASK(5, 0)
  39. #define PHY_R2_PCS_TX_DEEMPH_GEN2_3P5DB GENMASK(11, 6)
  40. #define PHY_R2_PCS_TX_DEEMPH_GEN1 GENMASK(17, 12)
  41. #define PHY_R2_PHY_TX_VBOOST_LVL GENMASK(20, 18)
  42. #define PHY_R4 0x10
  43. #define PHY_R4_PHY_CR_WRITE BIT(0)
  44. #define PHY_R4_PHY_CR_READ BIT(1)
  45. #define PHY_R4_PHY_CR_DATA_IN GENMASK(17, 2)
  46. #define PHY_R4_PHY_CR_CAP_DATA BIT(18)
  47. #define PHY_R4_PHY_CR_CAP_ADDR BIT(19)
  48. #define PHY_R5 0x14
  49. #define PHY_R5_PHY_CR_DATA_OUT GENMASK(15, 0)
  50. #define PHY_R5_PHY_CR_ACK BIT(16)
  51. #define PHY_R5_PHY_BS_OUT BIT(17)
  52. #define PCIE_RESET_DELAY 500
  53. struct phy_g12a_usb3_pcie_priv {
  54. struct regmap *regmap;
  55. #if CONFIG_IS_ENABLED(CLK)
  56. struct clk clk;
  57. #endif
  58. struct reset_ctl_bulk resets;
  59. };
  60. static int phy_g12a_usb3_pcie_cr_bus_addr(struct phy_g12a_usb3_pcie_priv *priv,
  61. unsigned int addr)
  62. {
  63. unsigned int val, reg;
  64. int ret;
  65. reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, addr);
  66. regmap_write(priv->regmap, PHY_R4, reg);
  67. regmap_write(priv->regmap, PHY_R4, reg);
  68. regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR);
  69. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  70. (val & PHY_R5_PHY_CR_ACK),
  71. 5, 1000);
  72. if (ret)
  73. return ret;
  74. regmap_write(priv->regmap, PHY_R4, reg);
  75. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  76. !(val & PHY_R5_PHY_CR_ACK),
  77. 5, 1000);
  78. if (ret)
  79. return ret;
  80. return 0;
  81. }
  82. static int
  83. phy_g12a_usb3_pcie_cr_bus_read(struct phy_g12a_usb3_pcie_priv *priv,
  84. unsigned int addr, unsigned int *data)
  85. {
  86. unsigned int val;
  87. int ret;
  88. ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
  89. if (ret)
  90. return ret;
  91. regmap_write(priv->regmap, PHY_R4, 0);
  92. regmap_write(priv->regmap, PHY_R4, PHY_R4_PHY_CR_READ);
  93. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  94. (val & PHY_R5_PHY_CR_ACK),
  95. 5, 1000);
  96. if (ret)
  97. return ret;
  98. *data = FIELD_GET(PHY_R5_PHY_CR_DATA_OUT, val);
  99. regmap_write(priv->regmap, PHY_R4, 0);
  100. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  101. !(val & PHY_R5_PHY_CR_ACK),
  102. 5, 1000);
  103. if (ret)
  104. return ret;
  105. return 0;
  106. }
  107. static int
  108. phy_g12a_usb3_pcie_cr_bus_write(struct phy_g12a_usb3_pcie_priv *priv,
  109. unsigned int addr, unsigned int data)
  110. {
  111. unsigned int val, reg;
  112. int ret;
  113. ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
  114. if (ret)
  115. return ret;
  116. reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, data);
  117. regmap_write(priv->regmap, PHY_R4, reg);
  118. regmap_write(priv->regmap, PHY_R4, reg);
  119. regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_DATA);
  120. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  121. (val & PHY_R5_PHY_CR_ACK),
  122. 5, 1000);
  123. if (ret)
  124. return ret;
  125. regmap_write(priv->regmap, PHY_R4, reg);
  126. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  127. (val & PHY_R5_PHY_CR_ACK) == 0,
  128. 5, 1000);
  129. if (ret)
  130. return ret;
  131. regmap_write(priv->regmap, PHY_R4, reg);
  132. regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_WRITE);
  133. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  134. (val & PHY_R5_PHY_CR_ACK),
  135. 5, 1000);
  136. if (ret)
  137. return ret;
  138. regmap_write(priv->regmap, PHY_R4, reg);
  139. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  140. (val & PHY_R5_PHY_CR_ACK) == 0,
  141. 5, 1000);
  142. if (ret)
  143. return ret;
  144. return 0;
  145. }
  146. static int
  147. phy_g12a_usb3_pcie_cr_bus_update_bits(struct phy_g12a_usb3_pcie_priv *priv,
  148. uint offset, uint mask, uint val)
  149. {
  150. uint reg;
  151. int ret;
  152. ret = phy_g12a_usb3_pcie_cr_bus_read(priv, offset, &reg);
  153. if (ret)
  154. return ret;
  155. reg &= ~mask;
  156. return phy_g12a_usb3_pcie_cr_bus_write(priv, offset, reg | val);
  157. }
  158. static int phy_meson_g12a_usb3_init(struct phy *phy)
  159. {
  160. struct udevice *dev = phy->dev;
  161. struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(dev);
  162. unsigned int data;
  163. int ret;
  164. ret = reset_assert_bulk(&priv->resets);
  165. udelay(1);
  166. ret |= reset_deassert_bulk(&priv->resets);
  167. if (ret)
  168. return ret;
  169. /* Switch PHY to USB3 */
  170. regmap_update_bits(priv->regmap, PHY_R0,
  171. PHY_R0_PCIE_USB3_SWITCH,
  172. PHY_R0_PCIE_USB3_SWITCH);
  173. /*
  174. * WORKAROUND: There is SSPHY suspend bug due to
  175. * which USB enumerates
  176. * in HS mode instead of SS mode. Workaround it by asserting
  177. * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus
  178. * mode
  179. */
  180. ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x102d,
  181. BIT(7), BIT(7));
  182. if (ret)
  183. return ret;
  184. ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x1010, 0xff0, 20);
  185. if (ret)
  186. return ret;
  187. /*
  188. * Fix RX Equalization setting as follows
  189. * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
  190. * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
  191. * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
  192. * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
  193. */
  194. ret = phy_g12a_usb3_pcie_cr_bus_read(priv, 0x1006, &data);
  195. if (ret)
  196. return ret;
  197. data &= ~BIT(6);
  198. data |= BIT(7);
  199. data &= ~(0x7 << 8);
  200. data |= (0x3 << 8);
  201. data |= (1 << 11);
  202. ret = phy_g12a_usb3_pcie_cr_bus_write(priv, 0x1006, data);
  203. if (ret)
  204. return ret;
  205. /*
  206. * Set EQ and TX launch amplitudes as follows
  207. * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
  208. * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
  209. * LANE0.TX_OVRD_DRV_LO.EN set to 1.
  210. */
  211. ret = phy_g12a_usb3_pcie_cr_bus_read(priv, 0x1002, &data);
  212. if (ret)
  213. return ret;
  214. data &= ~0x3f80;
  215. data |= (0x16 << 7);
  216. data &= ~0x7f;
  217. data |= (0x7f | BIT(14));
  218. ret = phy_g12a_usb3_pcie_cr_bus_write(priv, 0x1002, data);
  219. if (ret)
  220. return ret;
  221. /*
  222. * MPLL_LOOP_CTL.PROP_CNTRL = 8
  223. */
  224. ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x30,
  225. 0xf << 4, 8 << 4);
  226. if (ret)
  227. return ret;
  228. regmap_update_bits(priv->regmap, PHY_R2,
  229. PHY_R2_PHY_TX_VBOOST_LVL,
  230. FIELD_PREP(PHY_R2_PHY_TX_VBOOST_LVL, 0x4));
  231. regmap_update_bits(priv->regmap, PHY_R1,
  232. PHY_R1_PHY_LOS_BIAS | PHY_R1_PHY_LOS_LEVEL,
  233. FIELD_PREP(PHY_R1_PHY_LOS_BIAS, 4) |
  234. FIELD_PREP(PHY_R1_PHY_LOS_LEVEL, 9));
  235. return ret;
  236. }
  237. static int phy_meson_g12a_usb3_exit(struct phy *phy)
  238. {
  239. struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev);
  240. return reset_assert_bulk(&priv->resets);
  241. }
  242. static int phy_meson_g12a_usb3_pcie_init(struct phy *phy)
  243. {
  244. if (phy->id == PHY_TYPE_USB3)
  245. return phy_meson_g12a_usb3_init(phy);
  246. return 0;
  247. }
  248. static int phy_meson_g12a_usb3_pcie_exit(struct phy *phy)
  249. {
  250. if (phy->id == PHY_TYPE_USB3)
  251. return phy_meson_g12a_usb3_exit(phy);
  252. return 0;
  253. }
  254. static int phy_meson_g12a_usb3_pcie_power_on(struct phy *phy)
  255. {
  256. struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev);
  257. if (phy->id == PHY_TYPE_USB3)
  258. return 0;
  259. regmap_update_bits(priv->regmap, PHY_R0,
  260. PHY_R0_PCIE_POWER_STATE,
  261. FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
  262. return 0;
  263. }
  264. static int phy_meson_g12a_usb3_pcie_power_off(struct phy *phy)
  265. {
  266. struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev);
  267. if (phy->id == PHY_TYPE_USB3)
  268. return 0;
  269. regmap_update_bits(priv->regmap, PHY_R0,
  270. PHY_R0_PCIE_POWER_STATE,
  271. FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1d));
  272. return 0;
  273. }
  274. static int phy_meson_g12a_usb3_pcie_reset(struct phy *phy)
  275. {
  276. struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev);
  277. int ret;
  278. if (phy->id == PHY_TYPE_USB3)
  279. return 0;
  280. ret = reset_assert_bulk(&priv->resets);
  281. if (ret)
  282. return ret;
  283. udelay(PCIE_RESET_DELAY);
  284. ret = reset_deassert_bulk(&priv->resets);
  285. if (ret)
  286. return ret;
  287. udelay(PCIE_RESET_DELAY);
  288. return 0;
  289. }
  290. struct phy_ops meson_g12a_usb3_pcie_phy_ops = {
  291. .init = phy_meson_g12a_usb3_pcie_init,
  292. .exit = phy_meson_g12a_usb3_pcie_exit,
  293. .power_on = phy_meson_g12a_usb3_pcie_power_on,
  294. .power_off = phy_meson_g12a_usb3_pcie_power_off,
  295. .reset = phy_meson_g12a_usb3_pcie_reset,
  296. };
  297. int meson_g12a_usb3_pcie_phy_probe(struct udevice *dev)
  298. {
  299. struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(dev);
  300. int ret;
  301. ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
  302. if (ret)
  303. return ret;
  304. ret = reset_get_bulk(dev, &priv->resets);
  305. if (ret == -ENOTSUPP)
  306. return 0;
  307. else if (ret)
  308. return ret;
  309. #if CONFIG_IS_ENABLED(CLK)
  310. ret = clk_get_by_index(dev, 0, &priv->clk);
  311. if (ret < 0)
  312. return ret;
  313. ret = clk_enable(&priv->clk);
  314. if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
  315. pr_err("failed to enable PHY clock\n");
  316. clk_free(&priv->clk);
  317. return ret;
  318. }
  319. #endif
  320. return 0;
  321. }
  322. static const struct udevice_id meson_g12a_usb3_pcie_phy_ids[] = {
  323. { .compatible = "amlogic,g12a-usb3-pcie-phy" },
  324. { }
  325. };
  326. U_BOOT_DRIVER(meson_g12a_usb3_pcie_phy) = {
  327. .name = "meson_g12a_usb3_pcie_phy",
  328. .id = UCLASS_PHY,
  329. .of_match = meson_g12a_usb3_pcie_phy_ids,
  330. .probe = meson_g12a_usb3_pcie_phy_probe,
  331. .ops = &meson_g12a_usb3_pcie_phy_ops,
  332. .priv_auto = sizeof(struct phy_g12a_usb3_pcie_priv),
  333. };