pch9.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <log.h>
  8. #include <pch.h>
  9. #define GPIO_BASE 0x48
  10. #define IO_BASE 0x4c
  11. #define SBASE_ADDR 0x54
  12. static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep)
  13. {
  14. uint32_t sbase_addr;
  15. dm_pci_read_config32(dev, SBASE_ADDR, &sbase_addr);
  16. *sbasep = sbase_addr & 0xfffffe00;
  17. return 0;
  18. }
  19. static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep)
  20. {
  21. u32 base;
  22. /*
  23. * GPIO_BASE moved to its current offset with ICH6, but prior to
  24. * that it was unused (or undocumented). Check that it looks
  25. * okay: not all ones or zeros.
  26. *
  27. * Note we don't need check bit0 here, because the Tunnel Creek
  28. * GPIO base address register bit0 is reserved (read returns 0),
  29. * while on the Ivybridge the bit0 is used to indicate it is an
  30. * I/O space.
  31. */
  32. dm_pci_read_config32(dev, GPIO_BASE, &base);
  33. if (base == 0x00000000 || base == 0xffffffff) {
  34. debug("%s: unexpected BASE value\n", __func__);
  35. return -ENODEV;
  36. }
  37. /*
  38. * Okay, I guess we're looking at the right device. The actual
  39. * GPIO registers are in the PCI device's I/O space, starting
  40. * at the offset that we just read. Bit 0 indicates that it's
  41. * an I/O address, not a memory address, so mask that off.
  42. */
  43. *gbasep = base & 1 ? base & ~3 : base & ~15;
  44. return 0;
  45. }
  46. static int pch9_get_io_base(struct udevice *dev, u32 *iobasep)
  47. {
  48. u32 base;
  49. dm_pci_read_config32(dev, IO_BASE, &base);
  50. if (base == 0x00000000 || base == 0xffffffff) {
  51. debug("%s: unexpected BASE value\n", __func__);
  52. return -ENODEV;
  53. }
  54. *iobasep = base & 1 ? base & ~3 : base & ~15;
  55. return 0;
  56. }
  57. static const struct pch_ops pch9_ops = {
  58. .get_spi_base = pch9_get_spi_base,
  59. .get_gpio_base = pch9_get_gpio_base,
  60. .get_io_base = pch9_get_io_base,
  61. };
  62. static const struct udevice_id pch9_ids[] = {
  63. { .compatible = "intel,pch9" },
  64. { }
  65. };
  66. U_BOOT_DRIVER(pch9_drv) = {
  67. .name = "intel-pch9",
  68. .id = UCLASS_PCH,
  69. .of_match = pch9_ids,
  70. .ops = &pch9_ops,
  71. };