tmio-common.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <cpu_func.h>
  9. #include <fdtdec.h>
  10. #include <mmc.h>
  11. #include <dm.h>
  12. #include <asm/global_data.h>
  13. #include <dm/device_compat.h>
  14. #include <dm/pinctrl.h>
  15. #include <linux/compat.h>
  16. #include <linux/delay.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/io.h>
  19. #include <linux/sizes.h>
  20. #include <power/regulator.h>
  21. #include <asm/unaligned.h>
  22. #include "tmio-common.h"
  23. DECLARE_GLOBAL_DATA_PTR;
  24. static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg)
  25. {
  26. return readq(priv->regbase + (reg << 1));
  27. }
  28. static void tmio_sd_writeq(struct tmio_sd_priv *priv,
  29. u64 val, unsigned int reg)
  30. {
  31. writeq(val, priv->regbase + (reg << 1));
  32. }
  33. static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg)
  34. {
  35. return readw(priv->regbase + (reg >> 1));
  36. }
  37. static void tmio_sd_writew(struct tmio_sd_priv *priv,
  38. u16 val, unsigned int reg)
  39. {
  40. writew(val, priv->regbase + (reg >> 1));
  41. }
  42. u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg)
  43. {
  44. u32 val;
  45. if (priv->caps & TMIO_SD_CAP_64BIT)
  46. return readl(priv->regbase + (reg << 1));
  47. else if (priv->caps & TMIO_SD_CAP_16BIT) {
  48. val = readw(priv->regbase + (reg >> 1)) & 0xffff;
  49. if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) ||
  50. (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) {
  51. val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
  52. }
  53. return val;
  54. } else
  55. return readl(priv->regbase + reg);
  56. }
  57. void tmio_sd_writel(struct tmio_sd_priv *priv,
  58. u32 val, unsigned int reg)
  59. {
  60. if (priv->caps & TMIO_SD_CAP_64BIT)
  61. writel(val, priv->regbase + (reg << 1));
  62. else if (priv->caps & TMIO_SD_CAP_16BIT) {
  63. writew(val & 0xffff, priv->regbase + (reg >> 1));
  64. if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK ||
  65. reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK ||
  66. reg == TMIO_SD_ARG)
  67. writew(val >> 16, priv->regbase + (reg >> 1) + 2);
  68. } else
  69. writel(val, priv->regbase + reg);
  70. }
  71. static int tmio_sd_check_error(struct udevice *dev, struct mmc_cmd *cmd)
  72. {
  73. struct tmio_sd_priv *priv = dev_get_priv(dev);
  74. u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
  75. if (info2 & TMIO_SD_INFO2_ERR_RTO) {
  76. /*
  77. * TIMEOUT must be returned for unsupported command. Do not
  78. * display error log since this might be a part of sequence to
  79. * distinguish between SD and MMC.
  80. */
  81. return -ETIMEDOUT;
  82. }
  83. if (info2 & TMIO_SD_INFO2_ERR_TO) {
  84. dev_err(dev, "timeout error\n");
  85. return -ETIMEDOUT;
  86. }
  87. if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
  88. TMIO_SD_INFO2_ERR_IDX)) {
  89. if ((cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK) &&
  90. (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200))
  91. dev_err(dev, "communication out of sync\n");
  92. return -EILSEQ;
  93. }
  94. if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR |
  95. TMIO_SD_INFO2_ERR_ILW)) {
  96. dev_err(dev, "illegal access\n");
  97. return -EIO;
  98. }
  99. return 0;
  100. }
  101. static int tmio_sd_wait_for_irq(struct udevice *dev, struct mmc_cmd *cmd,
  102. unsigned int reg, u32 flag)
  103. {
  104. struct tmio_sd_priv *priv = dev_get_priv(dev);
  105. long wait = 1000000;
  106. int ret;
  107. while (!(tmio_sd_readl(priv, reg) & flag)) {
  108. if (wait-- < 0) {
  109. dev_err(dev, "timeout\n");
  110. return -ETIMEDOUT;
  111. }
  112. ret = tmio_sd_check_error(dev, cmd);
  113. if (ret)
  114. return ret;
  115. udelay(1);
  116. }
  117. return 0;
  118. }
  119. #define tmio_pio_read_fifo(__width, __suffix) \
  120. static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \
  121. char *pbuf, uint blksz) \
  122. { \
  123. u##__width *buf = (u##__width *)pbuf; \
  124. int i; \
  125. \
  126. if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
  127. for (i = 0; i < blksz / ((__width) / 8); i++) { \
  128. *buf++ = tmio_sd_read##__suffix(priv, \
  129. TMIO_SD_BUF); \
  130. } \
  131. } else { \
  132. for (i = 0; i < blksz / ((__width) / 8); i++) { \
  133. u##__width data; \
  134. data = tmio_sd_read##__suffix(priv, \
  135. TMIO_SD_BUF); \
  136. put_unaligned(data, buf++); \
  137. } \
  138. } \
  139. }
  140. tmio_pio_read_fifo(64, q)
  141. tmio_pio_read_fifo(32, l)
  142. tmio_pio_read_fifo(16, w)
  143. static int tmio_sd_pio_read_one_block(struct udevice *dev, struct mmc_cmd *cmd,
  144. char *pbuf, uint blocksize)
  145. {
  146. struct tmio_sd_priv *priv = dev_get_priv(dev);
  147. int ret;
  148. /* wait until the buffer is filled with data */
  149. ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
  150. TMIO_SD_INFO2_BRE);
  151. if (ret)
  152. return ret;
  153. /*
  154. * Clear the status flag _before_ read the buffer out because
  155. * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered.
  156. */
  157. tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
  158. if (priv->caps & TMIO_SD_CAP_64BIT)
  159. tmio_pio_read_fifo_64(priv, pbuf, blocksize);
  160. else if (priv->caps & TMIO_SD_CAP_16BIT)
  161. tmio_pio_read_fifo_16(priv, pbuf, blocksize);
  162. else
  163. tmio_pio_read_fifo_32(priv, pbuf, blocksize);
  164. return 0;
  165. }
  166. #define tmio_pio_write_fifo(__width, __suffix) \
  167. static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \
  168. const char *pbuf, uint blksz)\
  169. { \
  170. const u##__width *buf = (const u##__width *)pbuf; \
  171. int i; \
  172. \
  173. if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
  174. for (i = 0; i < blksz / ((__width) / 8); i++) { \
  175. tmio_sd_write##__suffix(priv, *buf++, \
  176. TMIO_SD_BUF); \
  177. } \
  178. } else { \
  179. for (i = 0; i < blksz / ((__width) / 8); i++) { \
  180. u##__width data = get_unaligned(buf++); \
  181. tmio_sd_write##__suffix(priv, data, \
  182. TMIO_SD_BUF); \
  183. } \
  184. } \
  185. }
  186. tmio_pio_write_fifo(64, q)
  187. tmio_pio_write_fifo(32, l)
  188. tmio_pio_write_fifo(16, w)
  189. static int tmio_sd_pio_write_one_block(struct udevice *dev, struct mmc_cmd *cmd,
  190. const char *pbuf, uint blocksize)
  191. {
  192. struct tmio_sd_priv *priv = dev_get_priv(dev);
  193. int ret;
  194. /* wait until the buffer becomes empty */
  195. ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
  196. TMIO_SD_INFO2_BWE);
  197. if (ret)
  198. return ret;
  199. tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
  200. if (priv->caps & TMIO_SD_CAP_64BIT)
  201. tmio_pio_write_fifo_64(priv, pbuf, blocksize);
  202. else if (priv->caps & TMIO_SD_CAP_16BIT)
  203. tmio_pio_write_fifo_16(priv, pbuf, blocksize);
  204. else
  205. tmio_pio_write_fifo_32(priv, pbuf, blocksize);
  206. return 0;
  207. }
  208. static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_cmd *cmd,
  209. struct mmc_data *data)
  210. {
  211. const char *src = data->src;
  212. char *dest = data->dest;
  213. int i, ret;
  214. for (i = 0; i < data->blocks; i++) {
  215. if (data->flags & MMC_DATA_READ)
  216. ret = tmio_sd_pio_read_one_block(dev, cmd, dest,
  217. data->blocksize);
  218. else
  219. ret = tmio_sd_pio_write_one_block(dev, cmd, src,
  220. data->blocksize);
  221. if (ret)
  222. return ret;
  223. if (data->flags & MMC_DATA_READ)
  224. dest += data->blocksize;
  225. else
  226. src += data->blocksize;
  227. }
  228. return 0;
  229. }
  230. static void tmio_sd_dma_start(struct tmio_sd_priv *priv,
  231. dma_addr_t dma_addr)
  232. {
  233. u32 tmp;
  234. tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1);
  235. tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2);
  236. /* enable DMA */
  237. tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
  238. tmp |= TMIO_SD_EXTMODE_DMA_EN;
  239. tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
  240. tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L);
  241. /* suppress the warning "right shift count >= width of type" */
  242. dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
  243. tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H);
  244. tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL);
  245. }
  246. static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
  247. unsigned int blocks)
  248. {
  249. struct tmio_sd_priv *priv = dev_get_priv(dev);
  250. long wait = 1000000 + 10 * blocks;
  251. while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
  252. if (wait-- < 0) {
  253. dev_err(dev, "timeout during DMA\n");
  254. return -ETIMEDOUT;
  255. }
  256. udelay(10);
  257. }
  258. if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) {
  259. dev_err(dev, "error during DMA\n");
  260. return -EIO;
  261. }
  262. return 0;
  263. }
  264. static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
  265. {
  266. struct tmio_sd_priv *priv = dev_get_priv(dev);
  267. size_t len = data->blocks * data->blocksize;
  268. void *buf;
  269. enum dma_data_direction dir;
  270. dma_addr_t dma_addr;
  271. u32 poll_flag, tmp;
  272. int ret;
  273. tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
  274. tmp |= priv->idma_bus_width;
  275. if (data->flags & MMC_DATA_READ) {
  276. buf = data->dest;
  277. dir = DMA_FROM_DEVICE;
  278. /*
  279. * The DMA READ completion flag position differs on Socionext
  280. * and Renesas SoCs. It is bit 20 on Socionext SoCs and using
  281. * bit 17 is a hardware bug and forbidden. It is either bit 17
  282. * or bit 20 on Renesas SoCs, depending on SoC.
  283. */
  284. poll_flag = priv->read_poll_flag;
  285. tmp |= TMIO_SD_DMA_MODE_DIR_RD;
  286. } else {
  287. buf = (void *)data->src;
  288. dir = DMA_TO_DEVICE;
  289. poll_flag = TMIO_SD_DMA_INFO1_END_WR;
  290. tmp &= ~TMIO_SD_DMA_MODE_DIR_RD;
  291. }
  292. tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
  293. dma_addr = dma_map_single(buf, len, dir);
  294. tmio_sd_dma_start(priv, dma_addr);
  295. ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
  296. if (poll_flag == TMIO_SD_DMA_INFO1_END_RD)
  297. udelay(1);
  298. dma_unmap_single(dma_addr, len, dir);
  299. return ret;
  300. }
  301. /* check if the address is DMA'able */
  302. static bool tmio_sd_addr_is_dmaable(struct mmc_data *data)
  303. {
  304. uintptr_t addr = (uintptr_t)data->src;
  305. if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
  306. return false;
  307. #if defined(CONFIG_RCAR_GEN3)
  308. if (!(data->flags & MMC_DATA_READ) && !IS_ALIGNED(addr, 128))
  309. return false;
  310. /* Gen3 DMA has 32bit limit */
  311. if (addr >> 32)
  312. return false;
  313. #endif
  314. #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
  315. defined(CONFIG_SPL_BUILD)
  316. /*
  317. * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
  318. * of L2, which is unreachable from the DMA engine.
  319. */
  320. if (addr < CONFIG_SPL_STACK)
  321. return false;
  322. #endif
  323. return true;
  324. }
  325. int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  326. struct mmc_data *data)
  327. {
  328. struct tmio_sd_priv *priv = dev_get_priv(dev);
  329. int ret;
  330. u32 tmp;
  331. if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) {
  332. dev_err(dev, "command busy\n");
  333. return -EBUSY;
  334. }
  335. /* clear all status flags */
  336. tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
  337. tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
  338. /* disable DMA once */
  339. tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
  340. tmp &= ~TMIO_SD_EXTMODE_DMA_EN;
  341. tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
  342. tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG);
  343. tmp = cmd->cmdidx;
  344. if (data) {
  345. tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE);
  346. tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT);
  347. /* Do not send CMD12 automatically */
  348. tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA;
  349. if (data->blocks > 1)
  350. tmp |= TMIO_SD_CMD_MULTI;
  351. if (data->flags & MMC_DATA_READ)
  352. tmp |= TMIO_SD_CMD_RD;
  353. }
  354. /*
  355. * Do not use the response type auto-detection on this hardware.
  356. * CMD8, for example, has different response types on SD and eMMC,
  357. * while this controller always assumes the response type for SD.
  358. * Set the response type manually.
  359. */
  360. switch (cmd->resp_type) {
  361. case MMC_RSP_NONE:
  362. tmp |= TMIO_SD_CMD_RSP_NONE;
  363. break;
  364. case MMC_RSP_R1:
  365. tmp |= TMIO_SD_CMD_RSP_R1;
  366. break;
  367. case MMC_RSP_R1b:
  368. tmp |= TMIO_SD_CMD_RSP_R1B;
  369. break;
  370. case MMC_RSP_R2:
  371. tmp |= TMIO_SD_CMD_RSP_R2;
  372. break;
  373. case MMC_RSP_R3:
  374. tmp |= TMIO_SD_CMD_RSP_R3;
  375. break;
  376. default:
  377. dev_err(dev, "unknown response type\n");
  378. return -EINVAL;
  379. }
  380. dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
  381. cmd->cmdidx, tmp, cmd->cmdarg);
  382. tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
  383. ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
  384. TMIO_SD_INFO1_RSP);
  385. if (ret)
  386. return ret;
  387. if (cmd->resp_type & MMC_RSP_136) {
  388. u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76);
  389. u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54);
  390. u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32);
  391. u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10);
  392. cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
  393. ((rsp_103_72 & 0xff000000) >> 24);
  394. cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
  395. ((rsp_71_40 & 0xff000000) >> 24);
  396. cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
  397. ((rsp_39_8 & 0xff000000) >> 24);
  398. cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
  399. } else {
  400. /* bit 39-8 */
  401. cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10);
  402. }
  403. if (data) {
  404. /* use DMA if the HW supports it and the buffer is aligned */
  405. if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
  406. tmio_sd_addr_is_dmaable(data))
  407. ret = tmio_sd_dma_xfer(dev, data);
  408. else
  409. ret = tmio_sd_pio_xfer(dev, cmd, data);
  410. if (ret)
  411. return ret;
  412. ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
  413. TMIO_SD_INFO1_CMP);
  414. if (ret)
  415. return ret;
  416. }
  417. return tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
  418. TMIO_SD_INFO2_SCLKDIVEN);
  419. }
  420. static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
  421. struct mmc *mmc)
  422. {
  423. u32 val, tmp;
  424. switch (mmc->bus_width) {
  425. case 0:
  426. case 1:
  427. val = TMIO_SD_OPTION_WIDTH_1;
  428. break;
  429. case 4:
  430. val = TMIO_SD_OPTION_WIDTH_4;
  431. break;
  432. case 8:
  433. val = TMIO_SD_OPTION_WIDTH_8;
  434. break;
  435. default:
  436. return -EINVAL;
  437. }
  438. tmp = tmio_sd_readl(priv, TMIO_SD_OPTION);
  439. tmp &= ~TMIO_SD_OPTION_WIDTH_MASK;
  440. tmp |= val;
  441. tmio_sd_writel(priv, tmp, TMIO_SD_OPTION);
  442. return 0;
  443. }
  444. static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
  445. struct mmc *mmc)
  446. {
  447. u32 tmp;
  448. tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE);
  449. if (mmc->ddr_mode)
  450. tmp |= TMIO_SD_IF_MODE_DDR;
  451. else
  452. tmp &= ~TMIO_SD_IF_MODE_DDR;
  453. tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
  454. }
  455. static ulong tmio_sd_clk_get_rate(struct tmio_sd_priv *priv)
  456. {
  457. return priv->clk_get_rate(priv);
  458. }
  459. static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc)
  460. {
  461. unsigned int divisor;
  462. u32 tmp, val = 0;
  463. ulong mclk;
  464. if (mmc->clock) {
  465. mclk = tmio_sd_clk_get_rate(priv);
  466. divisor = DIV_ROUND_UP(mclk, mmc->clock);
  467. /* Do not set divider to 0xff in DDR mode */
  468. if (mmc->ddr_mode && (divisor == 1))
  469. divisor = 2;
  470. if (divisor <= 1)
  471. val = (priv->caps & TMIO_SD_CAP_RCAR) ?
  472. TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
  473. else if (divisor <= 2)
  474. val = TMIO_SD_CLKCTL_DIV2;
  475. else if (divisor <= 4)
  476. val = TMIO_SD_CLKCTL_DIV4;
  477. else if (divisor <= 8)
  478. val = TMIO_SD_CLKCTL_DIV8;
  479. else if (divisor <= 16)
  480. val = TMIO_SD_CLKCTL_DIV16;
  481. else if (divisor <= 32)
  482. val = TMIO_SD_CLKCTL_DIV32;
  483. else if (divisor <= 64)
  484. val = TMIO_SD_CLKCTL_DIV64;
  485. else if (divisor <= 128)
  486. val = TMIO_SD_CLKCTL_DIV128;
  487. else if (divisor <= 256)
  488. val = TMIO_SD_CLKCTL_DIV256;
  489. else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024))
  490. val = TMIO_SD_CLKCTL_DIV512;
  491. else
  492. val = TMIO_SD_CLKCTL_DIV1024;
  493. }
  494. tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  495. if (mmc->clock &&
  496. !((tmp & TMIO_SD_CLKCTL_SCLKEN) &&
  497. ((tmp & TMIO_SD_CLKCTL_DIV_MASK) == val))) {
  498. /*
  499. * Stop the clock before changing its rate
  500. * to avoid a glitch signal
  501. */
  502. tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
  503. tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
  504. /* Change the clock rate. */
  505. tmp &= ~TMIO_SD_CLKCTL_DIV_MASK;
  506. tmp |= val;
  507. }
  508. /* Enable or Disable the clock */
  509. if (mmc->clk_disable) {
  510. tmp |= TMIO_SD_CLKCTL_OFFEN;
  511. tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
  512. } else {
  513. tmp &= ~TMIO_SD_CLKCTL_OFFEN;
  514. tmp |= TMIO_SD_CLKCTL_SCLKEN;
  515. }
  516. tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
  517. udelay(1000);
  518. }
  519. static void tmio_sd_set_pins(struct udevice *dev)
  520. {
  521. __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
  522. #ifdef CONFIG_DM_REGULATOR
  523. struct tmio_sd_priv *priv = dev_get_priv(dev);
  524. if (priv->vqmmc_dev) {
  525. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
  526. regulator_set_value(priv->vqmmc_dev, 1800000);
  527. else
  528. regulator_set_value(priv->vqmmc_dev, 3300000);
  529. regulator_set_enable(priv->vqmmc_dev, true);
  530. }
  531. #endif
  532. #ifdef CONFIG_PINCTRL
  533. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
  534. pinctrl_select_state(dev, "state_uhs");
  535. else
  536. pinctrl_select_state(dev, "default");
  537. #endif
  538. }
  539. int tmio_sd_set_ios(struct udevice *dev)
  540. {
  541. struct tmio_sd_priv *priv = dev_get_priv(dev);
  542. struct mmc *mmc = mmc_get_mmc_dev(dev);
  543. int ret;
  544. dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
  545. mmc->clock, mmc->ddr_mode, mmc->bus_width);
  546. tmio_sd_set_clk_rate(priv, mmc);
  547. ret = tmio_sd_set_bus_width(priv, mmc);
  548. if (ret)
  549. return ret;
  550. tmio_sd_set_ddr_mode(priv, mmc);
  551. tmio_sd_set_pins(dev);
  552. return 0;
  553. }
  554. int tmio_sd_get_cd(struct udevice *dev)
  555. {
  556. struct tmio_sd_priv *priv = dev_get_priv(dev);
  557. if (priv->caps & TMIO_SD_CAP_NONREMOVABLE)
  558. return 1;
  559. return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) &
  560. TMIO_SD_INFO1_CD);
  561. }
  562. static void tmio_sd_host_init(struct tmio_sd_priv *priv)
  563. {
  564. u32 tmp;
  565. /* soft reset of the host */
  566. tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST);
  567. tmp &= ~TMIO_SD_SOFT_RST_RSTX;
  568. tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
  569. tmp |= TMIO_SD_SOFT_RST_RSTX;
  570. tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
  571. /* FIXME: implement eMMC hw_reset */
  572. tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP);
  573. /*
  574. * Connected to 32bit AXI.
  575. * This register dropped backward compatibility at version 0x10.
  576. * Write an appropriate value depending on the IP version.
  577. */
  578. if (priv->version >= 0x10) {
  579. if (priv->caps & TMIO_SD_CAP_64BIT)
  580. tmio_sd_writel(priv, 0x000, TMIO_SD_HOST_MODE);
  581. else
  582. tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
  583. } else {
  584. tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
  585. }
  586. if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
  587. tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
  588. tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
  589. tmp |= priv->idma_bus_width;
  590. tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
  591. }
  592. }
  593. int tmio_sd_bind(struct udevice *dev)
  594. {
  595. struct tmio_sd_plat *plat = dev_get_plat(dev);
  596. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  597. }
  598. int tmio_sd_probe(struct udevice *dev, u32 quirks)
  599. {
  600. struct tmio_sd_plat *plat = dev_get_plat(dev);
  601. struct tmio_sd_priv *priv = dev_get_priv(dev);
  602. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  603. fdt_addr_t base;
  604. ulong mclk;
  605. int ret;
  606. base = dev_read_addr(dev);
  607. if (base == FDT_ADDR_T_NONE)
  608. return -EINVAL;
  609. priv->regbase = devm_ioremap(dev, base, SZ_2K);
  610. if (!priv->regbase)
  611. return -ENOMEM;
  612. #ifdef CONFIG_DM_REGULATOR
  613. device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
  614. if (priv->vqmmc_dev)
  615. regulator_set_value(priv->vqmmc_dev, 3300000);
  616. #endif
  617. ret = mmc_of_parse(dev, &plat->cfg);
  618. if (ret < 0) {
  619. dev_err(dev, "failed to parse host caps\n");
  620. return ret;
  621. }
  622. plat->cfg.name = dev->name;
  623. plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  624. if (quirks)
  625. priv->caps = quirks;
  626. priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) &
  627. TMIO_SD_VERSION_IP;
  628. dev_dbg(dev, "version %x\n", priv->version);
  629. if (priv->version >= 0x10) {
  630. priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
  631. priv->caps |= TMIO_SD_CAP_DIV1024;
  632. }
  633. if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
  634. NULL))
  635. priv->caps |= TMIO_SD_CAP_NONREMOVABLE;
  636. tmio_sd_host_init(priv);
  637. mclk = tmio_sd_clk_get_rate(priv);
  638. plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
  639. plat->cfg.f_min = mclk /
  640. (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
  641. plat->cfg.f_max = mclk;
  642. if (quirks & TMIO_SD_CAP_16BIT)
  643. plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */
  644. else
  645. plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
  646. upriv->mmc = &plat->mmc;
  647. return 0;
  648. }