sh_mmcif.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MMCIF driver.
  4. *
  5. * Copyright (C) 2011 Renesas Solutions Corp.
  6. */
  7. #include <config.h>
  8. #include <common.h>
  9. #include <log.h>
  10. #include <watchdog.h>
  11. #include <command.h>
  12. #include <mmc.h>
  13. #include <clk.h>
  14. #include <dm.h>
  15. #include <malloc.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. #include <linux/errno.h>
  20. #include <linux/compat.h>
  21. #include <linux/io.h>
  22. #include <linux/sizes.h>
  23. #include "sh_mmcif.h"
  24. #include <asm/global_data.h>
  25. #define DRIVER_NAME "sh_mmcif"
  26. static int sh_mmcif_intr(void *dev_id)
  27. {
  28. struct sh_mmcif_host *host = dev_id;
  29. u32 state = 0;
  30. state = sh_mmcif_read(&host->regs->ce_int);
  31. state &= sh_mmcif_read(&host->regs->ce_int_mask);
  32. if (state & INT_RBSYE) {
  33. sh_mmcif_write(~(INT_RBSYE | INT_CRSPE), &host->regs->ce_int);
  34. sh_mmcif_bitclr(MASK_MRBSYE, &host->regs->ce_int_mask);
  35. goto end;
  36. } else if (state & INT_CRSPE) {
  37. sh_mmcif_write(~INT_CRSPE, &host->regs->ce_int);
  38. sh_mmcif_bitclr(MASK_MCRSPE, &host->regs->ce_int_mask);
  39. /* one more interrupt (INT_RBSYE) */
  40. if (sh_mmcif_read(&host->regs->ce_cmd_set) & CMD_SET_RBSY)
  41. return -EAGAIN;
  42. goto end;
  43. } else if (state & INT_BUFREN) {
  44. sh_mmcif_write(~INT_BUFREN, &host->regs->ce_int);
  45. sh_mmcif_bitclr(MASK_MBUFREN, &host->regs->ce_int_mask);
  46. goto end;
  47. } else if (state & INT_BUFWEN) {
  48. sh_mmcif_write(~INT_BUFWEN, &host->regs->ce_int);
  49. sh_mmcif_bitclr(MASK_MBUFWEN, &host->regs->ce_int_mask);
  50. goto end;
  51. } else if (state & INT_CMD12DRE) {
  52. sh_mmcif_write(~(INT_CMD12DRE | INT_CMD12RBE | INT_CMD12CRE |
  53. INT_BUFRE), &host->regs->ce_int);
  54. sh_mmcif_bitclr(MASK_MCMD12DRE, &host->regs->ce_int_mask);
  55. goto end;
  56. } else if (state & INT_BUFRE) {
  57. sh_mmcif_write(~INT_BUFRE, &host->regs->ce_int);
  58. sh_mmcif_bitclr(MASK_MBUFRE, &host->regs->ce_int_mask);
  59. goto end;
  60. } else if (state & INT_DTRANE) {
  61. sh_mmcif_write(~INT_DTRANE, &host->regs->ce_int);
  62. sh_mmcif_bitclr(MASK_MDTRANE, &host->regs->ce_int_mask);
  63. goto end;
  64. } else if (state & INT_CMD12RBE) {
  65. sh_mmcif_write(~(INT_CMD12RBE | INT_CMD12CRE),
  66. &host->regs->ce_int);
  67. sh_mmcif_bitclr(MASK_MCMD12RBE, &host->regs->ce_int_mask);
  68. goto end;
  69. } else if (state & INT_ERR_STS) {
  70. /* err interrupts */
  71. sh_mmcif_write(~state, &host->regs->ce_int);
  72. sh_mmcif_bitclr(state, &host->regs->ce_int_mask);
  73. goto err;
  74. } else
  75. return -EAGAIN;
  76. err:
  77. host->sd_error = 1;
  78. debug("%s: int err state = %08x\n", DRIVER_NAME, state);
  79. end:
  80. host->wait_int = 1;
  81. return 0;
  82. }
  83. static int mmcif_wait_interrupt_flag(struct sh_mmcif_host *host)
  84. {
  85. int timeout = 10000000;
  86. while (1) {
  87. timeout--;
  88. if (timeout < 0) {
  89. printf("timeout\n");
  90. return 0;
  91. }
  92. if (!sh_mmcif_intr(host))
  93. break;
  94. udelay(1); /* 1 usec */
  95. }
  96. return 1; /* Return value: NOT 0 = complete waiting */
  97. }
  98. static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
  99. {
  100. sh_mmcif_bitclr(CLK_ENABLE, &host->regs->ce_clk_ctrl);
  101. sh_mmcif_bitclr(CLK_CLEAR, &host->regs->ce_clk_ctrl);
  102. if (!clk)
  103. return;
  104. if (clk == CLKDEV_EMMC_DATA)
  105. sh_mmcif_bitset(CLK_PCLK, &host->regs->ce_clk_ctrl);
  106. else
  107. sh_mmcif_bitset((fls(DIV_ROUND_UP(host->clk,
  108. clk) - 1) - 1) << 16,
  109. &host->regs->ce_clk_ctrl);
  110. sh_mmcif_bitset(CLK_ENABLE, &host->regs->ce_clk_ctrl);
  111. }
  112. static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
  113. {
  114. u32 tmp;
  115. tmp = sh_mmcif_read(&host->regs->ce_clk_ctrl) & (CLK_ENABLE |
  116. CLK_CLEAR);
  117. sh_mmcif_write(SOFT_RST_ON, &host->regs->ce_version);
  118. sh_mmcif_write(SOFT_RST_OFF, &host->regs->ce_version);
  119. sh_mmcif_bitset(tmp | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29,
  120. &host->regs->ce_clk_ctrl);
  121. /* byte swap on */
  122. sh_mmcif_bitset(BUF_ACC_ATYP, &host->regs->ce_buf_acc);
  123. }
  124. static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
  125. {
  126. u32 state1, state2;
  127. int ret, timeout = 10000000;
  128. host->sd_error = 0;
  129. host->wait_int = 0;
  130. state1 = sh_mmcif_read(&host->regs->ce_host_sts1);
  131. state2 = sh_mmcif_read(&host->regs->ce_host_sts2);
  132. debug("%s: ERR HOST_STS1 = %08x\n", \
  133. DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts1));
  134. debug("%s: ERR HOST_STS2 = %08x\n", \
  135. DRIVER_NAME, sh_mmcif_read(&host->regs->ce_host_sts2));
  136. if (state1 & STS1_CMDSEQ) {
  137. debug("%s: Forced end of command sequence\n", DRIVER_NAME);
  138. sh_mmcif_bitset(CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
  139. sh_mmcif_bitset(~CMD_CTRL_BREAK, &host->regs->ce_cmd_ctrl);
  140. while (1) {
  141. timeout--;
  142. if (timeout < 0) {
  143. printf(DRIVER_NAME": Forceed end of " \
  144. "command sequence timeout err\n");
  145. return -EILSEQ;
  146. }
  147. if (!(sh_mmcif_read(&host->regs->ce_host_sts1)
  148. & STS1_CMDSEQ))
  149. break;
  150. }
  151. sh_mmcif_sync_reset(host);
  152. return -EILSEQ;
  153. }
  154. if (state2 & STS2_CRC_ERR)
  155. ret = -EILSEQ;
  156. else if (state2 & STS2_TIMEOUT_ERR)
  157. ret = -ETIMEDOUT;
  158. else
  159. ret = -EILSEQ;
  160. return ret;
  161. }
  162. static int sh_mmcif_single_read(struct sh_mmcif_host *host,
  163. struct mmc_data *data)
  164. {
  165. long time;
  166. u32 blocksize, i;
  167. unsigned long *p = (unsigned long *)data->dest;
  168. if ((unsigned long)p & 0x00000001) {
  169. printf("%s: The data pointer is unaligned.", __func__);
  170. return -EIO;
  171. }
  172. host->wait_int = 0;
  173. /* buf read enable */
  174. sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
  175. time = mmcif_wait_interrupt_flag(host);
  176. if (time == 0 || host->sd_error != 0)
  177. return sh_mmcif_error_manage(host);
  178. host->wait_int = 0;
  179. blocksize = (BLOCK_SIZE_MASK &
  180. sh_mmcif_read(&host->regs->ce_block_set)) + 3;
  181. for (i = 0; i < blocksize / 4; i++)
  182. *p++ = sh_mmcif_read(&host->regs->ce_data);
  183. /* buffer read end */
  184. sh_mmcif_bitset(MASK_MBUFRE, &host->regs->ce_int_mask);
  185. time = mmcif_wait_interrupt_flag(host);
  186. if (time == 0 || host->sd_error != 0)
  187. return sh_mmcif_error_manage(host);
  188. host->wait_int = 0;
  189. return 0;
  190. }
  191. static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
  192. struct mmc_data *data)
  193. {
  194. long time;
  195. u32 blocksize, i, j;
  196. unsigned long *p = (unsigned long *)data->dest;
  197. if ((unsigned long)p & 0x00000001) {
  198. printf("%s: The data pointer is unaligned.", __func__);
  199. return -EIO;
  200. }
  201. host->wait_int = 0;
  202. blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
  203. for (j = 0; j < data->blocks; j++) {
  204. sh_mmcif_bitset(MASK_MBUFREN, &host->regs->ce_int_mask);
  205. time = mmcif_wait_interrupt_flag(host);
  206. if (time == 0 || host->sd_error != 0)
  207. return sh_mmcif_error_manage(host);
  208. host->wait_int = 0;
  209. for (i = 0; i < blocksize / 4; i++)
  210. *p++ = sh_mmcif_read(&host->regs->ce_data);
  211. WATCHDOG_RESET();
  212. }
  213. return 0;
  214. }
  215. static int sh_mmcif_single_write(struct sh_mmcif_host *host,
  216. struct mmc_data *data)
  217. {
  218. long time;
  219. u32 blocksize, i;
  220. const unsigned long *p = (unsigned long *)data->dest;
  221. if ((unsigned long)p & 0x00000001) {
  222. printf("%s: The data pointer is unaligned.", __func__);
  223. return -EIO;
  224. }
  225. host->wait_int = 0;
  226. sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
  227. time = mmcif_wait_interrupt_flag(host);
  228. if (time == 0 || host->sd_error != 0)
  229. return sh_mmcif_error_manage(host);
  230. host->wait_int = 0;
  231. blocksize = (BLOCK_SIZE_MASK &
  232. sh_mmcif_read(&host->regs->ce_block_set)) + 3;
  233. for (i = 0; i < blocksize / 4; i++)
  234. sh_mmcif_write(*p++, &host->regs->ce_data);
  235. /* buffer write end */
  236. sh_mmcif_bitset(MASK_MDTRANE, &host->regs->ce_int_mask);
  237. time = mmcif_wait_interrupt_flag(host);
  238. if (time == 0 || host->sd_error != 0)
  239. return sh_mmcif_error_manage(host);
  240. host->wait_int = 0;
  241. return 0;
  242. }
  243. static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
  244. struct mmc_data *data)
  245. {
  246. long time;
  247. u32 i, j, blocksize;
  248. const unsigned long *p = (unsigned long *)data->dest;
  249. if ((unsigned long)p & 0x00000001) {
  250. printf("%s: The data pointer is unaligned.", __func__);
  251. return -EIO;
  252. }
  253. host->wait_int = 0;
  254. blocksize = BLOCK_SIZE_MASK & sh_mmcif_read(&host->regs->ce_block_set);
  255. for (j = 0; j < data->blocks; j++) {
  256. sh_mmcif_bitset(MASK_MBUFWEN, &host->regs->ce_int_mask);
  257. time = mmcif_wait_interrupt_flag(host);
  258. if (time == 0 || host->sd_error != 0)
  259. return sh_mmcif_error_manage(host);
  260. host->wait_int = 0;
  261. for (i = 0; i < blocksize / 4; i++)
  262. sh_mmcif_write(*p++, &host->regs->ce_data);
  263. WATCHDOG_RESET();
  264. }
  265. return 0;
  266. }
  267. static void sh_mmcif_get_response(struct sh_mmcif_host *host,
  268. struct mmc_cmd *cmd)
  269. {
  270. if (cmd->resp_type & MMC_RSP_136) {
  271. cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp3);
  272. cmd->response[1] = sh_mmcif_read(&host->regs->ce_resp2);
  273. cmd->response[2] = sh_mmcif_read(&host->regs->ce_resp1);
  274. cmd->response[3] = sh_mmcif_read(&host->regs->ce_resp0);
  275. debug(" RESP %08x, %08x, %08x, %08x\n", cmd->response[0],
  276. cmd->response[1], cmd->response[2], cmd->response[3]);
  277. } else {
  278. cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp0);
  279. }
  280. }
  281. static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
  282. struct mmc_cmd *cmd)
  283. {
  284. cmd->response[0] = sh_mmcif_read(&host->regs->ce_resp_cmd12);
  285. }
  286. static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
  287. struct mmc_data *data, struct mmc_cmd *cmd)
  288. {
  289. u32 tmp = 0;
  290. u32 opc = cmd->cmdidx;
  291. /* Response Type check */
  292. switch (cmd->resp_type) {
  293. case MMC_RSP_NONE:
  294. tmp |= CMD_SET_RTYP_NO;
  295. break;
  296. case MMC_RSP_R1:
  297. case MMC_RSP_R1b:
  298. case MMC_RSP_R3:
  299. tmp |= CMD_SET_RTYP_6B;
  300. break;
  301. case MMC_RSP_R2:
  302. tmp |= CMD_SET_RTYP_17B;
  303. break;
  304. default:
  305. printf(DRIVER_NAME": Not support type response.\n");
  306. break;
  307. }
  308. /* RBSY */
  309. if (opc == MMC_CMD_SWITCH)
  310. tmp |= CMD_SET_RBSY;
  311. /* WDAT / DATW */
  312. if (host->data) {
  313. tmp |= CMD_SET_WDAT;
  314. switch (host->bus_width) {
  315. case MMC_BUS_WIDTH_1:
  316. tmp |= CMD_SET_DATW_1;
  317. break;
  318. case MMC_BUS_WIDTH_4:
  319. tmp |= CMD_SET_DATW_4;
  320. break;
  321. case MMC_BUS_WIDTH_8:
  322. tmp |= CMD_SET_DATW_8;
  323. break;
  324. default:
  325. printf(DRIVER_NAME": Not support bus width.\n");
  326. break;
  327. }
  328. }
  329. /* DWEN */
  330. if (opc == MMC_CMD_WRITE_SINGLE_BLOCK ||
  331. opc == MMC_CMD_WRITE_MULTIPLE_BLOCK)
  332. tmp |= CMD_SET_DWEN;
  333. /* CMLTE/CMD12EN */
  334. if (opc == MMC_CMD_READ_MULTIPLE_BLOCK ||
  335. opc == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
  336. tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
  337. sh_mmcif_bitset(data->blocks << 16, &host->regs->ce_block_set);
  338. }
  339. /* RIDXC[1:0] check bits */
  340. if (opc == MMC_CMD_SEND_OP_COND || opc == MMC_CMD_ALL_SEND_CID ||
  341. opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
  342. tmp |= CMD_SET_RIDXC_BITS;
  343. /* RCRC7C[1:0] check bits */
  344. if (opc == MMC_CMD_SEND_OP_COND)
  345. tmp |= CMD_SET_CRC7C_BITS;
  346. /* RCRC7C[1:0] internal CRC7 */
  347. if (opc == MMC_CMD_ALL_SEND_CID ||
  348. opc == MMC_CMD_SEND_CSD || opc == MMC_CMD_SEND_CID)
  349. tmp |= CMD_SET_CRC7C_INTERNAL;
  350. return opc = ((opc << 24) | tmp);
  351. }
  352. static u32 sh_mmcif_data_trans(struct sh_mmcif_host *host,
  353. struct mmc_data *data, u16 opc)
  354. {
  355. u32 ret;
  356. switch (opc) {
  357. case MMC_CMD_READ_MULTIPLE_BLOCK:
  358. ret = sh_mmcif_multi_read(host, data);
  359. break;
  360. case MMC_CMD_WRITE_MULTIPLE_BLOCK:
  361. ret = sh_mmcif_multi_write(host, data);
  362. break;
  363. case MMC_CMD_WRITE_SINGLE_BLOCK:
  364. ret = sh_mmcif_single_write(host, data);
  365. break;
  366. case MMC_CMD_READ_SINGLE_BLOCK:
  367. case MMC_CMD_SEND_EXT_CSD:
  368. ret = sh_mmcif_single_read(host, data);
  369. break;
  370. default:
  371. printf(DRIVER_NAME": NOT SUPPORT CMD = d'%08d\n", opc);
  372. ret = -EINVAL;
  373. break;
  374. }
  375. return ret;
  376. }
  377. static int sh_mmcif_start_cmd(struct sh_mmcif_host *host,
  378. struct mmc_data *data, struct mmc_cmd *cmd)
  379. {
  380. long time;
  381. int ret = 0, mask = 0;
  382. u32 opc = cmd->cmdidx;
  383. if (opc == MMC_CMD_STOP_TRANSMISSION) {
  384. /* MMCIF sends the STOP command automatically */
  385. if (host->last_cmd == MMC_CMD_READ_MULTIPLE_BLOCK)
  386. sh_mmcif_bitset(MASK_MCMD12DRE,
  387. &host->regs->ce_int_mask);
  388. else
  389. sh_mmcif_bitset(MASK_MCMD12RBE,
  390. &host->regs->ce_int_mask);
  391. time = mmcif_wait_interrupt_flag(host);
  392. if (time == 0 || host->sd_error != 0)
  393. return sh_mmcif_error_manage(host);
  394. sh_mmcif_get_cmd12response(host, cmd);
  395. return 0;
  396. }
  397. if (opc == MMC_CMD_SWITCH)
  398. mask = MASK_MRBSYE;
  399. else
  400. mask = MASK_MCRSPE;
  401. mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
  402. MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
  403. MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
  404. MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
  405. if (host->data) {
  406. sh_mmcif_write(0, &host->regs->ce_block_set);
  407. sh_mmcif_write(data->blocksize, &host->regs->ce_block_set);
  408. }
  409. opc = sh_mmcif_set_cmd(host, data, cmd);
  410. sh_mmcif_write(INT_START_MAGIC, &host->regs->ce_int);
  411. sh_mmcif_write(mask, &host->regs->ce_int_mask);
  412. debug("CMD%d ARG:%08x\n", cmd->cmdidx, cmd->cmdarg);
  413. /* set arg */
  414. sh_mmcif_write(cmd->cmdarg, &host->regs->ce_arg);
  415. host->wait_int = 0;
  416. /* set cmd */
  417. sh_mmcif_write(opc, &host->regs->ce_cmd_set);
  418. time = mmcif_wait_interrupt_flag(host);
  419. if (time == 0)
  420. return sh_mmcif_error_manage(host);
  421. if (host->sd_error) {
  422. switch (cmd->cmdidx) {
  423. case MMC_CMD_ALL_SEND_CID:
  424. case MMC_CMD_SELECT_CARD:
  425. case MMC_CMD_APP_CMD:
  426. ret = -ETIMEDOUT;
  427. break;
  428. default:
  429. printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx);
  430. ret = sh_mmcif_error_manage(host);
  431. break;
  432. }
  433. host->sd_error = 0;
  434. host->wait_int = 0;
  435. return ret;
  436. }
  437. /* if no response */
  438. if (!(opc & 0x00C00000))
  439. return 0;
  440. if (host->wait_int == 1) {
  441. sh_mmcif_get_response(host, cmd);
  442. host->wait_int = 0;
  443. }
  444. if (host->data)
  445. ret = sh_mmcif_data_trans(host, data, cmd->cmdidx);
  446. host->last_cmd = cmd->cmdidx;
  447. return ret;
  448. }
  449. static int sh_mmcif_send_cmd_common(struct sh_mmcif_host *host,
  450. struct mmc_cmd *cmd, struct mmc_data *data)
  451. {
  452. int ret;
  453. WATCHDOG_RESET();
  454. switch (cmd->cmdidx) {
  455. case MMC_CMD_APP_CMD:
  456. return -ETIMEDOUT;
  457. case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
  458. if (data)
  459. /* ext_csd */
  460. break;
  461. else
  462. /* send_if_cond cmd (not support) */
  463. return -ETIMEDOUT;
  464. default:
  465. break;
  466. }
  467. host->sd_error = 0;
  468. host->data = data;
  469. ret = sh_mmcif_start_cmd(host, data, cmd);
  470. host->data = NULL;
  471. return ret;
  472. }
  473. static int sh_mmcif_set_ios_common(struct sh_mmcif_host *host, struct mmc *mmc)
  474. {
  475. if (mmc->clock)
  476. sh_mmcif_clock_control(host, mmc->clock);
  477. if (mmc->bus_width == 8)
  478. host->bus_width = MMC_BUS_WIDTH_8;
  479. else if (mmc->bus_width == 4)
  480. host->bus_width = MMC_BUS_WIDTH_4;
  481. else
  482. host->bus_width = MMC_BUS_WIDTH_1;
  483. debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width);
  484. return 0;
  485. }
  486. static int sh_mmcif_initialize_common(struct sh_mmcif_host *host)
  487. {
  488. sh_mmcif_sync_reset(host);
  489. sh_mmcif_write(MASK_ALL, &host->regs->ce_int_mask);
  490. return 0;
  491. }
  492. #ifndef CONFIG_DM_MMC
  493. static void *mmc_priv(struct mmc *mmc)
  494. {
  495. return (void *)mmc->priv;
  496. }
  497. static int sh_mmcif_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  498. struct mmc_data *data)
  499. {
  500. struct sh_mmcif_host *host = mmc_priv(mmc);
  501. return sh_mmcif_send_cmd_common(host, cmd, data);
  502. }
  503. static int sh_mmcif_set_ios(struct mmc *mmc)
  504. {
  505. struct sh_mmcif_host *host = mmc_priv(mmc);
  506. return sh_mmcif_set_ios_common(host, mmc);
  507. }
  508. static int sh_mmcif_initialize(struct mmc *mmc)
  509. {
  510. struct sh_mmcif_host *host = mmc_priv(mmc);
  511. return sh_mmcif_initialize_common(host);
  512. }
  513. static const struct mmc_ops sh_mmcif_ops = {
  514. .send_cmd = sh_mmcif_send_cmd,
  515. .set_ios = sh_mmcif_set_ios,
  516. .init = sh_mmcif_initialize,
  517. };
  518. static struct mmc_config sh_mmcif_cfg = {
  519. .name = DRIVER_NAME,
  520. .ops = &sh_mmcif_ops,
  521. .host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT |
  522. MMC_MODE_8BIT,
  523. .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
  524. .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  525. };
  526. int mmcif_mmc_init(void)
  527. {
  528. struct mmc *mmc;
  529. struct sh_mmcif_host *host = NULL;
  530. host = malloc(sizeof(struct sh_mmcif_host));
  531. if (!host)
  532. return -ENOMEM;
  533. memset(host, 0, sizeof(*host));
  534. host->regs = (struct sh_mmcif_regs *)CONFIG_SH_MMCIF_ADDR;
  535. host->clk = CONFIG_SH_MMCIF_CLK;
  536. sh_mmcif_cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
  537. sh_mmcif_cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
  538. mmc = mmc_create(&sh_mmcif_cfg, host);
  539. if (mmc == NULL) {
  540. free(host);
  541. return -ENOMEM;
  542. }
  543. return 0;
  544. }
  545. #else
  546. struct sh_mmcif_plat {
  547. struct mmc_config cfg;
  548. struct mmc mmc;
  549. };
  550. int sh_mmcif_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  551. struct mmc_data *data)
  552. {
  553. struct sh_mmcif_host *host = dev_get_priv(dev);
  554. return sh_mmcif_send_cmd_common(host, cmd, data);
  555. }
  556. int sh_mmcif_dm_set_ios(struct udevice *dev)
  557. {
  558. struct sh_mmcif_host *host = dev_get_priv(dev);
  559. struct mmc *mmc = mmc_get_mmc_dev(dev);
  560. return sh_mmcif_set_ios_common(host, mmc);
  561. }
  562. static const struct dm_mmc_ops sh_mmcif_dm_ops = {
  563. .send_cmd = sh_mmcif_dm_send_cmd,
  564. .set_ios = sh_mmcif_dm_set_ios,
  565. };
  566. static int sh_mmcif_dm_bind(struct udevice *dev)
  567. {
  568. struct sh_mmcif_plat *plat = dev_get_plat(dev);
  569. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  570. }
  571. static int sh_mmcif_dm_probe(struct udevice *dev)
  572. {
  573. struct sh_mmcif_plat *plat = dev_get_plat(dev);
  574. struct sh_mmcif_host *host = dev_get_priv(dev);
  575. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  576. struct clk sh_mmcif_clk;
  577. fdt_addr_t base;
  578. int ret;
  579. base = dev_read_addr(dev);
  580. if (base == FDT_ADDR_T_NONE)
  581. return -EINVAL;
  582. host->regs = (struct sh_mmcif_regs *)devm_ioremap(dev, base, SZ_2K);
  583. if (!host->regs)
  584. return -ENOMEM;
  585. ret = clk_get_by_index(dev, 0, &sh_mmcif_clk);
  586. if (ret) {
  587. debug("failed to get clock, ret=%d\n", ret);
  588. return ret;
  589. }
  590. ret = clk_enable(&sh_mmcif_clk);
  591. if (ret) {
  592. debug("failed to enable clock, ret=%d\n", ret);
  593. return ret;
  594. }
  595. host->clk = clk_set_rate(&sh_mmcif_clk, 97500000);
  596. plat->cfg.name = dev->name;
  597. plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
  598. switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
  599. 1)) {
  600. case 8:
  601. plat->cfg.host_caps |= MMC_MODE_8BIT;
  602. break;
  603. case 4:
  604. plat->cfg.host_caps |= MMC_MODE_4BIT;
  605. break;
  606. case 1:
  607. break;
  608. default:
  609. dev_err(dev, "Invalid \"bus-width\" value\n");
  610. return -EINVAL;
  611. }
  612. sh_mmcif_initialize_common(host);
  613. plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
  614. plat->cfg.f_min = MMC_CLK_DIV_MIN(host->clk);
  615. plat->cfg.f_max = MMC_CLK_DIV_MAX(host->clk);
  616. plat->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  617. upriv->mmc = &plat->mmc;
  618. return 0;
  619. }
  620. static const struct udevice_id sh_mmcif_sd_match[] = {
  621. { .compatible = "renesas,sh-mmcif" },
  622. { /* sentinel */ }
  623. };
  624. U_BOOT_DRIVER(sh_mmcif_mmc) = {
  625. .name = "sh-mmcif",
  626. .id = UCLASS_MMC,
  627. .of_match = sh_mmcif_sd_match,
  628. .bind = sh_mmcif_dm_bind,
  629. .probe = sh_mmcif_dm_probe,
  630. .priv_auto = sizeof(struct sh_mmcif_host),
  631. .plat_auto = sizeof(struct sh_mmcif_plat),
  632. .ops = &sh_mmcif_dm_ops,
  633. };
  634. #endif