sdhci-cadence.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <asm/global_data.h>
  9. #include <dm/device_compat.h>
  10. #include <linux/bitfield.h>
  11. #include <linux/bitops.h>
  12. #include <linux/bug.h>
  13. #include <linux/io.h>
  14. #include <linux/iopoll.h>
  15. #include <linux/sizes.h>
  16. #include <linux/libfdt.h>
  17. #include <mmc.h>
  18. #include <sdhci.h>
  19. /* HRS - Host Register Set (specific to Cadence) */
  20. #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
  21. #define SDHCI_CDNS_HRS04_ACK BIT(26)
  22. #define SDHCI_CDNS_HRS04_RD BIT(25)
  23. #define SDHCI_CDNS_HRS04_WR BIT(24)
  24. #define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
  25. #define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
  26. #define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
  27. #define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
  28. #define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
  29. #define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
  30. #define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
  31. #define SDHCI_CDNS_HRS06_MODE_SD 0x0
  32. #define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
  33. #define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
  34. #define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
  35. #define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
  36. #define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6
  37. /* SRS - Slot Register Set (SDHCI-compatible) */
  38. #define SDHCI_CDNS_SRS_BASE 0x200
  39. /* PHY */
  40. #define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
  41. #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
  42. #define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
  43. #define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
  44. #define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
  45. #define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
  46. #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
  47. #define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
  48. #define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
  49. #define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b
  50. #define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
  51. #define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
  52. /*
  53. * The tuned val register is 6 bit-wide, but not the whole of the range is
  54. * available. The range 0-42 seems to be available (then 43 wraps around to 0)
  55. * but I am not quite sure if it is official. Use only 0 to 39 for safety.
  56. */
  57. #define SDHCI_CDNS_MAX_TUNING_LOOP 40
  58. struct sdhci_cdns_plat {
  59. struct mmc_config cfg;
  60. struct mmc mmc;
  61. void __iomem *hrs_addr;
  62. };
  63. struct sdhci_cdns_phy_cfg {
  64. const char *property;
  65. u8 addr;
  66. };
  67. static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
  68. { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
  69. { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
  70. { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
  71. { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
  72. { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
  73. { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
  74. { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
  75. { "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
  76. { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
  77. { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
  78. { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
  79. };
  80. static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
  81. u8 addr, u8 data)
  82. {
  83. void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;
  84. u32 tmp;
  85. int ret;
  86. tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
  87. FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
  88. writel(tmp, reg);
  89. tmp |= SDHCI_CDNS_HRS04_WR;
  90. writel(tmp, reg);
  91. ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10);
  92. if (ret)
  93. return ret;
  94. tmp &= ~SDHCI_CDNS_HRS04_WR;
  95. writel(tmp, reg);
  96. return 0;
  97. }
  98. static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat,
  99. const void *fdt, int nodeoffset)
  100. {
  101. const fdt32_t *prop;
  102. int ret, i;
  103. for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
  104. prop = fdt_getprop(fdt, nodeoffset,
  105. sdhci_cdns_phy_cfgs[i].property, NULL);
  106. if (!prop)
  107. continue;
  108. ret = sdhci_cdns_write_phy_reg(plat,
  109. sdhci_cdns_phy_cfgs[i].addr,
  110. fdt32_to_cpu(*prop));
  111. if (ret)
  112. return ret;
  113. }
  114. return 0;
  115. }
  116. static void sdhci_cdns_set_control_reg(struct sdhci_host *host)
  117. {
  118. struct mmc *mmc = host->mmc;
  119. struct sdhci_cdns_plat *plat = dev_get_plat(mmc->dev);
  120. unsigned int clock = mmc->clock;
  121. u32 mode, tmp;
  122. /*
  123. * REVISIT:
  124. * The mode should be decided by MMC_TIMING_* like Linux, but
  125. * U-Boot does not support timing. Use the clock frequency instead.
  126. */
  127. if (clock <= 26000000) {
  128. mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */
  129. } else if (clock <= 52000000) {
  130. if (mmc->ddr_mode)
  131. mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
  132. else
  133. mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
  134. } else {
  135. if (mmc->ddr_mode)
  136. mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
  137. else
  138. mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
  139. }
  140. tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06);
  141. tmp &= ~SDHCI_CDNS_HRS06_MODE;
  142. tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
  143. writel(tmp, plat->hrs_addr + SDHCI_CDNS_HRS06);
  144. }
  145. static const struct sdhci_ops sdhci_cdns_ops = {
  146. .set_control_reg = sdhci_cdns_set_control_reg,
  147. };
  148. static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat,
  149. unsigned int val)
  150. {
  151. void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS06;
  152. u32 tmp;
  153. int i, ret;
  154. if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
  155. return -EINVAL;
  156. tmp = readl(reg);
  157. tmp &= ~SDHCI_CDNS_HRS06_TUNE;
  158. tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
  159. /*
  160. * Workaround for IP errata:
  161. * The IP6116 SD/eMMC PHY design has a timing issue on receive data
  162. * path. Send tune request twice.
  163. */
  164. for (i = 0; i < 2; i++) {
  165. tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
  166. writel(tmp, reg);
  167. ret = readl_poll_timeout(reg, tmp,
  168. !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), 1);
  169. if (ret)
  170. return ret;
  171. }
  172. return 0;
  173. }
  174. static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev,
  175. unsigned int opcode)
  176. {
  177. struct sdhci_cdns_plat *plat = dev_get_plat(dev);
  178. struct mmc *mmc = &plat->mmc;
  179. int cur_streak = 0;
  180. int max_streak = 0;
  181. int end_of_streak = 0;
  182. int i;
  183. /*
  184. * This handler only implements the eMMC tuning that is specific to
  185. * this controller. The tuning for SD timing should be handled by the
  186. * SDHCI core.
  187. */
  188. if (!IS_MMC(mmc))
  189. return -ENOTSUPP;
  190. if (WARN_ON(opcode != MMC_CMD_SEND_TUNING_BLOCK_HS200))
  191. return -EINVAL;
  192. for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
  193. if (sdhci_cdns_set_tune_val(plat, i) ||
  194. mmc_send_tuning(mmc, opcode, NULL)) { /* bad */
  195. cur_streak = 0;
  196. } else { /* good */
  197. cur_streak++;
  198. if (cur_streak > max_streak) {
  199. max_streak = cur_streak;
  200. end_of_streak = i;
  201. }
  202. }
  203. }
  204. if (!max_streak) {
  205. dev_err(dev, "no tuning point found\n");
  206. return -EIO;
  207. }
  208. return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2);
  209. }
  210. static struct dm_mmc_ops sdhci_cdns_mmc_ops;
  211. static int sdhci_cdns_bind(struct udevice *dev)
  212. {
  213. struct sdhci_cdns_plat *plat = dev_get_plat(dev);
  214. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  215. }
  216. static int sdhci_cdns_probe(struct udevice *dev)
  217. {
  218. DECLARE_GLOBAL_DATA_PTR;
  219. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  220. struct sdhci_cdns_plat *plat = dev_get_plat(dev);
  221. struct sdhci_host *host = dev_get_priv(dev);
  222. fdt_addr_t base;
  223. int ret;
  224. base = dev_read_addr(dev);
  225. if (base == FDT_ADDR_T_NONE)
  226. return -EINVAL;
  227. plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);
  228. if (!plat->hrs_addr)
  229. return -ENOMEM;
  230. host->name = dev->name;
  231. host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
  232. host->ops = &sdhci_cdns_ops;
  233. host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
  234. sdhci_cdns_mmc_ops = sdhci_ops;
  235. #ifdef MMC_SUPPORTS_TUNING
  236. sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning;
  237. #endif
  238. ret = mmc_of_parse(dev, &plat->cfg);
  239. if (ret)
  240. return ret;
  241. ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev_of_offset(dev));
  242. if (ret)
  243. return ret;
  244. host->mmc = &plat->mmc;
  245. host->mmc->dev = dev;
  246. ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
  247. if (ret)
  248. return ret;
  249. upriv->mmc = &plat->mmc;
  250. host->mmc->priv = host;
  251. return sdhci_probe(dev);
  252. }
  253. static const struct udevice_id sdhci_cdns_match[] = {
  254. { .compatible = "socionext,uniphier-sd4hc" },
  255. { .compatible = "cdns,sd4hc" },
  256. { /* sentinel */ }
  257. };
  258. U_BOOT_DRIVER(sdhci_cdns) = {
  259. .name = "sdhci-cdns",
  260. .id = UCLASS_MMC,
  261. .of_match = sdhci_cdns_match,
  262. .bind = sdhci_cdns_bind,
  263. .probe = sdhci_cdns_probe,
  264. .priv_auto = sizeof(struct sdhci_host),
  265. .plat_auto = sizeof(struct sdhci_cdns_plat),
  266. .ops = &sdhci_cdns_mmc_ops,
  267. };