rockchip_dw_mmc.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2013 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <dm.h>
  8. #include <dt-structs.h>
  9. #include <dwmmc.h>
  10. #include <errno.h>
  11. #include <log.h>
  12. #include <mapmem.h>
  13. #include <pwrseq.h>
  14. #include <syscon.h>
  15. #include <asm/gpio.h>
  16. #include <asm/arch-rockchip/clock.h>
  17. #include <asm/arch-rockchip/periph.h>
  18. #include <linux/delay.h>
  19. #include <linux/err.h>
  20. struct rockchip_mmc_plat {
  21. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  22. struct dtd_rockchip_rk3288_dw_mshc dtplat;
  23. #endif
  24. struct mmc_config cfg;
  25. struct mmc mmc;
  26. };
  27. struct rockchip_dwmmc_priv {
  28. struct clk clk;
  29. struct dwmci_host host;
  30. int fifo_depth;
  31. bool fifo_mode;
  32. u32 minmax[2];
  33. };
  34. static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
  35. {
  36. struct udevice *dev = host->priv;
  37. struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
  38. int ret;
  39. ret = clk_set_rate(&priv->clk, freq);
  40. if (ret < 0) {
  41. debug("%s: err=%d\n", __func__, ret);
  42. return ret;
  43. }
  44. return freq;
  45. }
  46. static int rockchip_dwmmc_of_to_plat(struct udevice *dev)
  47. {
  48. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  49. struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
  50. struct dwmci_host *host = &priv->host;
  51. host->name = dev->name;
  52. host->ioaddr = dev_read_addr_ptr(dev);
  53. host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
  54. host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
  55. host->priv = dev;
  56. /* use non-removeable as sdcard and emmc as judgement */
  57. if (dev_read_bool(dev, "non-removable"))
  58. host->dev_index = 0;
  59. else
  60. host->dev_index = 1;
  61. priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
  62. if (priv->fifo_depth < 0)
  63. return -EINVAL;
  64. priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
  65. #ifdef CONFIG_SPL_BUILD
  66. if (!priv->fifo_mode)
  67. priv->fifo_mode = dev_read_bool(dev, "u-boot,spl-fifo-mode");
  68. #endif
  69. /*
  70. * 'clock-freq-min-max' is deprecated
  71. * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
  72. */
  73. if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
  74. int val = dev_read_u32_default(dev, "max-frequency", -EINVAL);
  75. if (val < 0)
  76. return val;
  77. priv->minmax[0] = 400000; /* 400 kHz */
  78. priv->minmax[1] = val;
  79. } else {
  80. debug("%s: 'clock-freq-min-max' property was deprecated.\n",
  81. __func__);
  82. }
  83. #endif
  84. return 0;
  85. }
  86. static int rockchip_dwmmc_probe(struct udevice *dev)
  87. {
  88. struct rockchip_mmc_plat *plat = dev_get_plat(dev);
  89. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  90. struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
  91. struct dwmci_host *host = &priv->host;
  92. int ret;
  93. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  94. struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
  95. host->name = dev->name;
  96. host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
  97. host->buswidth = dtplat->bus_width;
  98. host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
  99. host->priv = dev;
  100. host->dev_index = 0;
  101. priv->fifo_depth = dtplat->fifo_depth;
  102. priv->fifo_mode = 0;
  103. priv->minmax[0] = 400000; /* 400 kHz */
  104. priv->minmax[1] = dtplat->max_frequency;
  105. ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk);
  106. if (ret < 0)
  107. return ret;
  108. #else
  109. ret = clk_get_by_index(dev, 0, &priv->clk);
  110. if (ret < 0)
  111. return ret;
  112. #endif
  113. host->fifoth_val = MSIZE(0x2) |
  114. RX_WMARK(priv->fifo_depth / 2 - 1) |
  115. TX_WMARK(priv->fifo_depth / 2);
  116. host->fifo_mode = priv->fifo_mode;
  117. #ifdef CONFIG_MMC_PWRSEQ
  118. /* Enable power if needed */
  119. ret = mmc_pwrseq_get_power(dev, &plat->cfg);
  120. if (!ret) {
  121. ret = pwrseq_set_power(plat->cfg.pwr_dev, true);
  122. if (ret)
  123. return ret;
  124. }
  125. #endif
  126. dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
  127. host->mmc = &plat->mmc;
  128. host->mmc->priv = &priv->host;
  129. host->mmc->dev = dev;
  130. upriv->mmc = host->mmc;
  131. return dwmci_probe(dev);
  132. }
  133. static int rockchip_dwmmc_bind(struct udevice *dev)
  134. {
  135. struct rockchip_mmc_plat *plat = dev_get_plat(dev);
  136. return dwmci_bind(dev, &plat->mmc, &plat->cfg);
  137. }
  138. static const struct udevice_id rockchip_dwmmc_ids[] = {
  139. { .compatible = "rockchip,rk2928-dw-mshc" },
  140. { .compatible = "rockchip,rk3288-dw-mshc" },
  141. { }
  142. };
  143. U_BOOT_DRIVER(rockchip_rk3288_dw_mshc) = {
  144. .name = "rockchip_rk3288_dw_mshc",
  145. .id = UCLASS_MMC,
  146. .of_match = rockchip_dwmmc_ids,
  147. .of_to_plat = rockchip_dwmmc_of_to_plat,
  148. .ops = &dm_dwmci_ops,
  149. .bind = rockchip_dwmmc_bind,
  150. .probe = rockchip_dwmmc_probe,
  151. .priv_auto = sizeof(struct rockchip_dwmmc_priv),
  152. .plat_auto = sizeof(struct rockchip_mmc_plat),
  153. };
  154. DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3328_dw_mshc)
  155. DM_DRIVER_ALIAS(rockchip_rk3288_dw_mshc, rockchip_rk3368_dw_mshc)