renesas-sdhi.c 29 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <bouncebuf.h>
  7. #include <clk.h>
  8. #include <fdtdec.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <mmc.h>
  12. #include <dm.h>
  13. #include <asm/global_data.h>
  14. #include <dm/device_compat.h>
  15. #include <linux/bitops.h>
  16. #include <linux/compat.h>
  17. #include <linux/delay.h>
  18. #include <linux/dma-direction.h>
  19. #include <linux/io.h>
  20. #include <linux/sizes.h>
  21. #include <power/regulator.h>
  22. #include <asm/unaligned.h>
  23. #include "tmio-common.h"
  24. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  25. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  26. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  27. /* SCC registers */
  28. #define RENESAS_SDHI_SCC_DTCNTL 0x800
  29. #define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
  30. #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
  31. #define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
  32. #define RENESAS_SDHI_SCC_TAPSET 0x804
  33. #define RENESAS_SDHI_SCC_DT2FF 0x808
  34. #define RENESAS_SDHI_SCC_CKSEL 0x80c
  35. #define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
  36. #define RENESAS_SDHI_SCC_RVSCNTL 0x810
  37. #define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
  38. #define RENESAS_SDHI_SCC_RVSREQ 0x814
  39. #define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
  40. #define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
  41. #define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
  42. #define RENESAS_SDHI_SCC_SMPCMP 0x818
  43. #define RENESAS_SDHI_SCC_SMPCMP_CMD_ERR (BIT(24) | BIT(8))
  44. #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24)
  45. #define RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8)
  46. #define RENESAS_SDHI_SCC_TMPPORT2 0x81c
  47. #define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
  48. #define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
  49. #define RENESAS_SDHI_SCC_TMPPORT3 0x828
  50. #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_0 3
  51. #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_1 2
  52. #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_2 1
  53. #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_3 0
  54. #define RENESAS_SDHI_SCC_TMPPORT3_OFFSET_MASK 0x3
  55. #define RENESAS_SDHI_SCC_TMPPORT4 0x82c
  56. #define RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0)
  57. #define RENESAS_SDHI_SCC_TMPPORT5 0x830
  58. #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8)
  59. #define RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8)
  60. #define RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F
  61. #define RENESAS_SDHI_SCC_TMPPORT6 0x834
  62. #define RENESAS_SDHI_SCC_TMPPORT7 0x838
  63. #define RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000
  64. #define RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f
  65. #define RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7)
  66. #define RENESAS_SDHI_MAX_TAP 3
  67. #define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1)
  68. static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = {
  69. { 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 5, 5, 6, 6, 7, 11,
  70. 15, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 21 },
  71. { 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 15,
  72. 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 22 }
  73. };
  74. static const u8 r8a7796_rev1_calib_table[2][CALIB_TABLE_MAX] = {
  75. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 9,
  76. 15, 15, 15, 16, 16, 16, 16, 16, 17, 18, 19, 20, 21, 21, 22, 22 },
  77. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
  78. 2, 9, 16, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 23, 24}
  79. };
  80. static const u8 r8a7796_rev3_calib_table[2][CALIB_TABLE_MAX] = {
  81. { 0, 0, 0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 9, 10,
  82. 11, 12, 13, 15, 16, 17, 17, 18, 19, 19, 20, 21, 21, 22, 23, 23 },
  83. { 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12,
  84. 13, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22, 22, 23, 24, 24 }
  85. };
  86. static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = {
  87. { 0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15,
  88. 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 29 },
  89. { 0, 1, 2, 2, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 15,
  90. 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 31 }
  91. };
  92. static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = {
  93. { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  94. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
  95. { 0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 5, 6, 7, 8, 10, 11,
  96. 12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 }
  97. };
  98. static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv)
  99. {
  100. /* On R-Car Gen3, MMC0 is at 0xee140000 */
  101. return (uintptr_t)(priv->regbase) == 0xee140000;
  102. }
  103. static u32 sd_scc_tmpport_read32(struct tmio_sd_priv *priv, u32 addr)
  104. {
  105. /* read mode */
  106. tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R |
  107. (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
  108. RENESAS_SDHI_SCC_TMPPORT5);
  109. /* access start and stop */
  110. tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
  111. RENESAS_SDHI_SCC_TMPPORT4);
  112. tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
  113. return tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT7);
  114. }
  115. static void sd_scc_tmpport_write32(struct tmio_sd_priv *priv, u32 addr, u32 val)
  116. {
  117. /* write mode */
  118. tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W |
  119. (RENESAS_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr),
  120. RENESAS_SDHI_SCC_TMPPORT5);
  121. tmio_sd_writel(priv, val, RENESAS_SDHI_SCC_TMPPORT6);
  122. /* access start and stop */
  123. tmio_sd_writel(priv, RENESAS_SDHI_SCC_TMPPORT4_DLL_ACC_START,
  124. RENESAS_SDHI_SCC_TMPPORT4);
  125. tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT4);
  126. }
  127. static bool renesas_sdhi_check_scc_error(struct udevice *dev)
  128. {
  129. struct tmio_sd_priv *priv = dev_get_priv(dev);
  130. struct mmc *mmc = mmc_get_mmc_dev(dev);
  131. unsigned long new_tap = priv->tap_set;
  132. unsigned long error_tap = priv->tap_set;
  133. u32 reg, smpcmp;
  134. if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
  135. (mmc->selected_mode != UHS_SDR104) &&
  136. (mmc->selected_mode != MMC_HS_200) &&
  137. (mmc->selected_mode != MMC_HS_400) &&
  138. (priv->nrtaps != 4))
  139. return false;
  140. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
  141. /* Handle automatic tuning correction */
  142. if (reg & RENESAS_SDHI_SCC_RVSCNTL_RVSEN) {
  143. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
  144. if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR) {
  145. tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
  146. return true;
  147. }
  148. return false;
  149. }
  150. /* Handle manual tuning correction */
  151. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSREQ);
  152. if (!reg) /* No error */
  153. return false;
  154. tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
  155. if (mmc->selected_mode == MMC_HS_400) {
  156. /*
  157. * Correction Error Status contains CMD and DAT signal status.
  158. * In HS400, DAT signal based on DS signal, not CLK.
  159. * Therefore, use only CMD status.
  160. */
  161. smpcmp = tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP) &
  162. RENESAS_SDHI_SCC_SMPCMP_CMD_ERR;
  163. switch (smpcmp) {
  164. case 0:
  165. return false; /* No error in CMD signal */
  166. case RENESAS_SDHI_SCC_SMPCMP_CMD_REQUP:
  167. new_tap = (priv->tap_set +
  168. priv->tap_num + 1) % priv->tap_num;
  169. error_tap = (priv->tap_set +
  170. priv->tap_num - 1) % priv->tap_num;
  171. break;
  172. case RENESAS_SDHI_SCC_SMPCMP_CMD_REQDOWN:
  173. new_tap = (priv->tap_set +
  174. priv->tap_num - 1) % priv->tap_num;
  175. error_tap = (priv->tap_set +
  176. priv->tap_num + 1) % priv->tap_num;
  177. break;
  178. default:
  179. return true; /* Need re-tune */
  180. }
  181. if (priv->hs400_bad_tap & BIT(new_tap)) {
  182. /*
  183. * New tap is bad tap (cannot change).
  184. * Compare with HS200 tuning result.
  185. * In HS200 tuning, when smpcmp[error_tap]
  186. * is OK, retune is executed.
  187. */
  188. if (priv->smpcmp & BIT(error_tap))
  189. return true; /* Need retune */
  190. return false; /* cannot change */
  191. }
  192. priv->tap_set = new_tap;
  193. } else {
  194. if (reg & RENESAS_SDHI_SCC_RVSREQ_RVSERR)
  195. return true; /* Need re-tune */
  196. else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPUP)
  197. priv->tap_set = (priv->tap_set +
  198. priv->tap_num + 1) % priv->tap_num;
  199. else if (reg & RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN)
  200. priv->tap_set = (priv->tap_set +
  201. priv->tap_num - 1) % priv->tap_num;
  202. else
  203. return false;
  204. }
  205. /* Set TAP position */
  206. tmio_sd_writel(priv, priv->tap_set >> ((priv->nrtaps == 4) ? 1 : 0),
  207. RENESAS_SDHI_SCC_TAPSET);
  208. return false;
  209. }
  210. static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_sd_priv *priv)
  211. {
  212. u32 calib_code;
  213. if (!priv->adjust_hs400_enable)
  214. return;
  215. if (!priv->needs_adjust_hs400)
  216. return;
  217. if (!priv->adjust_hs400_calib_table)
  218. return;
  219. /*
  220. * Enabled Manual adjust HS400 mode
  221. *
  222. * 1) Disabled Write Protect
  223. * W(addr=0x00, WP_DISABLE_CODE)
  224. *
  225. * 2) Read Calibration code
  226. * read_value = R(addr=0x26)
  227. * 3) Refer to calibration table
  228. * Calibration code = table[read_value]
  229. * 4) Enabled Manual Calibration
  230. * W(addr=0x22, manual mode | Calibration code)
  231. * 5) Set Offset value to TMPPORT3 Reg
  232. */
  233. sd_scc_tmpport_write32(priv, 0x00,
  234. RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
  235. calib_code = sd_scc_tmpport_read32(priv, 0x26);
  236. calib_code &= RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK;
  237. sd_scc_tmpport_write32(priv, 0x22,
  238. RENESAS_SDHI_SCC_TMPPORT_MANUAL_MODE |
  239. priv->adjust_hs400_calib_table[calib_code]);
  240. tmio_sd_writel(priv, priv->adjust_hs400_offset,
  241. RENESAS_SDHI_SCC_TMPPORT3);
  242. /* Clear flag */
  243. priv->needs_adjust_hs400 = false;
  244. }
  245. static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_sd_priv *priv)
  246. {
  247. /* Disabled Manual adjust HS400 mode
  248. *
  249. * 1) Disabled Write Protect
  250. * W(addr=0x00, WP_DISABLE_CODE)
  251. * 2) Disabled Manual Calibration
  252. * W(addr=0x22, 0)
  253. * 3) Clear offset value to TMPPORT3 Reg
  254. */
  255. sd_scc_tmpport_write32(priv, 0x00,
  256. RENESAS_SDHI_SCC_TMPPORT_DISABLE_WP_CODE);
  257. sd_scc_tmpport_write32(priv, 0x22, 0);
  258. tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_TMPPORT3);
  259. }
  260. static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
  261. {
  262. u32 reg;
  263. /* Initialize SCC */
  264. tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
  265. reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  266. reg &= ~TMIO_SD_CLKCTL_SCLKEN;
  267. tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  268. /* Set sampling clock selection range */
  269. tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
  270. RENESAS_SDHI_SCC_DTCNTL_TAPEN,
  271. RENESAS_SDHI_SCC_DTCNTL);
  272. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
  273. reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
  274. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
  275. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
  276. reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
  277. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
  278. tmio_sd_writel(priv, 0x300 /* scc_tappos */,
  279. RENESAS_SDHI_SCC_DT2FF);
  280. reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  281. reg |= TMIO_SD_CLKCTL_SCLKEN;
  282. tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  283. /* Read TAPNUM */
  284. return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
  285. RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
  286. RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
  287. }
  288. static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
  289. {
  290. u32 reg;
  291. /* Reset SCC */
  292. reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  293. reg &= ~TMIO_SD_CLKCTL_SCLKEN;
  294. tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  295. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
  296. reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
  297. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
  298. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
  299. reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
  300. RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
  301. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
  302. /* Disable HS400 mode adjustment */
  303. renesas_sdhi_adjust_hs400_mode_disable(priv);
  304. reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  305. reg |= TMIO_SD_CLKCTL_SCLKEN;
  306. tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
  307. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
  308. reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
  309. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
  310. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
  311. reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
  312. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
  313. }
  314. static int renesas_sdhi_hs400(struct udevice *dev)
  315. {
  316. struct tmio_sd_priv *priv = dev_get_priv(dev);
  317. struct mmc *mmc = mmc_get_mmc_dev(dev);
  318. bool hs400 = (mmc->selected_mode == MMC_HS_400);
  319. int ret, taps = hs400 ? priv->nrtaps : 8;
  320. unsigned long new_tap;
  321. u32 reg;
  322. if (taps == 4) /* HS400 on 4tap SoC needs different clock */
  323. ret = clk_set_rate(&priv->clk, 400000000);
  324. else
  325. ret = clk_set_rate(&priv->clk, 200000000);
  326. if (ret < 0)
  327. return ret;
  328. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
  329. reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
  330. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
  331. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
  332. if (hs400) {
  333. reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
  334. RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
  335. } else {
  336. reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
  337. RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
  338. }
  339. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
  340. /* Disable HS400 mode adjustment */
  341. if (!hs400)
  342. renesas_sdhi_adjust_hs400_mode_disable(priv);
  343. tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
  344. RENESAS_SDHI_SCC_DTCNTL_TAPEN,
  345. RENESAS_SDHI_SCC_DTCNTL);
  346. /* Avoid bad TAP */
  347. if (priv->hs400_bad_tap & BIT(priv->tap_set)) {
  348. new_tap = (priv->tap_set +
  349. priv->tap_num + 1) % priv->tap_num;
  350. if (priv->hs400_bad_tap & BIT(new_tap))
  351. new_tap = (priv->tap_set +
  352. priv->tap_num - 1) % priv->tap_num;
  353. if (priv->hs400_bad_tap & BIT(new_tap)) {
  354. new_tap = priv->tap_set;
  355. debug("Three consecutive bad tap is prohibited\n");
  356. }
  357. priv->tap_set = new_tap;
  358. tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
  359. }
  360. if (taps == 4) {
  361. tmio_sd_writel(priv, priv->tap_set >> 1,
  362. RENESAS_SDHI_SCC_TAPSET);
  363. tmio_sd_writel(priv, hs400 ? 0x100 : 0x300,
  364. RENESAS_SDHI_SCC_DT2FF);
  365. } else {
  366. tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
  367. tmio_sd_writel(priv, 0x300, RENESAS_SDHI_SCC_DT2FF);
  368. }
  369. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
  370. reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
  371. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
  372. /* Execute adjust hs400 offset after setting to HS400 mode */
  373. if (hs400)
  374. priv->needs_adjust_hs400 = true;
  375. return 0;
  376. }
  377. static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
  378. unsigned long tap)
  379. {
  380. /* Set sampling clock position */
  381. tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
  382. }
  383. static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
  384. {
  385. /* Get comparison of sampling data */
  386. return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
  387. }
  388. static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
  389. unsigned int taps)
  390. {
  391. unsigned long tap_cnt; /* counter of tuning success */
  392. unsigned long tap_start;/* start position of tuning success */
  393. unsigned long tap_end; /* end position of tuning success */
  394. unsigned long ntap; /* temporary counter of tuning success */
  395. unsigned long match_cnt;/* counter of matching data */
  396. unsigned long i;
  397. bool select = false;
  398. u32 reg;
  399. priv->needs_adjust_hs400 = false;
  400. /* Clear SCC_RVSREQ */
  401. tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
  402. /* Merge the results */
  403. for (i = 0; i < priv->tap_num * 2; i++) {
  404. if (!(taps & BIT(i))) {
  405. taps &= ~BIT(i % priv->tap_num);
  406. taps &= ~BIT((i % priv->tap_num) + priv->tap_num);
  407. }
  408. if (!(priv->smpcmp & BIT(i))) {
  409. priv->smpcmp &= ~BIT(i % priv->tap_num);
  410. priv->smpcmp &= ~BIT((i % priv->tap_num) + priv->tap_num);
  411. }
  412. }
  413. /*
  414. * Find the longest consecutive run of successful probes. If that
  415. * is more than RENESAS_SDHI_MAX_TAP probes long then use the
  416. * center index as the tap.
  417. */
  418. tap_cnt = 0;
  419. ntap = 0;
  420. tap_start = 0;
  421. tap_end = 0;
  422. for (i = 0; i < priv->tap_num * 2; i++) {
  423. if (taps & BIT(i))
  424. ntap++;
  425. else {
  426. if (ntap > tap_cnt) {
  427. tap_start = i - ntap;
  428. tap_end = i - 1;
  429. tap_cnt = ntap;
  430. }
  431. ntap = 0;
  432. }
  433. }
  434. if (ntap > tap_cnt) {
  435. tap_start = i - ntap;
  436. tap_end = i - 1;
  437. tap_cnt = ntap;
  438. }
  439. /*
  440. * If all of the TAP is OK, the sampling clock position is selected by
  441. * identifying the change point of data.
  442. */
  443. if (tap_cnt == priv->tap_num * 2) {
  444. match_cnt = 0;
  445. ntap = 0;
  446. tap_start = 0;
  447. tap_end = 0;
  448. for (i = 0; i < priv->tap_num * 2; i++) {
  449. if (priv->smpcmp & BIT(i))
  450. ntap++;
  451. else {
  452. if (ntap > match_cnt) {
  453. tap_start = i - ntap;
  454. tap_end = i - 1;
  455. match_cnt = ntap;
  456. }
  457. ntap = 0;
  458. }
  459. }
  460. if (ntap > match_cnt) {
  461. tap_start = i - ntap;
  462. tap_end = i - 1;
  463. match_cnt = ntap;
  464. }
  465. if (match_cnt)
  466. select = true;
  467. } else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
  468. select = true;
  469. if (select)
  470. priv->tap_set = ((tap_start + tap_end) / 2) % priv->tap_num;
  471. else
  472. return -EIO;
  473. /* Set SCC */
  474. tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
  475. /* Enable auto re-tuning */
  476. reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
  477. reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
  478. tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
  479. return 0;
  480. }
  481. int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
  482. {
  483. struct tmio_sd_priv *priv = dev_get_priv(dev);
  484. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  485. struct mmc *mmc = upriv->mmc;
  486. unsigned int tap_num;
  487. unsigned int taps = 0;
  488. int i, ret = 0;
  489. u32 caps;
  490. /* Only supported on Renesas RCar */
  491. if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
  492. return -EINVAL;
  493. /* clock tuning is not needed for upto 52MHz */
  494. if (!((mmc->selected_mode == MMC_HS_200) ||
  495. (mmc->selected_mode == MMC_HS_400) ||
  496. (mmc->selected_mode == UHS_SDR104) ||
  497. (mmc->selected_mode == UHS_SDR50)))
  498. return 0;
  499. tap_num = renesas_sdhi_init_tuning(priv);
  500. if (!tap_num)
  501. /* Tuning is not supported */
  502. goto out;
  503. priv->tap_num = tap_num;
  504. if (priv->tap_num * 2 >= sizeof(taps) * 8) {
  505. dev_err(dev,
  506. "Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
  507. goto out;
  508. }
  509. priv->smpcmp = 0;
  510. /* Issue CMD19 twice for each tap */
  511. for (i = 0; i < 2 * priv->tap_num; i++) {
  512. renesas_sdhi_prepare_tuning(priv, i % priv->tap_num);
  513. /* Force PIO for the tuning */
  514. caps = priv->caps;
  515. priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
  516. ret = mmc_send_tuning(mmc, opcode, NULL);
  517. priv->caps = caps;
  518. if (ret == 0)
  519. taps |= BIT(i);
  520. ret = renesas_sdhi_compare_scc_data(priv);
  521. if (ret == 0)
  522. priv->smpcmp |= BIT(i);
  523. mdelay(1);
  524. }
  525. ret = renesas_sdhi_select_tuning(priv, taps);
  526. out:
  527. if (ret < 0) {
  528. dev_warn(dev, "Tuning procedure failed\n");
  529. renesas_sdhi_reset_tuning(priv);
  530. }
  531. return ret;
  532. }
  533. #else
  534. static int renesas_sdhi_hs400(struct udevice *dev)
  535. {
  536. return 0;
  537. }
  538. #endif
  539. static int renesas_sdhi_set_ios(struct udevice *dev)
  540. {
  541. struct tmio_sd_priv *priv = dev_get_priv(dev);
  542. u32 tmp;
  543. int ret;
  544. /* Stop the clock before changing its rate to avoid a glitch signal */
  545. tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
  546. tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
  547. tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
  548. ret = renesas_sdhi_hs400(dev);
  549. if (ret)
  550. return ret;
  551. ret = tmio_sd_set_ios(dev);
  552. mdelay(10);
  553. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  554. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  555. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  556. struct mmc *mmc = mmc_get_mmc_dev(dev);
  557. if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
  558. (mmc->selected_mode != UHS_SDR104) &&
  559. (mmc->selected_mode != MMC_HS_200) &&
  560. (mmc->selected_mode != MMC_HS_400)) {
  561. renesas_sdhi_reset_tuning(priv);
  562. }
  563. #endif
  564. return ret;
  565. }
  566. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  567. static int renesas_sdhi_wait_dat0(struct udevice *dev, int state,
  568. int timeout_us)
  569. {
  570. int ret = -ETIMEDOUT;
  571. bool dat0_high;
  572. bool target_dat0_high = !!state;
  573. struct tmio_sd_priv *priv = dev_get_priv(dev);
  574. timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
  575. while (timeout_us--) {
  576. dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
  577. if (dat0_high == target_dat0_high) {
  578. ret = 0;
  579. break;
  580. }
  581. udelay(10);
  582. }
  583. return ret;
  584. }
  585. #endif
  586. #define RENESAS_SDHI_DMA_ALIGNMENT 128
  587. static int renesas_sdhi_addr_aligned_gen(uintptr_t ubuf,
  588. size_t len, size_t len_aligned)
  589. {
  590. /* Check if start is aligned */
  591. if (!IS_ALIGNED(ubuf, RENESAS_SDHI_DMA_ALIGNMENT)) {
  592. debug("Unaligned buffer address %lx\n", ubuf);
  593. return 0;
  594. }
  595. /* Check if length is aligned */
  596. if (len != len_aligned) {
  597. debug("Unaligned buffer length %zu\n", len);
  598. return 0;
  599. }
  600. #ifdef CONFIG_PHYS_64BIT
  601. /* Check if below 32bit boundary */
  602. if ((ubuf >> 32) || (ubuf + len_aligned) >> 32) {
  603. debug("Buffer above 32bit boundary %lx-%lx\n",
  604. ubuf, ubuf + len_aligned);
  605. return 0;
  606. }
  607. #endif
  608. /* Aligned */
  609. return 1;
  610. }
  611. static int renesas_sdhi_addr_aligned(struct bounce_buffer *state)
  612. {
  613. uintptr_t ubuf = (uintptr_t)state->user_buffer;
  614. return renesas_sdhi_addr_aligned_gen(ubuf, state->len,
  615. state->len_aligned);
  616. }
  617. static int renesas_sdhi_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  618. struct mmc_data *data)
  619. {
  620. struct bounce_buffer bbstate;
  621. unsigned int bbflags;
  622. bool bbok = false;
  623. size_t len;
  624. void *buf;
  625. int ret;
  626. if (data) {
  627. if (data->flags & MMC_DATA_READ) {
  628. buf = data->dest;
  629. bbflags = GEN_BB_WRITE;
  630. } else {
  631. buf = (void *)data->src;
  632. bbflags = GEN_BB_READ;
  633. }
  634. len = data->blocks * data->blocksize;
  635. ret = bounce_buffer_start_extalign(&bbstate, buf, len, bbflags,
  636. RENESAS_SDHI_DMA_ALIGNMENT,
  637. renesas_sdhi_addr_aligned);
  638. /*
  639. * If the amount of data to transfer is too large, we can get
  640. * -ENOMEM when starting the bounce buffer. If that happens,
  641. * fall back to PIO as it was before, otherwise use the BB.
  642. */
  643. if (!ret) {
  644. bbok = true;
  645. if (data->flags & MMC_DATA_READ)
  646. data->dest = bbstate.bounce_buffer;
  647. else
  648. data->src = bbstate.bounce_buffer;
  649. }
  650. }
  651. ret = tmio_sd_send_cmd(dev, cmd, data);
  652. if (data && bbok) {
  653. buf = bbstate.user_buffer;
  654. bounce_buffer_stop(&bbstate);
  655. if (data->flags & MMC_DATA_READ)
  656. data->dest = buf;
  657. else
  658. data->src = buf;
  659. }
  660. if (ret)
  661. return ret;
  662. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  663. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  664. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  665. struct tmio_sd_priv *priv = dev_get_priv(dev);
  666. renesas_sdhi_check_scc_error(dev);
  667. if (cmd->cmdidx == MMC_CMD_SEND_STATUS)
  668. renesas_sdhi_adjust_hs400_mode_enable(priv);
  669. #endif
  670. return 0;
  671. }
  672. int renesas_sdhi_get_b_max(struct udevice *dev, void *dst, lbaint_t blkcnt)
  673. {
  674. struct tmio_sd_priv *priv = dev_get_priv(dev);
  675. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  676. struct mmc *mmc = upriv->mmc;
  677. size_t len = blkcnt * mmc->read_bl_len;
  678. size_t len_align = roundup(len, RENESAS_SDHI_DMA_ALIGNMENT);
  679. if (renesas_sdhi_addr_aligned_gen((uintptr_t)dst, len, len_align)) {
  680. if (priv->quirks & TMIO_SD_CAP_16BIT)
  681. return U16_MAX;
  682. else
  683. return U32_MAX;
  684. } else {
  685. return (CONFIG_SYS_MALLOC_LEN / 4) / mmc->read_bl_len;
  686. }
  687. }
  688. static const struct dm_mmc_ops renesas_sdhi_ops = {
  689. .send_cmd = renesas_sdhi_send_cmd,
  690. .set_ios = renesas_sdhi_set_ios,
  691. .get_cd = tmio_sd_get_cd,
  692. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  693. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  694. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  695. .execute_tuning = renesas_sdhi_execute_tuning,
  696. #endif
  697. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  698. .wait_dat0 = renesas_sdhi_wait_dat0,
  699. #endif
  700. .get_b_max = renesas_sdhi_get_b_max,
  701. };
  702. #define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
  703. #define RENESAS_GEN3_QUIRKS \
  704. TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
  705. static const struct udevice_id renesas_sdhi_match[] = {
  706. { .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
  707. { .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
  708. { .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
  709. { .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
  710. { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
  711. { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
  712. { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
  713. { .compatible = "renesas,rcar-gen3-sdhi", .data = RENESAS_GEN3_QUIRKS },
  714. { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
  715. { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
  716. { .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
  717. { .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
  718. { /* sentinel */ }
  719. };
  720. static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
  721. {
  722. return clk_get_rate(&priv->clk);
  723. }
  724. static void renesas_sdhi_filter_caps(struct udevice *dev)
  725. {
  726. struct tmio_sd_priv *priv = dev_get_priv(dev);
  727. if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
  728. return;
  729. if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL)
  730. priv->idma_bus_width = TMIO_SD_DMA_MODE_BUS_WIDTH;
  731. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  732. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  733. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  734. struct tmio_sd_plat *plat = dev_get_plat(dev);
  735. /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */
  736. if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
  737. (rmobile_get_cpu_rev_integer() <= 1)) ||
  738. ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
  739. (rmobile_get_cpu_rev_integer() == 1) &&
  740. (rmobile_get_cpu_rev_fraction() < 2)))
  741. plat->cfg.host_caps &= ~MMC_MODE_HS400;
  742. /* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */
  743. if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
  744. (rmobile_get_cpu_rev_integer() >= 2)) ||
  745. ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
  746. (rmobile_get_cpu_rev_integer() == 1) &&
  747. (rmobile_get_cpu_rev_fraction() == 2)) ||
  748. (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965))
  749. priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7);
  750. /* H3 ES3.0 can use HS400 with manual adjustment */
  751. if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
  752. (rmobile_get_cpu_rev_integer() >= 3)) {
  753. priv->adjust_hs400_enable = true;
  754. priv->adjust_hs400_offset = 0;
  755. priv->adjust_hs400_calib_table =
  756. r8a7795_calib_table[!rmobile_is_gen3_mmc0(priv)];
  757. }
  758. /* M3W ES1.2 can use HS400 with manual adjustment */
  759. if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
  760. (rmobile_get_cpu_rev_integer() == 1) &&
  761. (rmobile_get_cpu_rev_fraction() == 2)) {
  762. priv->adjust_hs400_enable = true;
  763. priv->adjust_hs400_offset = 3;
  764. priv->adjust_hs400_calib_table =
  765. r8a7796_rev1_calib_table[!rmobile_is_gen3_mmc0(priv)];
  766. }
  767. /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */
  768. if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
  769. (rmobile_get_cpu_rev_integer() == 1) &&
  770. (rmobile_get_cpu_rev_fraction() > 2)) {
  771. priv->adjust_hs400_enable = true;
  772. priv->adjust_hs400_offset = 0;
  773. priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7);
  774. priv->adjust_hs400_calib_table =
  775. r8a7796_rev3_calib_table[!rmobile_is_gen3_mmc0(priv)];
  776. }
  777. /* M3N can use HS400 with manual adjustment */
  778. if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) {
  779. priv->adjust_hs400_enable = true;
  780. priv->adjust_hs400_offset = 3;
  781. priv->adjust_hs400_calib_table =
  782. r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)];
  783. }
  784. /* E3 can use HS400 with manual adjustment */
  785. if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) {
  786. priv->adjust_hs400_enable = true;
  787. priv->adjust_hs400_offset = 3;
  788. priv->adjust_hs400_calib_table =
  789. r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)];
  790. }
  791. /* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */
  792. if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
  793. (rmobile_get_cpu_rev_integer() <= 2)) ||
  794. ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
  795. (rmobile_get_cpu_rev_integer() == 1) &&
  796. (rmobile_get_cpu_rev_fraction() <= 2)))
  797. priv->nrtaps = 4;
  798. else
  799. priv->nrtaps = 8;
  800. #endif
  801. /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
  802. if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
  803. (rmobile_get_cpu_rev_integer() <= 1)) ||
  804. ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
  805. (rmobile_get_cpu_rev_integer() == 1) &&
  806. (rmobile_get_cpu_rev_fraction() == 0)))
  807. priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
  808. else
  809. priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
  810. }
  811. static int renesas_sdhi_probe(struct udevice *dev)
  812. {
  813. struct tmio_sd_priv *priv = dev_get_priv(dev);
  814. u32 quirks = dev_get_driver_data(dev);
  815. struct fdt_resource reg_res;
  816. DECLARE_GLOBAL_DATA_PTR;
  817. int ret;
  818. priv->clk_get_rate = renesas_sdhi_clk_get_rate;
  819. if (quirks == RENESAS_GEN2_QUIRKS) {
  820. ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
  821. "reg", 0, &reg_res);
  822. if (ret < 0) {
  823. dev_err(dev, "\"reg\" resource not found, ret=%i\n",
  824. ret);
  825. return ret;
  826. }
  827. if (fdt_resource_size(&reg_res) == 0x100)
  828. quirks |= TMIO_SD_CAP_16BIT;
  829. }
  830. ret = clk_get_by_index(dev, 0, &priv->clk);
  831. if (ret < 0) {
  832. dev_err(dev, "failed to get host clock\n");
  833. return ret;
  834. }
  835. /* set to max rate */
  836. ret = clk_set_rate(&priv->clk, 200000000);
  837. if (ret < 0) {
  838. dev_err(dev, "failed to set rate for host clock\n");
  839. clk_free(&priv->clk);
  840. return ret;
  841. }
  842. ret = clk_enable(&priv->clk);
  843. if (ret) {
  844. dev_err(dev, "failed to enable host clock\n");
  845. return ret;
  846. }
  847. priv->quirks = quirks;
  848. ret = tmio_sd_probe(dev, quirks);
  849. renesas_sdhi_filter_caps(dev);
  850. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  851. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  852. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  853. if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
  854. renesas_sdhi_reset_tuning(priv);
  855. #endif
  856. return ret;
  857. }
  858. U_BOOT_DRIVER(renesas_sdhi) = {
  859. .name = "renesas-sdhi",
  860. .id = UCLASS_MMC,
  861. .of_match = renesas_sdhi_match,
  862. .bind = tmio_sd_bind,
  863. .probe = renesas_sdhi_probe,
  864. .priv_auto = sizeof(struct tmio_sd_priv),
  865. .plat_auto = sizeof(struct tmio_sd_plat),
  866. .ops = &renesas_sdhi_ops,
  867. };