omap_hsmmc.c 51 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Texas Instruments, <www.ti.com>
  4. * Sukumar Ghorai <s-ghorai@ti.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation's version 2 of
  12. * the License.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #include <config.h>
  25. #include <common.h>
  26. #include <cpu_func.h>
  27. #include <log.h>
  28. #include <malloc.h>
  29. #include <memalign.h>
  30. #include <mmc.h>
  31. #include <part.h>
  32. #include <i2c.h>
  33. #if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
  34. #include <palmas.h>
  35. #endif
  36. #include <asm/cache.h>
  37. #include <asm/global_data.h>
  38. #include <asm/io.h>
  39. #include <asm/arch/mmc_host_def.h>
  40. #ifdef CONFIG_OMAP54XX
  41. #include <asm/arch/mux_dra7xx.h>
  42. #include <asm/arch/dra7xx_iodelay.h>
  43. #endif
  44. #if !defined(CONFIG_SOC_KEYSTONE)
  45. #include <asm/gpio.h>
  46. #include <asm/arch/sys_proto.h>
  47. #endif
  48. #ifdef CONFIG_MMC_OMAP36XX_PINS
  49. #include <asm/arch/mux.h>
  50. #endif
  51. #include <dm.h>
  52. #include <dm/devres.h>
  53. #include <linux/bitops.h>
  54. #include <linux/delay.h>
  55. #include <linux/err.h>
  56. #include <power/regulator.h>
  57. #include <thermal.h>
  58. DECLARE_GLOBAL_DATA_PTR;
  59. /* simplify defines to OMAP_HSMMC_USE_GPIO */
  60. #if (defined(CONFIG_OMAP_GPIO) && !defined(CONFIG_SPL_BUILD)) || \
  61. (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO))
  62. #define OMAP_HSMMC_USE_GPIO
  63. #else
  64. #undef OMAP_HSMMC_USE_GPIO
  65. #endif
  66. /* common definitions for all OMAPs */
  67. #define SYSCTL_SRC (1 << 25)
  68. #define SYSCTL_SRD (1 << 26)
  69. #ifdef CONFIG_IODELAY_RECALIBRATION
  70. struct omap_hsmmc_pinctrl_state {
  71. struct pad_conf_entry *padconf;
  72. int npads;
  73. struct iodelay_cfg_entry *iodelay;
  74. int niodelays;
  75. };
  76. #endif
  77. struct omap_hsmmc_data {
  78. struct hsmmc *base_addr;
  79. #if !CONFIG_IS_ENABLED(DM_MMC)
  80. struct mmc_config cfg;
  81. #endif
  82. uint bus_width;
  83. uint clock;
  84. ushort last_cmd;
  85. #ifdef OMAP_HSMMC_USE_GPIO
  86. #if CONFIG_IS_ENABLED(DM_MMC)
  87. struct gpio_desc cd_gpio; /* Change Detect GPIO */
  88. struct gpio_desc wp_gpio; /* Write Protect GPIO */
  89. #else
  90. int cd_gpio;
  91. int wp_gpio;
  92. #endif
  93. #endif
  94. #if CONFIG_IS_ENABLED(DM_MMC)
  95. enum bus_mode mode;
  96. #endif
  97. u8 controller_flags;
  98. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  99. struct omap_hsmmc_adma_desc *adma_desc_table;
  100. uint desc_slot;
  101. #endif
  102. const char *hw_rev;
  103. struct udevice *pbias_supply;
  104. uint signal_voltage;
  105. #ifdef CONFIG_IODELAY_RECALIBRATION
  106. struct omap_hsmmc_pinctrl_state *default_pinctrl_state;
  107. struct omap_hsmmc_pinctrl_state *hs_pinctrl_state;
  108. struct omap_hsmmc_pinctrl_state *hs200_1_8v_pinctrl_state;
  109. struct omap_hsmmc_pinctrl_state *ddr_1_8v_pinctrl_state;
  110. struct omap_hsmmc_pinctrl_state *sdr12_pinctrl_state;
  111. struct omap_hsmmc_pinctrl_state *sdr25_pinctrl_state;
  112. struct omap_hsmmc_pinctrl_state *ddr50_pinctrl_state;
  113. struct omap_hsmmc_pinctrl_state *sdr50_pinctrl_state;
  114. struct omap_hsmmc_pinctrl_state *sdr104_pinctrl_state;
  115. #endif
  116. };
  117. struct omap_mmc_of_data {
  118. u8 controller_flags;
  119. };
  120. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  121. struct omap_hsmmc_adma_desc {
  122. u8 attr;
  123. u8 reserved;
  124. u16 len;
  125. u32 addr;
  126. };
  127. #define ADMA_MAX_LEN 63488
  128. /* Decriptor table defines */
  129. #define ADMA_DESC_ATTR_VALID BIT(0)
  130. #define ADMA_DESC_ATTR_END BIT(1)
  131. #define ADMA_DESC_ATTR_INT BIT(2)
  132. #define ADMA_DESC_ATTR_ACT1 BIT(4)
  133. #define ADMA_DESC_ATTR_ACT2 BIT(5)
  134. #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2
  135. #define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
  136. #endif
  137. /* If we fail after 1 second wait, something is really bad */
  138. #define MAX_RETRY_MS 1000
  139. #define MMC_TIMEOUT_MS 20
  140. /* DMA transfers can take a long time if a lot a data is transferred.
  141. * The timeout must take in account the amount of data. Let's assume
  142. * that the time will never exceed 333 ms per MB (in other word we assume
  143. * that the bandwidth is always above 3MB/s).
  144. */
  145. #define DMA_TIMEOUT_PER_MB 333
  146. #define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(0)
  147. #define OMAP_HSMMC_NO_1_8_V BIT(1)
  148. #define OMAP_HSMMC_USE_ADMA BIT(2)
  149. #define OMAP_HSMMC_REQUIRE_IODELAY BIT(3)
  150. static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
  151. static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  152. unsigned int siz);
  153. static void omap_hsmmc_start_clock(struct hsmmc *mmc_base);
  154. static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base);
  155. static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit);
  156. static inline struct omap_hsmmc_data *omap_hsmmc_get_data(struct mmc *mmc)
  157. {
  158. #if CONFIG_IS_ENABLED(DM_MMC)
  159. return dev_get_priv(mmc->dev);
  160. #else
  161. return (struct omap_hsmmc_data *)mmc->priv;
  162. #endif
  163. }
  164. #if defined(CONFIG_OMAP34XX) || defined(CONFIG_IODELAY_RECALIBRATION)
  165. static inline struct mmc_config *omap_hsmmc_get_cfg(struct mmc *mmc)
  166. {
  167. #if CONFIG_IS_ENABLED(DM_MMC)
  168. struct omap_hsmmc_plat *plat = dev_get_plat(mmc->dev);
  169. return &plat->cfg;
  170. #else
  171. return &((struct omap_hsmmc_data *)mmc->priv)->cfg;
  172. #endif
  173. }
  174. #endif
  175. #if defined(OMAP_HSMMC_USE_GPIO) && !CONFIG_IS_ENABLED(DM_MMC)
  176. static int omap_mmc_setup_gpio_in(int gpio, const char *label)
  177. {
  178. int ret;
  179. #if !CONFIG_IS_ENABLED(DM_GPIO)
  180. if (!gpio_is_valid(gpio))
  181. return -1;
  182. #endif
  183. ret = gpio_request(gpio, label);
  184. if (ret)
  185. return ret;
  186. ret = gpio_direction_input(gpio);
  187. if (ret)
  188. return ret;
  189. return gpio;
  190. }
  191. #endif
  192. static unsigned char mmc_board_init(struct mmc *mmc)
  193. {
  194. #if defined(CONFIG_OMAP34XX)
  195. struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
  196. t2_t *t2_base = (t2_t *)T2_BASE;
  197. struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
  198. u32 pbias_lite;
  199. #ifdef CONFIG_MMC_OMAP36XX_PINS
  200. u32 wkup_ctrl = readl(OMAP34XX_CTRL_WKUP_CTRL);
  201. #endif
  202. pbias_lite = readl(&t2_base->pbias_lite);
  203. pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
  204. #ifdef CONFIG_TARGET_OMAP3_CAIRO
  205. /* for cairo board, we need to set up 1.8 Volt bias level on MMC1 */
  206. pbias_lite &= ~PBIASLITEVMODE0;
  207. #endif
  208. #ifdef CONFIG_TARGET_OMAP3_LOGIC
  209. /* For Logic PD board, 1.8V bias to go enable gpio127 for mmc_cd */
  210. pbias_lite &= ~PBIASLITEVMODE1;
  211. #endif
  212. #ifdef CONFIG_MMC_OMAP36XX_PINS
  213. if (get_cpu_family() == CPU_OMAP36XX) {
  214. /* Disable extended drain IO before changing PBIAS */
  215. wkup_ctrl &= ~OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ;
  216. writel(wkup_ctrl, OMAP34XX_CTRL_WKUP_CTRL);
  217. }
  218. #endif
  219. writel(pbias_lite, &t2_base->pbias_lite);
  220. writel(pbias_lite | PBIASLITEPWRDNZ1 |
  221. PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
  222. &t2_base->pbias_lite);
  223. #ifdef CONFIG_MMC_OMAP36XX_PINS
  224. if (get_cpu_family() == CPU_OMAP36XX)
  225. /* Enable extended drain IO after changing PBIAS */
  226. writel(wkup_ctrl |
  227. OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
  228. OMAP34XX_CTRL_WKUP_CTRL);
  229. #endif
  230. writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
  231. &t2_base->devconf0);
  232. writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
  233. &t2_base->devconf1);
  234. /* Change from default of 52MHz to 26MHz if necessary */
  235. if (!(cfg->host_caps & MMC_MODE_HS_52MHz))
  236. writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
  237. &t2_base->ctl_prog_io1);
  238. writel(readl(&prcm_base->fclken1_core) |
  239. EN_MMC1 | EN_MMC2 | EN_MMC3,
  240. &prcm_base->fclken1_core);
  241. writel(readl(&prcm_base->iclken1_core) |
  242. EN_MMC1 | EN_MMC2 | EN_MMC3,
  243. &prcm_base->iclken1_core);
  244. #endif
  245. #if (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) &&\
  246. !CONFIG_IS_ENABLED(DM_REGULATOR)
  247. /* PBIAS config needed for MMC1 only */
  248. if (mmc_get_blk_desc(mmc)->devnum == 0)
  249. vmmc_pbias_config(LDO_VOLT_3V3);
  250. #endif
  251. return 0;
  252. }
  253. void mmc_init_stream(struct hsmmc *mmc_base)
  254. {
  255. ulong start;
  256. writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);
  257. writel(MMC_CMD0, &mmc_base->cmd);
  258. start = get_timer(0);
  259. while (!(readl(&mmc_base->stat) & CC_MASK)) {
  260. if (get_timer(0) - start > MAX_RETRY_MS) {
  261. printf("%s: timedout waiting for cc!\n", __func__);
  262. return;
  263. }
  264. }
  265. writel(CC_MASK, &mmc_base->stat)
  266. ;
  267. writel(MMC_CMD0, &mmc_base->cmd)
  268. ;
  269. start = get_timer(0);
  270. while (!(readl(&mmc_base->stat) & CC_MASK)) {
  271. if (get_timer(0) - start > MAX_RETRY_MS) {
  272. printf("%s: timedout waiting for cc2!\n", __func__);
  273. return;
  274. }
  275. }
  276. writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
  277. }
  278. #if CONFIG_IS_ENABLED(DM_MMC)
  279. #ifdef CONFIG_IODELAY_RECALIBRATION
  280. static void omap_hsmmc_io_recalibrate(struct mmc *mmc)
  281. {
  282. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  283. struct omap_hsmmc_pinctrl_state *pinctrl_state;
  284. switch (priv->mode) {
  285. case MMC_HS_200:
  286. pinctrl_state = priv->hs200_1_8v_pinctrl_state;
  287. break;
  288. case UHS_SDR104:
  289. pinctrl_state = priv->sdr104_pinctrl_state;
  290. break;
  291. case UHS_SDR50:
  292. pinctrl_state = priv->sdr50_pinctrl_state;
  293. break;
  294. case UHS_DDR50:
  295. pinctrl_state = priv->ddr50_pinctrl_state;
  296. break;
  297. case UHS_SDR25:
  298. pinctrl_state = priv->sdr25_pinctrl_state;
  299. break;
  300. case UHS_SDR12:
  301. pinctrl_state = priv->sdr12_pinctrl_state;
  302. break;
  303. case SD_HS:
  304. case MMC_HS:
  305. case MMC_HS_52:
  306. pinctrl_state = priv->hs_pinctrl_state;
  307. break;
  308. case MMC_DDR_52:
  309. pinctrl_state = priv->ddr_1_8v_pinctrl_state;
  310. default:
  311. pinctrl_state = priv->default_pinctrl_state;
  312. break;
  313. }
  314. if (!pinctrl_state)
  315. pinctrl_state = priv->default_pinctrl_state;
  316. if (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY) {
  317. if (pinctrl_state->iodelay)
  318. late_recalibrate_iodelay(pinctrl_state->padconf,
  319. pinctrl_state->npads,
  320. pinctrl_state->iodelay,
  321. pinctrl_state->niodelays);
  322. else
  323. do_set_mux32((*ctrl)->control_padconf_core_base,
  324. pinctrl_state->padconf,
  325. pinctrl_state->npads);
  326. }
  327. }
  328. #endif
  329. static void omap_hsmmc_set_timing(struct mmc *mmc)
  330. {
  331. u32 val;
  332. struct hsmmc *mmc_base;
  333. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  334. mmc_base = priv->base_addr;
  335. omap_hsmmc_stop_clock(mmc_base);
  336. val = readl(&mmc_base->ac12);
  337. val &= ~AC12_UHSMC_MASK;
  338. priv->mode = mmc->selected_mode;
  339. if (mmc_is_mode_ddr(priv->mode))
  340. writel(readl(&mmc_base->con) | DDR, &mmc_base->con);
  341. else
  342. writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con);
  343. switch (priv->mode) {
  344. case MMC_HS_200:
  345. case UHS_SDR104:
  346. val |= AC12_UHSMC_SDR104;
  347. break;
  348. case UHS_SDR50:
  349. val |= AC12_UHSMC_SDR50;
  350. break;
  351. case MMC_DDR_52:
  352. case UHS_DDR50:
  353. val |= AC12_UHSMC_DDR50;
  354. break;
  355. case SD_HS:
  356. case MMC_HS_52:
  357. case UHS_SDR25:
  358. val |= AC12_UHSMC_SDR25;
  359. break;
  360. case MMC_LEGACY:
  361. case MMC_HS:
  362. case UHS_SDR12:
  363. val |= AC12_UHSMC_SDR12;
  364. break;
  365. default:
  366. val |= AC12_UHSMC_RES;
  367. break;
  368. }
  369. writel(val, &mmc_base->ac12);
  370. #ifdef CONFIG_IODELAY_RECALIBRATION
  371. omap_hsmmc_io_recalibrate(mmc);
  372. #endif
  373. omap_hsmmc_start_clock(mmc_base);
  374. }
  375. static void omap_hsmmc_conf_bus_power(struct mmc *mmc, uint signal_voltage)
  376. {
  377. struct hsmmc *mmc_base;
  378. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  379. u32 hctl, ac12;
  380. mmc_base = priv->base_addr;
  381. hctl = readl(&mmc_base->hctl) & ~SDVS_MASK;
  382. ac12 = readl(&mmc_base->ac12) & ~AC12_V1V8_SIGEN;
  383. switch (signal_voltage) {
  384. case MMC_SIGNAL_VOLTAGE_330:
  385. hctl |= SDVS_3V3;
  386. break;
  387. case MMC_SIGNAL_VOLTAGE_180:
  388. hctl |= SDVS_1V8;
  389. ac12 |= AC12_V1V8_SIGEN;
  390. break;
  391. }
  392. writel(hctl, &mmc_base->hctl);
  393. writel(ac12, &mmc_base->ac12);
  394. }
  395. static int omap_hsmmc_wait_dat0(struct udevice *dev, int state, int timeout_us)
  396. {
  397. int ret = -ETIMEDOUT;
  398. u32 con;
  399. bool dat0_high;
  400. bool target_dat0_high = !!state;
  401. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  402. struct hsmmc *mmc_base = priv->base_addr;
  403. con = readl(&mmc_base->con);
  404. writel(con | CON_CLKEXTFREE | CON_PADEN, &mmc_base->con);
  405. timeout_us = DIV_ROUND_UP(timeout_us, 10); /* check every 10 us. */
  406. while (timeout_us--) {
  407. dat0_high = !!(readl(&mmc_base->pstate) & PSTATE_DLEV_DAT0);
  408. if (dat0_high == target_dat0_high) {
  409. ret = 0;
  410. break;
  411. }
  412. udelay(10);
  413. }
  414. writel(con, &mmc_base->con);
  415. return ret;
  416. }
  417. #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
  418. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  419. static int omap_hsmmc_set_io_regulator(struct mmc *mmc, int mV)
  420. {
  421. int ret = 0;
  422. int uV = mV * 1000;
  423. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  424. if (!mmc->vqmmc_supply)
  425. return 0;
  426. /* Disable PBIAS */
  427. ret = regulator_set_enable_if_allowed(priv->pbias_supply, false);
  428. if (ret)
  429. return ret;
  430. /* Turn off IO voltage */
  431. ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, false);
  432. if (ret)
  433. return ret;
  434. /* Program a new IO voltage value */
  435. ret = regulator_set_value(mmc->vqmmc_supply, uV);
  436. if (ret)
  437. return ret;
  438. /* Turn on IO voltage */
  439. ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
  440. if (ret)
  441. return ret;
  442. /* Program PBIAS voltage*/
  443. ret = regulator_set_value(priv->pbias_supply, uV);
  444. if (ret && ret != -ENOSYS)
  445. return ret;
  446. /* Enable PBIAS */
  447. ret = regulator_set_enable_if_allowed(priv->pbias_supply, true);
  448. if (ret)
  449. return ret;
  450. return 0;
  451. }
  452. #endif
  453. static int omap_hsmmc_set_signal_voltage(struct mmc *mmc)
  454. {
  455. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  456. struct hsmmc *mmc_base = priv->base_addr;
  457. int mv = mmc_voltage_to_mv(mmc->signal_voltage);
  458. u32 capa_mask;
  459. __maybe_unused u8 palmas_ldo_volt;
  460. u32 val;
  461. if (mv < 0)
  462. return -EINVAL;
  463. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
  464. mv = 3300;
  465. capa_mask = VS33_3V3SUP;
  466. palmas_ldo_volt = LDO_VOLT_3V3;
  467. } else if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  468. capa_mask = VS18_1V8SUP;
  469. palmas_ldo_volt = LDO_VOLT_1V8;
  470. } else {
  471. return -EOPNOTSUPP;
  472. }
  473. val = readl(&mmc_base->capa);
  474. if (!(val & capa_mask))
  475. return -EOPNOTSUPP;
  476. priv->signal_voltage = mmc->signal_voltage;
  477. omap_hsmmc_conf_bus_power(mmc, mmc->signal_voltage);
  478. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  479. return omap_hsmmc_set_io_regulator(mmc, mv);
  480. #elif (defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)) && \
  481. defined(CONFIG_PALMAS_POWER)
  482. if (mmc_get_blk_desc(mmc)->devnum == 0)
  483. vmmc_pbias_config(palmas_ldo_volt);
  484. return 0;
  485. #else
  486. return 0;
  487. #endif
  488. }
  489. #endif
  490. static uint32_t omap_hsmmc_set_capabilities(struct mmc *mmc)
  491. {
  492. struct hsmmc *mmc_base;
  493. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  494. u32 val;
  495. mmc_base = priv->base_addr;
  496. val = readl(&mmc_base->capa);
  497. if (priv->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
  498. val |= (VS33_3V3SUP | VS18_1V8SUP);
  499. } else if (priv->controller_flags & OMAP_HSMMC_NO_1_8_V) {
  500. val |= VS33_3V3SUP;
  501. val &= ~VS18_1V8SUP;
  502. } else {
  503. val |= VS18_1V8SUP;
  504. val &= ~VS33_3V3SUP;
  505. }
  506. writel(val, &mmc_base->capa);
  507. return val;
  508. }
  509. #ifdef MMC_SUPPORTS_TUNING
  510. static void omap_hsmmc_disable_tuning(struct mmc *mmc)
  511. {
  512. struct hsmmc *mmc_base;
  513. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  514. u32 val;
  515. mmc_base = priv->base_addr;
  516. val = readl(&mmc_base->ac12);
  517. val &= ~(AC12_SCLK_SEL);
  518. writel(val, &mmc_base->ac12);
  519. val = readl(&mmc_base->dll);
  520. val &= ~(DLL_FORCE_VALUE | DLL_SWT);
  521. writel(val, &mmc_base->dll);
  522. }
  523. static void omap_hsmmc_set_dll(struct mmc *mmc, int count)
  524. {
  525. int i;
  526. struct hsmmc *mmc_base;
  527. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  528. u32 val;
  529. mmc_base = priv->base_addr;
  530. val = readl(&mmc_base->dll);
  531. val |= DLL_FORCE_VALUE;
  532. val &= ~(DLL_FORCE_SR_C_MASK << DLL_FORCE_SR_C_SHIFT);
  533. val |= (count << DLL_FORCE_SR_C_SHIFT);
  534. writel(val, &mmc_base->dll);
  535. val |= DLL_CALIB;
  536. writel(val, &mmc_base->dll);
  537. for (i = 0; i < 1000; i++) {
  538. if (readl(&mmc_base->dll) & DLL_CALIB)
  539. break;
  540. }
  541. val &= ~DLL_CALIB;
  542. writel(val, &mmc_base->dll);
  543. }
  544. static int omap_hsmmc_execute_tuning(struct udevice *dev, uint opcode)
  545. {
  546. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  547. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  548. struct mmc *mmc = upriv->mmc;
  549. struct hsmmc *mmc_base;
  550. u32 val;
  551. u8 cur_match, prev_match = 0;
  552. int ret;
  553. u32 phase_delay = 0;
  554. u32 start_window = 0, max_window = 0;
  555. u32 length = 0, max_len = 0;
  556. bool single_point_failure = false;
  557. struct udevice *thermal_dev;
  558. int temperature;
  559. int i;
  560. mmc_base = priv->base_addr;
  561. val = readl(&mmc_base->capa2);
  562. /* clock tuning is not needed for upto 52MHz */
  563. if (!((mmc->selected_mode == MMC_HS_200) ||
  564. (mmc->selected_mode == UHS_SDR104) ||
  565. ((mmc->selected_mode == UHS_SDR50) && (val & CAPA2_TSDR50))))
  566. return 0;
  567. ret = uclass_first_device(UCLASS_THERMAL, &thermal_dev);
  568. if (ret) {
  569. printf("Couldn't get thermal device for tuning\n");
  570. return ret;
  571. }
  572. ret = thermal_get_temp(thermal_dev, &temperature);
  573. if (ret) {
  574. printf("Couldn't get temperature for tuning\n");
  575. return ret;
  576. }
  577. val = readl(&mmc_base->dll);
  578. val |= DLL_SWT;
  579. writel(val, &mmc_base->dll);
  580. /*
  581. * Stage 1: Search for a maximum pass window ignoring any
  582. * any single point failures. If the tuning value ends up
  583. * near it, move away from it in stage 2 below
  584. */
  585. while (phase_delay <= MAX_PHASE_DELAY) {
  586. omap_hsmmc_set_dll(mmc, phase_delay);
  587. cur_match = !mmc_send_tuning(mmc, opcode, NULL);
  588. if (cur_match) {
  589. if (prev_match) {
  590. length++;
  591. } else if (single_point_failure) {
  592. /* ignore single point failure */
  593. length++;
  594. single_point_failure = false;
  595. } else {
  596. start_window = phase_delay;
  597. length = 1;
  598. }
  599. } else {
  600. single_point_failure = prev_match;
  601. }
  602. if (length > max_len) {
  603. max_window = start_window;
  604. max_len = length;
  605. }
  606. prev_match = cur_match;
  607. phase_delay += 4;
  608. }
  609. if (!max_len) {
  610. ret = -EIO;
  611. goto tuning_error;
  612. }
  613. val = readl(&mmc_base->ac12);
  614. if (!(val & AC12_SCLK_SEL)) {
  615. ret = -EIO;
  616. goto tuning_error;
  617. }
  618. /*
  619. * Assign tuning value as a ratio of maximum pass window based
  620. * on temperature
  621. */
  622. if (temperature < -20000)
  623. phase_delay = min(max_window + 4 * max_len - 24,
  624. max_window +
  625. DIV_ROUND_UP(13 * max_len, 16) * 4);
  626. else if (temperature < 20000)
  627. phase_delay = max_window + DIV_ROUND_UP(9 * max_len, 16) * 4;
  628. else if (temperature < 40000)
  629. phase_delay = max_window + DIV_ROUND_UP(8 * max_len, 16) * 4;
  630. else if (temperature < 70000)
  631. phase_delay = max_window + DIV_ROUND_UP(7 * max_len, 16) * 4;
  632. else if (temperature < 90000)
  633. phase_delay = max_window + DIV_ROUND_UP(5 * max_len, 16) * 4;
  634. else if (temperature < 120000)
  635. phase_delay = max_window + DIV_ROUND_UP(4 * max_len, 16) * 4;
  636. else
  637. phase_delay = max_window + DIV_ROUND_UP(3 * max_len, 16) * 4;
  638. /*
  639. * Stage 2: Search for a single point failure near the chosen tuning
  640. * value in two steps. First in the +3 to +10 range and then in the
  641. * +2 to -10 range. If found, move away from it in the appropriate
  642. * direction by the appropriate amount depending on the temperature.
  643. */
  644. for (i = 3; i <= 10; i++) {
  645. omap_hsmmc_set_dll(mmc, phase_delay + i);
  646. if (mmc_send_tuning(mmc, opcode, NULL)) {
  647. if (temperature < 10000)
  648. phase_delay += i + 6;
  649. else if (temperature < 20000)
  650. phase_delay += i - 12;
  651. else if (temperature < 70000)
  652. phase_delay += i - 8;
  653. else if (temperature < 90000)
  654. phase_delay += i - 6;
  655. else
  656. phase_delay += i - 6;
  657. goto single_failure_found;
  658. }
  659. }
  660. for (i = 2; i >= -10; i--) {
  661. omap_hsmmc_set_dll(mmc, phase_delay + i);
  662. if (mmc_send_tuning(mmc, opcode, NULL)) {
  663. if (temperature < 10000)
  664. phase_delay += i + 12;
  665. else if (temperature < 20000)
  666. phase_delay += i + 8;
  667. else if (temperature < 70000)
  668. phase_delay += i + 8;
  669. else if (temperature < 90000)
  670. phase_delay += i + 10;
  671. else
  672. phase_delay += i + 12;
  673. goto single_failure_found;
  674. }
  675. }
  676. single_failure_found:
  677. omap_hsmmc_set_dll(mmc, phase_delay);
  678. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  679. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  680. return 0;
  681. tuning_error:
  682. omap_hsmmc_disable_tuning(mmc);
  683. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  684. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  685. return ret;
  686. }
  687. #endif
  688. #endif
  689. static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd)
  690. {
  691. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  692. struct hsmmc *mmc_base = priv->base_addr;
  693. u32 irq_mask = INT_EN_MASK;
  694. /*
  695. * TODO: Errata i802 indicates only DCRC interrupts can occur during
  696. * tuning procedure and DCRC should be disabled. But see occurences
  697. * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These
  698. * interrupts occur along with BRR, so the data is actually in the
  699. * buffer. It has to be debugged why these interrutps occur
  700. */
  701. if (cmd && mmc_is_tuning_cmd(cmd->cmdidx))
  702. irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC);
  703. writel(irq_mask, &mmc_base->ie);
  704. }
  705. static int omap_hsmmc_init_setup(struct mmc *mmc)
  706. {
  707. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  708. struct hsmmc *mmc_base;
  709. unsigned int reg_val;
  710. unsigned int dsor;
  711. ulong start;
  712. mmc_base = priv->base_addr;
  713. mmc_board_init(mmc);
  714. writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
  715. &mmc_base->sysconfig);
  716. start = get_timer(0);
  717. while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
  718. if (get_timer(0) - start > MAX_RETRY_MS) {
  719. printf("%s: timedout waiting for cc2!\n", __func__);
  720. return -ETIMEDOUT;
  721. }
  722. }
  723. writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
  724. start = get_timer(0);
  725. while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
  726. if (get_timer(0) - start > MAX_RETRY_MS) {
  727. printf("%s: timedout waiting for softresetall!\n",
  728. __func__);
  729. return -ETIMEDOUT;
  730. }
  731. }
  732. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  733. reg_val = readl(&mmc_base->hl_hwinfo);
  734. if (reg_val & MADMA_EN)
  735. priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
  736. #endif
  737. #if CONFIG_IS_ENABLED(DM_MMC)
  738. reg_val = omap_hsmmc_set_capabilities(mmc);
  739. omap_hsmmc_conf_bus_power(mmc, (reg_val & VS33_3V3SUP) ?
  740. MMC_SIGNAL_VOLTAGE_330 : MMC_SIGNAL_VOLTAGE_180);
  741. #else
  742. writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V3, &mmc_base->hctl);
  743. writel(readl(&mmc_base->capa) | VS33_3V3SUP | VS18_1V8SUP,
  744. &mmc_base->capa);
  745. #endif
  746. reg_val = readl(&mmc_base->con) & RESERVED_MASK;
  747. writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
  748. MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
  749. HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);
  750. dsor = 240;
  751. mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
  752. (ICE_STOP | DTO_15THDTO));
  753. mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
  754. (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
  755. start = get_timer(0);
  756. while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
  757. if (get_timer(0) - start > MAX_RETRY_MS) {
  758. printf("%s: timedout waiting for ics!\n", __func__);
  759. return -ETIMEDOUT;
  760. }
  761. }
  762. writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
  763. writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);
  764. mmc_enable_irq(mmc, NULL);
  765. #if !CONFIG_IS_ENABLED(DM_MMC)
  766. mmc_init_stream(mmc_base);
  767. #endif
  768. return 0;
  769. }
  770. /*
  771. * MMC controller internal finite state machine reset
  772. *
  773. * Used to reset command or data internal state machines, using respectively
  774. * SRC or SRD bit of SYSCTL register
  775. */
  776. static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
  777. {
  778. ulong start;
  779. mmc_reg_out(&mmc_base->sysctl, bit, bit);
  780. /*
  781. * CMD(DAT) lines reset procedures are slightly different
  782. * for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).
  783. * According to OMAP3 TRM:
  784. * Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until it
  785. * returns to 0x0.
  786. * According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
  787. * procedure steps must be as follows:
  788. * 1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
  789. * MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
  790. * 2. Poll the SRC(SRD) bit until it is set to 0x1.
  791. * 3. Wait until the SRC (SRD) bit returns to 0x0
  792. * (reset procedure is completed).
  793. */
  794. #if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
  795. defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
  796. if (!(readl(&mmc_base->sysctl) & bit)) {
  797. start = get_timer(0);
  798. while (!(readl(&mmc_base->sysctl) & bit)) {
  799. if (get_timer(0) - start > MMC_TIMEOUT_MS)
  800. return;
  801. }
  802. }
  803. #endif
  804. start = get_timer(0);
  805. while ((readl(&mmc_base->sysctl) & bit) != 0) {
  806. if (get_timer(0) - start > MAX_RETRY_MS) {
  807. printf("%s: timedout waiting for sysctl %x to clear\n",
  808. __func__, bit);
  809. return;
  810. }
  811. }
  812. }
  813. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  814. static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
  815. {
  816. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  817. struct omap_hsmmc_adma_desc *desc;
  818. u8 attr;
  819. desc = &priv->adma_desc_table[priv->desc_slot];
  820. attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
  821. if (!end)
  822. priv->desc_slot++;
  823. else
  824. attr |= ADMA_DESC_ATTR_END;
  825. desc->len = len;
  826. desc->addr = (u32)buf;
  827. desc->reserved = 0;
  828. desc->attr = attr;
  829. }
  830. static void omap_hsmmc_prepare_adma_table(struct mmc *mmc,
  831. struct mmc_data *data)
  832. {
  833. uint total_len = data->blocksize * data->blocks;
  834. uint desc_count = DIV_ROUND_UP(total_len, ADMA_MAX_LEN);
  835. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  836. int i = desc_count;
  837. char *buf;
  838. priv->desc_slot = 0;
  839. priv->adma_desc_table = (struct omap_hsmmc_adma_desc *)
  840. memalign(ARCH_DMA_MINALIGN, desc_count *
  841. sizeof(struct omap_hsmmc_adma_desc));
  842. if (data->flags & MMC_DATA_READ)
  843. buf = data->dest;
  844. else
  845. buf = (char *)data->src;
  846. while (--i) {
  847. omap_hsmmc_adma_desc(mmc, buf, ADMA_MAX_LEN, false);
  848. buf += ADMA_MAX_LEN;
  849. total_len -= ADMA_MAX_LEN;
  850. }
  851. omap_hsmmc_adma_desc(mmc, buf, total_len, true);
  852. flush_dcache_range((long)priv->adma_desc_table,
  853. (long)priv->adma_desc_table +
  854. ROUND(desc_count *
  855. sizeof(struct omap_hsmmc_adma_desc),
  856. ARCH_DMA_MINALIGN));
  857. }
  858. static void omap_hsmmc_prepare_data(struct mmc *mmc, struct mmc_data *data)
  859. {
  860. struct hsmmc *mmc_base;
  861. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  862. u32 val;
  863. char *buf;
  864. mmc_base = priv->base_addr;
  865. omap_hsmmc_prepare_adma_table(mmc, data);
  866. if (data->flags & MMC_DATA_READ)
  867. buf = data->dest;
  868. else
  869. buf = (char *)data->src;
  870. val = readl(&mmc_base->hctl);
  871. val |= DMA_SELECT;
  872. writel(val, &mmc_base->hctl);
  873. val = readl(&mmc_base->con);
  874. val |= DMA_MASTER;
  875. writel(val, &mmc_base->con);
  876. writel((u32)priv->adma_desc_table, &mmc_base->admasal);
  877. flush_dcache_range((u32)buf,
  878. (u32)buf +
  879. ROUND(data->blocksize * data->blocks,
  880. ARCH_DMA_MINALIGN));
  881. }
  882. static void omap_hsmmc_dma_cleanup(struct mmc *mmc)
  883. {
  884. struct hsmmc *mmc_base;
  885. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  886. u32 val;
  887. mmc_base = priv->base_addr;
  888. val = readl(&mmc_base->con);
  889. val &= ~DMA_MASTER;
  890. writel(val, &mmc_base->con);
  891. val = readl(&mmc_base->hctl);
  892. val &= ~DMA_SELECT;
  893. writel(val, &mmc_base->hctl);
  894. kfree(priv->adma_desc_table);
  895. }
  896. #else
  897. #define omap_hsmmc_adma_desc
  898. #define omap_hsmmc_prepare_adma_table
  899. #define omap_hsmmc_prepare_data
  900. #define omap_hsmmc_dma_cleanup
  901. #endif
  902. #if !CONFIG_IS_ENABLED(DM_MMC)
  903. static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  904. struct mmc_data *data)
  905. {
  906. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  907. #else
  908. static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  909. struct mmc_data *data)
  910. {
  911. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  912. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  913. struct mmc *mmc = upriv->mmc;
  914. #endif
  915. struct hsmmc *mmc_base;
  916. unsigned int flags, mmc_stat;
  917. ulong start;
  918. priv->last_cmd = cmd->cmdidx;
  919. mmc_base = priv->base_addr;
  920. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  921. return 0;
  922. start = get_timer(0);
  923. while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
  924. if (get_timer(0) - start > MAX_RETRY_MS) {
  925. printf("%s: timedout waiting on cmd inhibit to clear\n",
  926. __func__);
  927. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  928. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  929. return -ETIMEDOUT;
  930. }
  931. }
  932. writel(0xFFFFFFFF, &mmc_base->stat);
  933. if (readl(&mmc_base->stat)) {
  934. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  935. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  936. }
  937. /*
  938. * CMDREG
  939. * CMDIDX[13:8] : Command index
  940. * DATAPRNT[5] : Data Present Select
  941. * ENCMDIDX[4] : Command Index Check Enable
  942. * ENCMDCRC[3] : Command CRC Check Enable
  943. * RSPTYP[1:0]
  944. * 00 = No Response
  945. * 01 = Length 136
  946. * 10 = Length 48
  947. * 11 = Length 48 Check busy after response
  948. */
  949. /* Delay added before checking the status of frq change
  950. * retry not supported by mmc.c(core file)
  951. */
  952. if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
  953. udelay(50000); /* wait 50 ms */
  954. if (!(cmd->resp_type & MMC_RSP_PRESENT))
  955. flags = 0;
  956. else if (cmd->resp_type & MMC_RSP_136)
  957. flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
  958. else if (cmd->resp_type & MMC_RSP_BUSY)
  959. flags = RSP_TYPE_LGHT48B;
  960. else
  961. flags = RSP_TYPE_LGHT48;
  962. /* enable default flags */
  963. flags = flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
  964. MSBS_SGLEBLK);
  965. flags &= ~(ACEN_ENABLE | BCE_ENABLE | DE_ENABLE);
  966. if (cmd->resp_type & MMC_RSP_CRC)
  967. flags |= CCCE_CHECK;
  968. if (cmd->resp_type & MMC_RSP_OPCODE)
  969. flags |= CICE_CHECK;
  970. if (data) {
  971. if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
  972. (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
  973. flags |= (MSBS_MULTIBLK | BCE_ENABLE | ACEN_ENABLE);
  974. data->blocksize = 512;
  975. writel(data->blocksize | (data->blocks << 16),
  976. &mmc_base->blk);
  977. } else
  978. writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);
  979. if (data->flags & MMC_DATA_READ)
  980. flags |= (DP_DATA | DDIR_READ);
  981. else
  982. flags |= (DP_DATA | DDIR_WRITE);
  983. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  984. if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
  985. !mmc_is_tuning_cmd(cmd->cmdidx)) {
  986. omap_hsmmc_prepare_data(mmc, data);
  987. flags |= DE_ENABLE;
  988. }
  989. #endif
  990. }
  991. mmc_enable_irq(mmc, cmd);
  992. writel(cmd->cmdarg, &mmc_base->arg);
  993. udelay(20); /* To fix "No status update" error on eMMC */
  994. writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);
  995. start = get_timer(0);
  996. do {
  997. mmc_stat = readl(&mmc_base->stat);
  998. if (get_timer(start) > MAX_RETRY_MS) {
  999. printf("%s : timeout: No status update\n", __func__);
  1000. return -ETIMEDOUT;
  1001. }
  1002. } while (!mmc_stat);
  1003. if ((mmc_stat & IE_CTO) != 0) {
  1004. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
  1005. return -ETIMEDOUT;
  1006. } else if ((mmc_stat & ERRI_MASK) != 0)
  1007. return -1;
  1008. if (mmc_stat & CC_MASK) {
  1009. writel(CC_MASK, &mmc_base->stat);
  1010. if (cmd->resp_type & MMC_RSP_PRESENT) {
  1011. if (cmd->resp_type & MMC_RSP_136) {
  1012. /* response type 2 */
  1013. cmd->response[3] = readl(&mmc_base->rsp10);
  1014. cmd->response[2] = readl(&mmc_base->rsp32);
  1015. cmd->response[1] = readl(&mmc_base->rsp54);
  1016. cmd->response[0] = readl(&mmc_base->rsp76);
  1017. } else
  1018. /* response types 1, 1b, 3, 4, 5, 6 */
  1019. cmd->response[0] = readl(&mmc_base->rsp10);
  1020. }
  1021. }
  1022. #ifdef CONFIG_MMC_OMAP_HS_ADMA
  1023. if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
  1024. !mmc_is_tuning_cmd(cmd->cmdidx)) {
  1025. u32 sz_mb, timeout;
  1026. if (mmc_stat & IE_ADMAE) {
  1027. omap_hsmmc_dma_cleanup(mmc);
  1028. return -EIO;
  1029. }
  1030. sz_mb = DIV_ROUND_UP(data->blocksize * data->blocks, 1 << 20);
  1031. timeout = sz_mb * DMA_TIMEOUT_PER_MB;
  1032. if (timeout < MAX_RETRY_MS)
  1033. timeout = MAX_RETRY_MS;
  1034. start = get_timer(0);
  1035. do {
  1036. mmc_stat = readl(&mmc_base->stat);
  1037. if (mmc_stat & TC_MASK) {
  1038. writel(readl(&mmc_base->stat) | TC_MASK,
  1039. &mmc_base->stat);
  1040. break;
  1041. }
  1042. if (get_timer(start) > timeout) {
  1043. printf("%s : DMA timeout: No status update\n",
  1044. __func__);
  1045. return -ETIMEDOUT;
  1046. }
  1047. } while (1);
  1048. omap_hsmmc_dma_cleanup(mmc);
  1049. return 0;
  1050. }
  1051. #endif
  1052. if (data && (data->flags & MMC_DATA_READ)) {
  1053. mmc_read_data(mmc_base, data->dest,
  1054. data->blocksize * data->blocks);
  1055. } else if (data && (data->flags & MMC_DATA_WRITE)) {
  1056. mmc_write_data(mmc_base, data->src,
  1057. data->blocksize * data->blocks);
  1058. }
  1059. return 0;
  1060. }
  1061. static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
  1062. {
  1063. unsigned int *output_buf = (unsigned int *)buf;
  1064. unsigned int mmc_stat;
  1065. unsigned int count;
  1066. /*
  1067. * Start Polled Read
  1068. */
  1069. count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
  1070. count /= 4;
  1071. while (size) {
  1072. ulong start = get_timer(0);
  1073. do {
  1074. mmc_stat = readl(&mmc_base->stat);
  1075. if (get_timer(0) - start > MAX_RETRY_MS) {
  1076. printf("%s: timedout waiting for status!\n",
  1077. __func__);
  1078. return -ETIMEDOUT;
  1079. }
  1080. } while (mmc_stat == 0);
  1081. if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
  1082. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  1083. if ((mmc_stat & ERRI_MASK) != 0)
  1084. return 1;
  1085. if (mmc_stat & BRR_MASK) {
  1086. unsigned int k;
  1087. writel(readl(&mmc_base->stat) | BRR_MASK,
  1088. &mmc_base->stat);
  1089. for (k = 0; k < count; k++) {
  1090. *output_buf = readl(&mmc_base->data);
  1091. output_buf++;
  1092. }
  1093. size -= (count*4);
  1094. }
  1095. if (mmc_stat & BWR_MASK)
  1096. writel(readl(&mmc_base->stat) | BWR_MASK,
  1097. &mmc_base->stat);
  1098. if (mmc_stat & TC_MASK) {
  1099. writel(readl(&mmc_base->stat) | TC_MASK,
  1100. &mmc_base->stat);
  1101. break;
  1102. }
  1103. }
  1104. return 0;
  1105. }
  1106. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1107. static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  1108. unsigned int size)
  1109. {
  1110. unsigned int *input_buf = (unsigned int *)buf;
  1111. unsigned int mmc_stat;
  1112. unsigned int count;
  1113. /*
  1114. * Start Polled Write
  1115. */
  1116. count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
  1117. count /= 4;
  1118. while (size) {
  1119. ulong start = get_timer(0);
  1120. do {
  1121. mmc_stat = readl(&mmc_base->stat);
  1122. if (get_timer(0) - start > MAX_RETRY_MS) {
  1123. printf("%s: timedout waiting for status!\n",
  1124. __func__);
  1125. return -ETIMEDOUT;
  1126. }
  1127. } while (mmc_stat == 0);
  1128. if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
  1129. mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
  1130. if ((mmc_stat & ERRI_MASK) != 0)
  1131. return 1;
  1132. if (mmc_stat & BWR_MASK) {
  1133. unsigned int k;
  1134. writel(readl(&mmc_base->stat) | BWR_MASK,
  1135. &mmc_base->stat);
  1136. for (k = 0; k < count; k++) {
  1137. writel(*input_buf, &mmc_base->data);
  1138. input_buf++;
  1139. }
  1140. size -= (count*4);
  1141. }
  1142. if (mmc_stat & BRR_MASK)
  1143. writel(readl(&mmc_base->stat) | BRR_MASK,
  1144. &mmc_base->stat);
  1145. if (mmc_stat & TC_MASK) {
  1146. writel(readl(&mmc_base->stat) | TC_MASK,
  1147. &mmc_base->stat);
  1148. break;
  1149. }
  1150. }
  1151. return 0;
  1152. }
  1153. #else
  1154. static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
  1155. unsigned int size)
  1156. {
  1157. return -ENOTSUPP;
  1158. }
  1159. #endif
  1160. static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
  1161. {
  1162. writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
  1163. }
  1164. static void omap_hsmmc_start_clock(struct hsmmc *mmc_base)
  1165. {
  1166. writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
  1167. }
  1168. static void omap_hsmmc_set_clock(struct mmc *mmc)
  1169. {
  1170. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1171. struct hsmmc *mmc_base;
  1172. unsigned int dsor = 0;
  1173. ulong start;
  1174. mmc_base = priv->base_addr;
  1175. omap_hsmmc_stop_clock(mmc_base);
  1176. /* TODO: Is setting DTO required here? */
  1177. mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK),
  1178. (ICE_STOP | DTO_15THDTO));
  1179. if (mmc->clock != 0) {
  1180. dsor = DIV_ROUND_UP(MMC_CLOCK_REFERENCE * 1000000, mmc->clock);
  1181. if (dsor > CLKD_MAX)
  1182. dsor = CLKD_MAX;
  1183. } else {
  1184. dsor = CLKD_MAX;
  1185. }
  1186. mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
  1187. (dsor << CLKD_OFFSET) | ICE_OSCILLATE);
  1188. start = get_timer(0);
  1189. while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
  1190. if (get_timer(0) - start > MAX_RETRY_MS) {
  1191. printf("%s: timedout waiting for ics!\n", __func__);
  1192. return;
  1193. }
  1194. }
  1195. priv->clock = MMC_CLOCK_REFERENCE * 1000000 / dsor;
  1196. mmc->clock = priv->clock;
  1197. omap_hsmmc_start_clock(mmc_base);
  1198. }
  1199. static void omap_hsmmc_set_bus_width(struct mmc *mmc)
  1200. {
  1201. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1202. struct hsmmc *mmc_base;
  1203. mmc_base = priv->base_addr;
  1204. /* configue bus width */
  1205. switch (mmc->bus_width) {
  1206. case 8:
  1207. writel(readl(&mmc_base->con) | DTW_8_BITMODE,
  1208. &mmc_base->con);
  1209. break;
  1210. case 4:
  1211. writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
  1212. &mmc_base->con);
  1213. writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
  1214. &mmc_base->hctl);
  1215. break;
  1216. case 1:
  1217. default:
  1218. writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
  1219. &mmc_base->con);
  1220. writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
  1221. &mmc_base->hctl);
  1222. break;
  1223. }
  1224. priv->bus_width = mmc->bus_width;
  1225. }
  1226. #if !CONFIG_IS_ENABLED(DM_MMC)
  1227. static int omap_hsmmc_set_ios(struct mmc *mmc)
  1228. {
  1229. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1230. #else
  1231. static int omap_hsmmc_set_ios(struct udevice *dev)
  1232. {
  1233. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  1234. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  1235. struct mmc *mmc = upriv->mmc;
  1236. #endif
  1237. struct hsmmc *mmc_base = priv->base_addr;
  1238. int ret = 0;
  1239. if (priv->bus_width != mmc->bus_width)
  1240. omap_hsmmc_set_bus_width(mmc);
  1241. if (priv->clock != mmc->clock)
  1242. omap_hsmmc_set_clock(mmc);
  1243. if (mmc->clk_disable)
  1244. omap_hsmmc_stop_clock(mmc_base);
  1245. else
  1246. omap_hsmmc_start_clock(mmc_base);
  1247. #if CONFIG_IS_ENABLED(DM_MMC)
  1248. if (priv->mode != mmc->selected_mode)
  1249. omap_hsmmc_set_timing(mmc);
  1250. #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
  1251. if (priv->signal_voltage != mmc->signal_voltage)
  1252. ret = omap_hsmmc_set_signal_voltage(mmc);
  1253. #endif
  1254. #endif
  1255. return ret;
  1256. }
  1257. #ifdef OMAP_HSMMC_USE_GPIO
  1258. #if CONFIG_IS_ENABLED(DM_MMC)
  1259. static int omap_hsmmc_getcd(struct udevice *dev)
  1260. {
  1261. int value = -1;
  1262. #if CONFIG_IS_ENABLED(DM_GPIO)
  1263. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  1264. value = dm_gpio_get_value(&priv->cd_gpio);
  1265. #endif
  1266. /* if no CD return as 1 */
  1267. if (value < 0)
  1268. return 1;
  1269. return value;
  1270. }
  1271. static int omap_hsmmc_getwp(struct udevice *dev)
  1272. {
  1273. int value = 0;
  1274. #if CONFIG_IS_ENABLED(DM_GPIO)
  1275. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  1276. value = dm_gpio_get_value(&priv->wp_gpio);
  1277. #endif
  1278. /* if no WP return as 0 */
  1279. if (value < 0)
  1280. return 0;
  1281. return value;
  1282. }
  1283. #else
  1284. static int omap_hsmmc_getcd(struct mmc *mmc)
  1285. {
  1286. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1287. int cd_gpio;
  1288. /* if no CD return as 1 */
  1289. cd_gpio = priv->cd_gpio;
  1290. if (cd_gpio < 0)
  1291. return 1;
  1292. /* NOTE: assumes card detect signal is active-low */
  1293. return !gpio_get_value(cd_gpio);
  1294. }
  1295. static int omap_hsmmc_getwp(struct mmc *mmc)
  1296. {
  1297. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1298. int wp_gpio;
  1299. /* if no WP return as 0 */
  1300. wp_gpio = priv->wp_gpio;
  1301. if (wp_gpio < 0)
  1302. return 0;
  1303. /* NOTE: assumes write protect signal is active-high */
  1304. return gpio_get_value(wp_gpio);
  1305. }
  1306. #endif
  1307. #endif
  1308. #if CONFIG_IS_ENABLED(DM_MMC)
  1309. static const struct dm_mmc_ops omap_hsmmc_ops = {
  1310. .send_cmd = omap_hsmmc_send_cmd,
  1311. .set_ios = omap_hsmmc_set_ios,
  1312. #ifdef OMAP_HSMMC_USE_GPIO
  1313. .get_cd = omap_hsmmc_getcd,
  1314. .get_wp = omap_hsmmc_getwp,
  1315. #endif
  1316. #ifdef MMC_SUPPORTS_TUNING
  1317. .execute_tuning = omap_hsmmc_execute_tuning,
  1318. #endif
  1319. .wait_dat0 = omap_hsmmc_wait_dat0,
  1320. };
  1321. #else
  1322. static const struct mmc_ops omap_hsmmc_ops = {
  1323. .send_cmd = omap_hsmmc_send_cmd,
  1324. .set_ios = omap_hsmmc_set_ios,
  1325. .init = omap_hsmmc_init_setup,
  1326. #ifdef OMAP_HSMMC_USE_GPIO
  1327. .getcd = omap_hsmmc_getcd,
  1328. .getwp = omap_hsmmc_getwp,
  1329. #endif
  1330. };
  1331. #endif
  1332. #if !CONFIG_IS_ENABLED(DM_MMC)
  1333. int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
  1334. int wp_gpio)
  1335. {
  1336. struct mmc *mmc;
  1337. struct omap_hsmmc_data *priv;
  1338. struct mmc_config *cfg;
  1339. uint host_caps_val;
  1340. priv = calloc(1, sizeof(*priv));
  1341. if (priv == NULL)
  1342. return -1;
  1343. host_caps_val = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
  1344. switch (dev_index) {
  1345. case 0:
  1346. priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
  1347. break;
  1348. #ifdef OMAP_HSMMC2_BASE
  1349. case 1:
  1350. priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE;
  1351. #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \
  1352. defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \
  1353. defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \
  1354. defined(CONFIG_HSMMC2_8BIT)
  1355. /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */
  1356. host_caps_val |= MMC_MODE_8BIT;
  1357. #endif
  1358. break;
  1359. #endif
  1360. #ifdef OMAP_HSMMC3_BASE
  1361. case 2:
  1362. priv->base_addr = (struct hsmmc *)OMAP_HSMMC3_BASE;
  1363. #if defined(CONFIG_DRA7XX) && defined(CONFIG_HSMMC3_8BIT)
  1364. /* Enable 8-bit interface for eMMC on DRA7XX */
  1365. host_caps_val |= MMC_MODE_8BIT;
  1366. #endif
  1367. break;
  1368. #endif
  1369. default:
  1370. priv->base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE;
  1371. return 1;
  1372. }
  1373. #ifdef OMAP_HSMMC_USE_GPIO
  1374. /* on error gpio values are set to -1, which is what we want */
  1375. priv->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd");
  1376. priv->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp");
  1377. #endif
  1378. cfg = &priv->cfg;
  1379. cfg->name = "OMAP SD/MMC";
  1380. cfg->ops = &omap_hsmmc_ops;
  1381. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  1382. cfg->host_caps = host_caps_val & ~host_caps_mask;
  1383. cfg->f_min = 400000;
  1384. if (f_max != 0)
  1385. cfg->f_max = f_max;
  1386. else {
  1387. if (cfg->host_caps & MMC_MODE_HS) {
  1388. if (cfg->host_caps & MMC_MODE_HS_52MHz)
  1389. cfg->f_max = 52000000;
  1390. else
  1391. cfg->f_max = 26000000;
  1392. } else
  1393. cfg->f_max = 20000000;
  1394. }
  1395. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  1396. #if defined(CONFIG_OMAP34XX)
  1397. /*
  1398. * Silicon revs 2.1 and older do not support multiblock transfers.
  1399. */
  1400. if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
  1401. cfg->b_max = 1;
  1402. #endif
  1403. mmc = mmc_create(cfg, priv);
  1404. if (mmc == NULL)
  1405. return -1;
  1406. return 0;
  1407. }
  1408. #else
  1409. #ifdef CONFIG_IODELAY_RECALIBRATION
  1410. static struct pad_conf_entry *
  1411. omap_hsmmc_get_pad_conf_entry(const fdt32_t *pinctrl, int count)
  1412. {
  1413. int index = 0;
  1414. struct pad_conf_entry *padconf;
  1415. padconf = (struct pad_conf_entry *)malloc(sizeof(*padconf) * count);
  1416. if (!padconf) {
  1417. debug("failed to allocate memory\n");
  1418. return 0;
  1419. }
  1420. while (index < count) {
  1421. padconf[index].offset = fdt32_to_cpu(pinctrl[2 * index]);
  1422. padconf[index].val = fdt32_to_cpu(pinctrl[2 * index + 1]);
  1423. index++;
  1424. }
  1425. return padconf;
  1426. }
  1427. static struct iodelay_cfg_entry *
  1428. omap_hsmmc_get_iodelay_cfg_entry(const fdt32_t *pinctrl, int count)
  1429. {
  1430. int index = 0;
  1431. struct iodelay_cfg_entry *iodelay;
  1432. iodelay = (struct iodelay_cfg_entry *)malloc(sizeof(*iodelay) * count);
  1433. if (!iodelay) {
  1434. debug("failed to allocate memory\n");
  1435. return 0;
  1436. }
  1437. while (index < count) {
  1438. iodelay[index].offset = fdt32_to_cpu(pinctrl[3 * index]);
  1439. iodelay[index].a_delay = fdt32_to_cpu(pinctrl[3 * index + 1]);
  1440. iodelay[index].g_delay = fdt32_to_cpu(pinctrl[3 * index + 2]);
  1441. index++;
  1442. }
  1443. return iodelay;
  1444. }
  1445. static const fdt32_t *omap_hsmmc_get_pinctrl_entry(u32 phandle,
  1446. const char *name, int *len)
  1447. {
  1448. const void *fdt = gd->fdt_blob;
  1449. int offset;
  1450. const fdt32_t *pinctrl;
  1451. offset = fdt_node_offset_by_phandle(fdt, phandle);
  1452. if (offset < 0) {
  1453. debug("failed to get pinctrl node %s.\n",
  1454. fdt_strerror(offset));
  1455. return 0;
  1456. }
  1457. pinctrl = fdt_getprop(fdt, offset, name, len);
  1458. if (!pinctrl) {
  1459. debug("failed to get property %s\n", name);
  1460. return 0;
  1461. }
  1462. return pinctrl;
  1463. }
  1464. static uint32_t omap_hsmmc_get_pad_conf_phandle(struct mmc *mmc,
  1465. char *prop_name)
  1466. {
  1467. const void *fdt = gd->fdt_blob;
  1468. const __be32 *phandle;
  1469. int node = dev_of_offset(mmc->dev);
  1470. phandle = fdt_getprop(fdt, node, prop_name, NULL);
  1471. if (!phandle) {
  1472. debug("failed to get property %s\n", prop_name);
  1473. return 0;
  1474. }
  1475. return fdt32_to_cpu(*phandle);
  1476. }
  1477. static uint32_t omap_hsmmc_get_iodelay_phandle(struct mmc *mmc,
  1478. char *prop_name)
  1479. {
  1480. const void *fdt = gd->fdt_blob;
  1481. const __be32 *phandle;
  1482. int len;
  1483. int count;
  1484. int node = dev_of_offset(mmc->dev);
  1485. phandle = fdt_getprop(fdt, node, prop_name, &len);
  1486. if (!phandle) {
  1487. debug("failed to get property %s\n", prop_name);
  1488. return 0;
  1489. }
  1490. /* No manual mode iodelay values if count < 2 */
  1491. count = len / sizeof(*phandle);
  1492. if (count < 2)
  1493. return 0;
  1494. return fdt32_to_cpu(*(phandle + 1));
  1495. }
  1496. static struct pad_conf_entry *
  1497. omap_hsmmc_get_pad_conf(struct mmc *mmc, char *prop_name, int *npads)
  1498. {
  1499. int len;
  1500. int count;
  1501. struct pad_conf_entry *padconf;
  1502. u32 phandle;
  1503. const fdt32_t *pinctrl;
  1504. phandle = omap_hsmmc_get_pad_conf_phandle(mmc, prop_name);
  1505. if (!phandle)
  1506. return ERR_PTR(-EINVAL);
  1507. pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-single,pins",
  1508. &len);
  1509. if (!pinctrl)
  1510. return ERR_PTR(-EINVAL);
  1511. count = (len / sizeof(*pinctrl)) / 2;
  1512. padconf = omap_hsmmc_get_pad_conf_entry(pinctrl, count);
  1513. if (!padconf)
  1514. return ERR_PTR(-EINVAL);
  1515. *npads = count;
  1516. return padconf;
  1517. }
  1518. static struct iodelay_cfg_entry *
  1519. omap_hsmmc_get_iodelay(struct mmc *mmc, char *prop_name, int *niodelay)
  1520. {
  1521. int len;
  1522. int count;
  1523. struct iodelay_cfg_entry *iodelay;
  1524. u32 phandle;
  1525. const fdt32_t *pinctrl;
  1526. phandle = omap_hsmmc_get_iodelay_phandle(mmc, prop_name);
  1527. /* Not all modes have manual mode iodelay values. So its not fatal */
  1528. if (!phandle)
  1529. return 0;
  1530. pinctrl = omap_hsmmc_get_pinctrl_entry(phandle, "pinctrl-pin-array",
  1531. &len);
  1532. if (!pinctrl)
  1533. return ERR_PTR(-EINVAL);
  1534. count = (len / sizeof(*pinctrl)) / 3;
  1535. iodelay = omap_hsmmc_get_iodelay_cfg_entry(pinctrl, count);
  1536. if (!iodelay)
  1537. return ERR_PTR(-EINVAL);
  1538. *niodelay = count;
  1539. return iodelay;
  1540. }
  1541. static struct omap_hsmmc_pinctrl_state *
  1542. omap_hsmmc_get_pinctrl_by_mode(struct mmc *mmc, char *mode)
  1543. {
  1544. int index;
  1545. int npads = 0;
  1546. int niodelays = 0;
  1547. const void *fdt = gd->fdt_blob;
  1548. int node = dev_of_offset(mmc->dev);
  1549. char prop_name[11];
  1550. struct omap_hsmmc_pinctrl_state *pinctrl_state;
  1551. pinctrl_state = (struct omap_hsmmc_pinctrl_state *)
  1552. malloc(sizeof(*pinctrl_state));
  1553. if (!pinctrl_state) {
  1554. debug("failed to allocate memory\n");
  1555. return 0;
  1556. }
  1557. index = fdt_stringlist_search(fdt, node, "pinctrl-names", mode);
  1558. if (index < 0) {
  1559. debug("fail to find %s mode %s\n", mode, fdt_strerror(index));
  1560. goto err_pinctrl_state;
  1561. }
  1562. sprintf(prop_name, "pinctrl-%d", index);
  1563. pinctrl_state->padconf = omap_hsmmc_get_pad_conf(mmc, prop_name,
  1564. &npads);
  1565. if (IS_ERR(pinctrl_state->padconf))
  1566. goto err_pinctrl_state;
  1567. pinctrl_state->npads = npads;
  1568. pinctrl_state->iodelay = omap_hsmmc_get_iodelay(mmc, prop_name,
  1569. &niodelays);
  1570. if (IS_ERR(pinctrl_state->iodelay))
  1571. goto err_padconf;
  1572. pinctrl_state->niodelays = niodelays;
  1573. return pinctrl_state;
  1574. err_padconf:
  1575. kfree(pinctrl_state->padconf);
  1576. err_pinctrl_state:
  1577. kfree(pinctrl_state);
  1578. return 0;
  1579. }
  1580. #define OMAP_HSMMC_SETUP_PINCTRL(capmask, mode, optional) \
  1581. do { \
  1582. struct omap_hsmmc_pinctrl_state *s = NULL; \
  1583. char str[20]; \
  1584. if (!(cfg->host_caps & capmask)) \
  1585. break; \
  1586. \
  1587. if (priv->hw_rev) { \
  1588. sprintf(str, "%s-%s", #mode, priv->hw_rev); \
  1589. s = omap_hsmmc_get_pinctrl_by_mode(mmc, str); \
  1590. } \
  1591. \
  1592. if (!s) \
  1593. s = omap_hsmmc_get_pinctrl_by_mode(mmc, #mode); \
  1594. \
  1595. if (!s && !optional) { \
  1596. debug("%s: no pinctrl for %s\n", \
  1597. mmc->dev->name, #mode); \
  1598. cfg->host_caps &= ~(capmask); \
  1599. } else { \
  1600. priv->mode##_pinctrl_state = s; \
  1601. } \
  1602. } while (0)
  1603. static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc)
  1604. {
  1605. struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
  1606. struct mmc_config *cfg = omap_hsmmc_get_cfg(mmc);
  1607. struct omap_hsmmc_pinctrl_state *default_pinctrl;
  1608. if (!(priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY))
  1609. return 0;
  1610. default_pinctrl = omap_hsmmc_get_pinctrl_by_mode(mmc, "default");
  1611. if (!default_pinctrl) {
  1612. printf("no pinctrl state for default mode\n");
  1613. return -EINVAL;
  1614. }
  1615. priv->default_pinctrl_state = default_pinctrl;
  1616. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR104), sdr104, false);
  1617. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR50), sdr50, false);
  1618. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_DDR50), ddr50, false);
  1619. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR25), sdr25, false);
  1620. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(UHS_SDR12), sdr12, false);
  1621. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_HS_200), hs200_1_8v, false);
  1622. OMAP_HSMMC_SETUP_PINCTRL(MMC_CAP(MMC_DDR_52), ddr_1_8v, false);
  1623. OMAP_HSMMC_SETUP_PINCTRL(MMC_MODE_HS, hs, true);
  1624. return 0;
  1625. }
  1626. #endif
  1627. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  1628. #ifdef CONFIG_OMAP54XX
  1629. __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
  1630. {
  1631. return NULL;
  1632. }
  1633. #endif
  1634. static int omap_hsmmc_of_to_plat(struct udevice *dev)
  1635. {
  1636. struct omap_hsmmc_plat *plat = dev_get_plat(dev);
  1637. struct omap_mmc_of_data *of_data = (void *)dev_get_driver_data(dev);
  1638. struct mmc_config *cfg = &plat->cfg;
  1639. #ifdef CONFIG_OMAP54XX
  1640. const struct mmc_platform_fixups *fixups;
  1641. #endif
  1642. const void *fdt = gd->fdt_blob;
  1643. int node = dev_of_offset(dev);
  1644. int ret;
  1645. plat->base_addr = map_physmem(dev_read_addr(dev),
  1646. sizeof(struct hsmmc *),
  1647. MAP_NOCACHE);
  1648. ret = mmc_of_parse(dev, cfg);
  1649. if (ret < 0)
  1650. return ret;
  1651. if (!cfg->f_max)
  1652. cfg->f_max = 52000000;
  1653. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  1654. cfg->f_min = 400000;
  1655. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  1656. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  1657. if (fdtdec_get_bool(fdt, node, "ti,dual-volt"))
  1658. plat->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
  1659. if (fdtdec_get_bool(fdt, node, "no-1-8-v"))
  1660. plat->controller_flags |= OMAP_HSMMC_NO_1_8_V;
  1661. if (of_data)
  1662. plat->controller_flags |= of_data->controller_flags;
  1663. #ifdef CONFIG_OMAP54XX
  1664. fixups = platform_fixups_mmc(dev_read_addr(dev));
  1665. if (fixups) {
  1666. plat->hw_rev = fixups->hw_rev;
  1667. cfg->host_caps &= ~fixups->unsupported_caps;
  1668. cfg->f_max = fixups->max_freq;
  1669. }
  1670. #endif
  1671. return 0;
  1672. }
  1673. #endif
  1674. #ifdef CONFIG_BLK
  1675. static int omap_hsmmc_bind(struct udevice *dev)
  1676. {
  1677. struct omap_hsmmc_plat *plat = dev_get_plat(dev);
  1678. plat->mmc = calloc(1, sizeof(struct mmc));
  1679. return mmc_bind(dev, plat->mmc, &plat->cfg);
  1680. }
  1681. #endif
  1682. static int omap_hsmmc_probe(struct udevice *dev)
  1683. {
  1684. struct omap_hsmmc_plat *plat = dev_get_plat(dev);
  1685. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  1686. struct omap_hsmmc_data *priv = dev_get_priv(dev);
  1687. struct mmc_config *cfg = &plat->cfg;
  1688. struct mmc *mmc;
  1689. #ifdef CONFIG_IODELAY_RECALIBRATION
  1690. int ret;
  1691. #endif
  1692. cfg->name = "OMAP SD/MMC";
  1693. priv->base_addr = plat->base_addr;
  1694. priv->controller_flags = plat->controller_flags;
  1695. priv->hw_rev = plat->hw_rev;
  1696. #ifdef CONFIG_BLK
  1697. mmc = plat->mmc;
  1698. #else
  1699. mmc = mmc_create(cfg, priv);
  1700. if (mmc == NULL)
  1701. return -1;
  1702. #endif
  1703. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  1704. device_get_supply_regulator(dev, "pbias-supply",
  1705. &priv->pbias_supply);
  1706. #endif
  1707. #if defined(OMAP_HSMMC_USE_GPIO)
  1708. #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DM_GPIO)
  1709. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
  1710. gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
  1711. #endif
  1712. #endif
  1713. mmc->dev = dev;
  1714. upriv->mmc = mmc;
  1715. #ifdef CONFIG_IODELAY_RECALIBRATION
  1716. ret = omap_hsmmc_get_pinctrl_state(mmc);
  1717. /*
  1718. * disable high speed modes for the platforms that require IO delay
  1719. * and for which we don't have this information
  1720. */
  1721. if ((ret < 0) &&
  1722. (priv->controller_flags & OMAP_HSMMC_REQUIRE_IODELAY)) {
  1723. priv->controller_flags &= ~OMAP_HSMMC_REQUIRE_IODELAY;
  1724. cfg->host_caps &= ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_DDR_52) |
  1725. UHS_CAPS);
  1726. }
  1727. #endif
  1728. return omap_hsmmc_init_setup(mmc);
  1729. }
  1730. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  1731. static const struct omap_mmc_of_data dra7_mmc_of_data = {
  1732. .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY,
  1733. };
  1734. static const struct udevice_id omap_hsmmc_ids[] = {
  1735. { .compatible = "ti,omap3-hsmmc" },
  1736. { .compatible = "ti,omap4-hsmmc" },
  1737. { .compatible = "ti,am33xx-hsmmc" },
  1738. { .compatible = "ti,dra7-hsmmc", .data = (ulong)&dra7_mmc_of_data },
  1739. { }
  1740. };
  1741. #endif
  1742. U_BOOT_DRIVER(omap_hsmmc) = {
  1743. .name = "omap_hsmmc",
  1744. .id = UCLASS_MMC,
  1745. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  1746. .of_match = omap_hsmmc_ids,
  1747. .of_to_plat = omap_hsmmc_of_to_plat,
  1748. .plat_auto = sizeof(struct omap_hsmmc_plat),
  1749. #endif
  1750. #ifdef CONFIG_BLK
  1751. .bind = omap_hsmmc_bind,
  1752. #endif
  1753. .ops = &omap_hsmmc_ops,
  1754. .probe = omap_hsmmc_probe,
  1755. .priv_auto = sizeof(struct omap_hsmmc_data),
  1756. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  1757. .flags = DM_FLAG_PRE_RELOC,
  1758. #endif
  1759. };
  1760. #endif