mvebu_mmc.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Marvell MMC/SD/SDIO driver
  4. *
  5. * (C) Copyright 2012-2014
  6. * Marvell Semiconductor <www.marvell.com>
  7. * Written-by: Maen Suleiman, Gerald Kerma
  8. */
  9. #include <common.h>
  10. #include <errno.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <dm.h>
  14. #include <fdtdec.h>
  15. #include <part.h>
  16. #include <mmc.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/soc.h>
  20. #include <mvebu_mmc.h>
  21. #include <dm/device_compat.h>
  22. #define MVEBU_TARGET_DRAM 0
  23. #define TIMEOUT_DELAY 5*CONFIG_SYS_HZ /* wait 5 seconds */
  24. static inline void *get_regbase(const struct mmc *mmc)
  25. {
  26. struct mvebu_mmc_plat *pdata = mmc->priv;
  27. return pdata->iobase;
  28. }
  29. static void mvebu_mmc_write(const struct mmc *mmc, u32 offs, u32 val)
  30. {
  31. writel(val, get_regbase(mmc) + (offs));
  32. }
  33. static u32 mvebu_mmc_read(const struct mmc *mmc, u32 offs)
  34. {
  35. return readl(get_regbase(mmc) + (offs));
  36. }
  37. static int mvebu_mmc_setup_data(struct udevice *dev, struct mmc_data *data)
  38. {
  39. struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
  40. struct mmc *mmc = &pdata->mmc;
  41. u32 ctrl_reg;
  42. dev_dbg(dev, "data %s : blocks=%d blksz=%d\n",
  43. (data->flags & MMC_DATA_READ) ? "read" : "write",
  44. data->blocks, data->blocksize);
  45. /* default to maximum timeout */
  46. ctrl_reg = mvebu_mmc_read(mmc, SDIO_HOST_CTRL);
  47. ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
  48. mvebu_mmc_write(mmc, SDIO_HOST_CTRL, ctrl_reg);
  49. if (data->flags & MMC_DATA_READ) {
  50. mvebu_mmc_write(mmc, SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);
  51. mvebu_mmc_write(mmc, SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);
  52. } else {
  53. mvebu_mmc_write(mmc, SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);
  54. mvebu_mmc_write(mmc, SDIO_SYS_ADDR_HI, (u32)data->src >> 16);
  55. }
  56. mvebu_mmc_write(mmc, SDIO_BLK_COUNT, data->blocks);
  57. mvebu_mmc_write(mmc, SDIO_BLK_SIZE, data->blocksize);
  58. return 0;
  59. }
  60. static int mvebu_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  61. struct mmc_data *data)
  62. {
  63. ulong start;
  64. ushort waittype = 0;
  65. ushort resptype = 0;
  66. ushort xfertype = 0;
  67. ushort resp_indx = 0;
  68. struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
  69. struct mmc *mmc = &pdata->mmc;
  70. dev_dbg(dev, "cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
  71. cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
  72. dev_dbg(dev, "cmd %d (hw state 0x%04x)\n",
  73. cmd->cmdidx, mvebu_mmc_read(mmc, SDIO_HW_STATE));
  74. /*
  75. * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
  76. * register is sometimes not set before a while when some
  77. * "unusual" data block sizes are used (such as with the SWITCH
  78. * command), even despite the fact that the XFER_DONE interrupt
  79. * was raised. And if another data transfer starts before
  80. * this bit comes to good sense (which eventually happens by
  81. * itself) then the new transfer simply fails with a timeout.
  82. */
  83. if (!(mvebu_mmc_read(mmc, SDIO_HW_STATE) & CMD_FIFO_EMPTY)) {
  84. ushort hw_state, count = 0;
  85. start = get_timer(0);
  86. do {
  87. hw_state = mvebu_mmc_read(mmc, SDIO_HW_STATE);
  88. if ((get_timer(0) - start) > TIMEOUT_DELAY) {
  89. printf("%s : FIFO_EMPTY bit missing\n",
  90. dev->name);
  91. break;
  92. }
  93. count++;
  94. } while (!(hw_state & CMD_FIFO_EMPTY));
  95. dev_dbg(dev, "*** wait for FIFO_EMPTY bit (hw=0x%04x, count=%d, jiffies=%ld)\n",
  96. hw_state, count, (get_timer(0) - (start)));
  97. }
  98. /* Clear status */
  99. mvebu_mmc_write(mmc, SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
  100. mvebu_mmc_write(mmc, SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
  101. resptype = SDIO_CMD_INDEX(cmd->cmdidx);
  102. /* Analyzing resptype/xfertype/waittype for the command */
  103. if (cmd->resp_type & MMC_RSP_BUSY)
  104. resptype |= SDIO_CMD_RSP_48BUSY;
  105. else if (cmd->resp_type & MMC_RSP_136)
  106. resptype |= SDIO_CMD_RSP_136;
  107. else if (cmd->resp_type & MMC_RSP_PRESENT)
  108. resptype |= SDIO_CMD_RSP_48;
  109. else
  110. resptype |= SDIO_CMD_RSP_NONE;
  111. if (cmd->resp_type & MMC_RSP_CRC)
  112. resptype |= SDIO_CMD_CHECK_CMDCRC;
  113. if (cmd->resp_type & MMC_RSP_OPCODE)
  114. resptype |= SDIO_CMD_INDX_CHECK;
  115. if (cmd->resp_type & MMC_RSP_PRESENT) {
  116. resptype |= SDIO_UNEXPECTED_RESP;
  117. waittype |= SDIO_NOR_UNEXP_RSP;
  118. }
  119. if (data) {
  120. int err = mvebu_mmc_setup_data(dev, data);
  121. if (err) {
  122. dev_dbg(dev, "command DATA error :%x\n", err);
  123. return err;
  124. }
  125. resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
  126. xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
  127. if (data->flags & MMC_DATA_READ) {
  128. xfertype |= SDIO_XFER_MODE_TO_HOST;
  129. waittype = SDIO_NOR_DMA_INI;
  130. } else {
  131. waittype |= SDIO_NOR_XFER_DONE;
  132. }
  133. } else {
  134. waittype |= SDIO_NOR_CMD_DONE;
  135. }
  136. /* Setting cmd arguments */
  137. mvebu_mmc_write(mmc, SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
  138. mvebu_mmc_write(mmc, SDIO_ARG_HI, cmd->cmdarg >> 16);
  139. /* Setting Xfer mode */
  140. mvebu_mmc_write(mmc, SDIO_XFER_MODE, xfertype);
  141. /* Sending command */
  142. mvebu_mmc_write(mmc, SDIO_CMD, resptype);
  143. start = get_timer(0);
  144. while (!((mvebu_mmc_read(mmc, SDIO_NOR_INTR_STATUS)) & waittype)) {
  145. if (mvebu_mmc_read(mmc, SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
  146. dev_dbg(dev, "error! cmdidx : %d, err reg: %04x\n",
  147. cmd->cmdidx,
  148. mvebu_mmc_read(mmc, SDIO_ERR_INTR_STATUS));
  149. if (mvebu_mmc_read(mmc, SDIO_ERR_INTR_STATUS) &
  150. (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) {
  151. dev_dbg(dev, "command READ timed out\n");
  152. return -ETIMEDOUT;
  153. }
  154. dev_dbg(dev, "command READ error\n");
  155. return -ECOMM;
  156. }
  157. if ((get_timer(0) - start) > TIMEOUT_DELAY) {
  158. dev_dbg(dev, "command timed out\n");
  159. return -ETIMEDOUT;
  160. }
  161. }
  162. /* Handling response */
  163. if (cmd->resp_type & MMC_RSP_136) {
  164. uint response[8];
  165. for (resp_indx = 0; resp_indx < 8; resp_indx++)
  166. response[resp_indx] = mvebu_mmc_read(mmc, SDIO_RSP(resp_indx));
  167. cmd->response[0] = ((response[0] & 0x03ff) << 22) |
  168. ((response[1] & 0xffff) << 6) |
  169. ((response[2] & 0xfc00) >> 10);
  170. cmd->response[1] = ((response[2] & 0x03ff) << 22) |
  171. ((response[3] & 0xffff) << 6) |
  172. ((response[4] & 0xfc00) >> 10);
  173. cmd->response[2] = ((response[4] & 0x03ff) << 22) |
  174. ((response[5] & 0xffff) << 6) |
  175. ((response[6] & 0xfc00) >> 10);
  176. cmd->response[3] = ((response[6] & 0x03ff) << 22) |
  177. ((response[7] & 0x3fff) << 8);
  178. } else if (cmd->resp_type & MMC_RSP_PRESENT) {
  179. uint response[3];
  180. for (resp_indx = 0; resp_indx < 3; resp_indx++)
  181. response[resp_indx] = mvebu_mmc_read(mmc, SDIO_RSP(resp_indx));
  182. cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) |
  183. ((response[1] & 0xffff) << (14 - 8)) |
  184. ((response[0] & 0x03ff) << (30 - 8));
  185. cmd->response[1] = ((response[0] & 0xfc00) >> 10);
  186. cmd->response[2] = 0;
  187. cmd->response[3] = 0;
  188. } else {
  189. cmd->response[0] = 0;
  190. cmd->response[1] = 0;
  191. cmd->response[2] = 0;
  192. cmd->response[3] = 0;
  193. }
  194. dev_dbg(dev, "resp[0x%x] ", cmd->resp_type);
  195. debug("[0x%x] ", cmd->response[0]);
  196. debug("[0x%x] ", cmd->response[1]);
  197. debug("[0x%x] ", cmd->response[2]);
  198. debug("[0x%x] ", cmd->response[3]);
  199. debug("\n");
  200. if (mvebu_mmc_read(mmc, SDIO_ERR_INTR_STATUS) &
  201. (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
  202. return -ETIMEDOUT;
  203. return 0;
  204. }
  205. static void mvebu_mmc_power_up(struct udevice *dev)
  206. {
  207. struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
  208. struct mmc *mmc = &pdata->mmc;
  209. dev_dbg(dev, "power up\n");
  210. /* disable interrupts */
  211. mvebu_mmc_write(mmc, SDIO_NOR_INTR_EN, 0);
  212. mvebu_mmc_write(mmc, SDIO_ERR_INTR_EN, 0);
  213. /* SW reset */
  214. mvebu_mmc_write(mmc, SDIO_SW_RESET, SDIO_SW_RESET_NOW);
  215. mvebu_mmc_write(mmc, SDIO_XFER_MODE, 0);
  216. /* enable status */
  217. mvebu_mmc_write(mmc, SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
  218. mvebu_mmc_write(mmc, SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
  219. /* enable interrupts status */
  220. mvebu_mmc_write(mmc, SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
  221. mvebu_mmc_write(mmc, SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
  222. }
  223. static void mvebu_mmc_set_clk(struct udevice *dev, unsigned int clock)
  224. {
  225. unsigned int m;
  226. struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
  227. struct mmc *mmc = &pdata->mmc;
  228. if (clock == 0) {
  229. dev_dbg(dev, "clock off\n");
  230. mvebu_mmc_write(mmc, SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
  231. mvebu_mmc_write(mmc, SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);
  232. } else {
  233. m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1;
  234. if (m > MVEBU_MMC_BASE_DIV_MAX)
  235. m = MVEBU_MMC_BASE_DIV_MAX;
  236. mvebu_mmc_write(mmc, SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
  237. dev_dbg(dev, "clock (%d) div : %d\n", clock, m);
  238. }
  239. }
  240. static void mvebu_mmc_set_bus(struct udevice *dev, unsigned int bus)
  241. {
  242. struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
  243. struct mmc *mmc = &pdata->mmc;
  244. u32 ctrl_reg = 0;
  245. ctrl_reg = mvebu_mmc_read(mmc, SDIO_HOST_CTRL);
  246. ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
  247. switch (bus) {
  248. case 4:
  249. ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
  250. break;
  251. case 1:
  252. default:
  253. ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
  254. }
  255. /* default transfer mode */
  256. ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;
  257. ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
  258. /* default to maximum timeout */
  259. ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
  260. ctrl_reg |= SDIO_HOST_CTRL_TMOUT_EN;
  261. ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
  262. ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
  263. dev_dbg(dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
  264. (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
  265. "push-pull" : "open-drain",
  266. (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
  267. "4bit-width" : "1bit-width",
  268. (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
  269. "high-speed" : "");
  270. mvebu_mmc_write(mmc, SDIO_HOST_CTRL, ctrl_reg);
  271. }
  272. static int mvebu_mmc_set_ios(struct udevice *dev)
  273. {
  274. struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
  275. struct mmc *mmc = &pdata->mmc;
  276. dev_dbg(dev, "bus[%d] clock[%d]\n",
  277. mmc->bus_width, mmc->clock);
  278. mvebu_mmc_set_bus(dev, mmc->bus_width);
  279. mvebu_mmc_set_clk(dev, mmc->clock);
  280. return 0;
  281. }
  282. /*
  283. * Set window register.
  284. */
  285. static void mvebu_window_setup(const struct mmc *mmc)
  286. {
  287. int i;
  288. for (i = 0; i < 4; i++) {
  289. mvebu_mmc_write(mmc, WINDOW_CTRL(i), 0);
  290. mvebu_mmc_write(mmc, WINDOW_BASE(i), 0);
  291. }
  292. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  293. u32 size, base, attrib;
  294. /* Enable DRAM bank */
  295. switch (i) {
  296. case 0:
  297. attrib = KWCPU_ATTR_DRAM_CS0;
  298. break;
  299. case 1:
  300. attrib = KWCPU_ATTR_DRAM_CS1;
  301. break;
  302. case 2:
  303. attrib = KWCPU_ATTR_DRAM_CS2;
  304. break;
  305. case 3:
  306. attrib = KWCPU_ATTR_DRAM_CS3;
  307. break;
  308. default:
  309. /* invalide bank, disable access */
  310. attrib = 0;
  311. break;
  312. }
  313. size = gd->bd->bi_dram[i].size;
  314. base = gd->bd->bi_dram[i].start;
  315. if (size && attrib) {
  316. mvebu_mmc_write(mmc, WINDOW_CTRL(i),
  317. MVCPU_WIN_CTRL_DATA(size,
  318. MVEBU_TARGET_DRAM,
  319. attrib,
  320. MVCPU_WIN_ENABLE));
  321. } else {
  322. mvebu_mmc_write(mmc, WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
  323. }
  324. mvebu_mmc_write(mmc, WINDOW_BASE(i), base);
  325. }
  326. }
  327. static int mvebu_mmc_initialize(struct udevice *dev)
  328. {
  329. struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
  330. struct mmc *mmc = &pdata->mmc;
  331. dev_dbg(dev, "%s\n", __func__);
  332. /*
  333. * Setting host parameters
  334. * Initial Host Ctrl : Timeout : max , Normal Speed mode,
  335. * 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line
  336. */
  337. mvebu_mmc_write(mmc, SDIO_HOST_CTRL,
  338. SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
  339. SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
  340. SDIO_HOST_CTRL_BIG_ENDIAN |
  341. SDIO_HOST_CTRL_PUSH_PULL_EN |
  342. SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
  343. mvebu_mmc_write(mmc, SDIO_CLK_CTRL, 0);
  344. /* enable status */
  345. mvebu_mmc_write(mmc, SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
  346. mvebu_mmc_write(mmc, SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
  347. /* disable interrupts */
  348. mvebu_mmc_write(mmc, SDIO_NOR_INTR_EN, 0);
  349. mvebu_mmc_write(mmc, SDIO_ERR_INTR_EN, 0);
  350. mvebu_window_setup(mmc);
  351. /* SW reset */
  352. mvebu_mmc_write(mmc, SDIO_SW_RESET, SDIO_SW_RESET_NOW);
  353. return 0;
  354. }
  355. static int mvebu_mmc_of_to_plat(struct udevice *dev)
  356. {
  357. struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
  358. fdt_addr_t addr;
  359. addr = dev_read_addr(dev);
  360. if (addr == FDT_ADDR_T_NONE)
  361. return -EINVAL;
  362. pdata->iobase = (void *)addr;
  363. return 0;
  364. }
  365. static int mvebu_mmc_probe(struct udevice *dev)
  366. {
  367. struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
  368. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  369. struct mmc *mmc = &pdata->mmc;
  370. struct mmc_config *cfg = &pdata->cfg;
  371. cfg->name = dev->name;
  372. cfg->f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX;
  373. cfg->f_max = MVEBU_MMC_CLOCKRATE_MAX;
  374. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  375. cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
  376. cfg->part_type = PART_TYPE_DOS;
  377. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  378. mmc->cfg = cfg;
  379. mmc->priv = pdata;
  380. mmc->dev = dev;
  381. upriv->mmc = mmc;
  382. mvebu_mmc_power_up(dev);
  383. mvebu_mmc_initialize(dev);
  384. return 0;
  385. }
  386. static const struct dm_mmc_ops mvebu_dm_mmc_ops = {
  387. .send_cmd = mvebu_mmc_send_cmd,
  388. .set_ios = mvebu_mmc_set_ios,
  389. };
  390. static int mvebu_mmc_bind(struct udevice *dev)
  391. {
  392. struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
  393. return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
  394. }
  395. static const struct udevice_id mvebu_mmc_match[] = {
  396. { .compatible = "marvell,orion-sdio" },
  397. { /* sentinel */ }
  398. };
  399. U_BOOT_DRIVER(mvebu_mmc) = {
  400. .name = "mvebu_mmc",
  401. .id = UCLASS_MMC,
  402. .of_match = mvebu_mmc_match,
  403. .ops = &mvebu_dm_mmc_ops,
  404. .probe = mvebu_mmc_probe,
  405. .bind = mvebu_mmc_bind,
  406. .of_to_plat = mvebu_mmc_of_to_plat,
  407. .plat_auto = sizeof(struct mvebu_mmc_plat),
  408. };