mv_sdhci.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Marvell SD Host Controller Interface
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <malloc.h>
  8. #include <sdhci.h>
  9. #include <asm/global_data.h>
  10. #include <linux/mbus.h>
  11. #define MVSDH_NAME "mv_sdh"
  12. #define SDHCI_WINDOW_CTRL(win) (0x4080 + ((win) << 4))
  13. #define SDHCI_WINDOW_BASE(win) (0x4084 + ((win) << 4))
  14. static void sdhci_mvebu_mbus_config(void __iomem *base)
  15. {
  16. const struct mbus_dram_target_info *dram;
  17. int i;
  18. dram = mvebu_mbus_dram_info();
  19. for (i = 0; i < 4; i++) {
  20. writel(0, base + SDHCI_WINDOW_CTRL(i));
  21. writel(0, base + SDHCI_WINDOW_BASE(i));
  22. }
  23. for (i = 0; i < dram->num_cs; i++) {
  24. const struct mbus_dram_window *cs = dram->cs + i;
  25. /* Write size, attributes and target id to control register */
  26. writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  27. (dram->mbus_dram_target_id << 4) | 1,
  28. base + SDHCI_WINDOW_CTRL(i));
  29. /* Write base address to base register */
  30. writel(cs->base, base + SDHCI_WINDOW_BASE(i));
  31. }
  32. }
  33. #ifndef CONFIG_DM_MMC
  34. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
  35. static struct sdhci_ops mv_ops;
  36. #if defined(CONFIG_SHEEVA_88SV331xV5)
  37. #define SD_CE_ATA_2 0xEA
  38. #define MMC_CARD 0x1000
  39. #define MMC_WIDTH 0x0100
  40. static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
  41. {
  42. struct mmc *mmc = host->mmc;
  43. u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2;
  44. if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) {
  45. if (mmc->bus_width == 8)
  46. writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata);
  47. else
  48. writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata);
  49. }
  50. writeb(val, host->ioaddr + reg);
  51. }
  52. #else
  53. #define mv_sdhci_writeb NULL
  54. #endif /* CONFIG_SHEEVA_88SV331xV5 */
  55. #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
  56. int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
  57. {
  58. struct sdhci_host *host = NULL;
  59. host = calloc(1, sizeof(*host));
  60. if (!host) {
  61. printf("sdh_host malloc fail!\n");
  62. return -ENOMEM;
  63. }
  64. host->name = MVSDH_NAME;
  65. host->ioaddr = (void *)regbase;
  66. host->quirks = quirks;
  67. host->max_clk = max_clk;
  68. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
  69. memset(&mv_ops, 0, sizeof(struct sdhci_ops));
  70. mv_ops.write_b = mv_sdhci_writeb;
  71. host->ops = &mv_ops;
  72. #endif
  73. if (CONFIG_IS_ENABLED(ARCH_MVEBU)) {
  74. /* Configure SDHCI MBUS mbus bridge windows */
  75. sdhci_mvebu_mbus_config((void __iomem *)regbase);
  76. }
  77. return add_sdhci(host, 0, min_clk);
  78. }
  79. #else
  80. DECLARE_GLOBAL_DATA_PTR;
  81. struct mv_sdhci_plat {
  82. struct mmc_config cfg;
  83. struct mmc mmc;
  84. };
  85. static int mv_sdhci_probe(struct udevice *dev)
  86. {
  87. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  88. struct mv_sdhci_plat *plat = dev_get_plat(dev);
  89. struct sdhci_host *host = dev_get_priv(dev);
  90. int ret;
  91. host->name = MVSDH_NAME;
  92. host->ioaddr = dev_read_addr_ptr(dev);
  93. host->quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD;
  94. host->mmc = &plat->mmc;
  95. host->mmc->dev = dev;
  96. host->mmc->priv = host;
  97. ret = mmc_of_parse(dev, &plat->cfg);
  98. if (ret)
  99. return ret;
  100. ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
  101. if (ret)
  102. return ret;
  103. if (CONFIG_IS_ENABLED(ARCH_MVEBU)) {
  104. /* Configure SDHCI MBUS mbus bridge windows */
  105. sdhci_mvebu_mbus_config(host->ioaddr);
  106. }
  107. upriv->mmc = host->mmc;
  108. return sdhci_probe(dev);
  109. }
  110. static int mv_sdhci_bind(struct udevice *dev)
  111. {
  112. struct mv_sdhci_plat *plat = dev_get_plat(dev);
  113. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  114. }
  115. static const struct udevice_id mv_sdhci_ids[] = {
  116. { .compatible = "marvell,armada-380-sdhci" },
  117. { }
  118. };
  119. U_BOOT_DRIVER(mv_sdhci_drv) = {
  120. .name = MVSDH_NAME,
  121. .id = UCLASS_MMC,
  122. .of_match = mv_sdhci_ids,
  123. .bind = mv_sdhci_bind,
  124. .probe = mv_sdhci_probe,
  125. .ops = &sdhci_ops,
  126. .priv_auto = sizeof(struct sdhci_host),
  127. .plat_auto = sizeof(struct mv_sdhci_plat),
  128. };
  129. #endif /* CONFIG_DM_MMC */