meson_gx_mmc.c 8.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Carlo Caione <carlo@caione.org>
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <fdtdec.h>
  10. #include <malloc.h>
  11. #include <pwrseq.h>
  12. #include <mmc.h>
  13. #include <asm/io.h>
  14. #include <asm/gpio.h>
  15. #include <linux/delay.h>
  16. #include <linux/log2.h>
  17. #include "meson_gx_mmc.h"
  18. bool meson_gx_mmc_is_compatible(struct udevice *dev,
  19. enum meson_gx_mmc_compatible family)
  20. {
  21. enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev);
  22. return compat == family;
  23. }
  24. static inline void *get_regbase(const struct mmc *mmc)
  25. {
  26. struct meson_mmc_plat *pdata = mmc->priv;
  27. return pdata->regbase;
  28. }
  29. static inline uint32_t meson_read(struct mmc *mmc, int offset)
  30. {
  31. return readl(get_regbase(mmc) + offset);
  32. }
  33. static inline void meson_write(struct mmc *mmc, uint32_t val, int offset)
  34. {
  35. writel(val, get_regbase(mmc) + offset);
  36. }
  37. static void meson_mmc_config_clock(struct mmc *mmc)
  38. {
  39. uint32_t meson_mmc_clk = 0;
  40. unsigned int clk, clk_src, clk_div;
  41. if (!mmc->clock)
  42. return;
  43. /* TOFIX This should use the proper clock taken from DT */
  44. /* 1GHz / CLK_MAX_DIV = 15,9 MHz */
  45. if (mmc->clock > 16000000) {
  46. clk = SD_EMMC_CLKSRC_DIV2;
  47. clk_src = CLK_SRC_DIV2;
  48. } else {
  49. clk = SD_EMMC_CLKSRC_24M;
  50. clk_src = CLK_SRC_24M;
  51. }
  52. clk_div = DIV_ROUND_UP(clk, mmc->clock);
  53. /*
  54. * SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180
  55. * If CLK_CO_PHASE_270 is used, it's more stable than other.
  56. * Other SoCs use CLK_CO_PHASE_180 by default.
  57. * It needs to find what is a proper value about each SoCs.
  58. */
  59. if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
  60. meson_mmc_clk |= CLK_CO_PHASE_270;
  61. else
  62. meson_mmc_clk |= CLK_CO_PHASE_180;
  63. /* 180 phase tx clock */
  64. meson_mmc_clk |= CLK_TX_PHASE_000;
  65. /* clock settings */
  66. meson_mmc_clk |= clk_src;
  67. meson_mmc_clk |= clk_div;
  68. meson_write(mmc, meson_mmc_clk, MESON_SD_EMMC_CLOCK);
  69. }
  70. static int meson_dm_mmc_set_ios(struct udevice *dev)
  71. {
  72. struct mmc *mmc = mmc_get_mmc_dev(dev);
  73. uint32_t meson_mmc_cfg;
  74. meson_mmc_config_clock(mmc);
  75. meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
  76. meson_mmc_cfg &= ~CFG_BUS_WIDTH_MASK;
  77. if (mmc->bus_width == 1)
  78. meson_mmc_cfg |= CFG_BUS_WIDTH_1;
  79. else if (mmc->bus_width == 4)
  80. meson_mmc_cfg |= CFG_BUS_WIDTH_4;
  81. else if (mmc->bus_width == 8)
  82. meson_mmc_cfg |= CFG_BUS_WIDTH_8;
  83. else
  84. return -EINVAL;
  85. /* 512 bytes block length */
  86. meson_mmc_cfg &= ~CFG_BL_LEN_MASK;
  87. meson_mmc_cfg |= CFG_BL_LEN_512;
  88. /* Response timeout 256 clk */
  89. meson_mmc_cfg &= ~CFG_RESP_TIMEOUT_MASK;
  90. meson_mmc_cfg |= CFG_RESP_TIMEOUT_256;
  91. /* Command-command gap 16 clk */
  92. meson_mmc_cfg &= ~CFG_RC_CC_MASK;
  93. meson_mmc_cfg |= CFG_RC_CC_16;
  94. meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG);
  95. return 0;
  96. }
  97. static void meson_mmc_setup_cmd(struct mmc *mmc, struct mmc_data *data,
  98. struct mmc_cmd *cmd)
  99. {
  100. uint32_t meson_mmc_cmd = 0, cfg;
  101. meson_mmc_cmd |= cmd->cmdidx << CMD_CFG_CMD_INDEX_SHIFT;
  102. if (cmd->resp_type & MMC_RSP_PRESENT) {
  103. if (cmd->resp_type & MMC_RSP_136)
  104. meson_mmc_cmd |= CMD_CFG_RESP_128;
  105. if (cmd->resp_type & MMC_RSP_BUSY)
  106. meson_mmc_cmd |= CMD_CFG_R1B;
  107. if (!(cmd->resp_type & MMC_RSP_CRC))
  108. meson_mmc_cmd |= CMD_CFG_RESP_NOCRC;
  109. } else {
  110. meson_mmc_cmd |= CMD_CFG_NO_RESP;
  111. }
  112. if (data) {
  113. cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
  114. cfg &= ~CFG_BL_LEN_MASK;
  115. cfg |= ilog2(data->blocksize) << CFG_BL_LEN_SHIFT;
  116. meson_write(mmc, cfg, MESON_SD_EMMC_CFG);
  117. if (data->flags == MMC_DATA_WRITE)
  118. meson_mmc_cmd |= CMD_CFG_DATA_WR;
  119. meson_mmc_cmd |= CMD_CFG_DATA_IO | CMD_CFG_BLOCK_MODE |
  120. data->blocks;
  121. }
  122. meson_mmc_cmd |= CMD_CFG_TIMEOUT_4S | CMD_CFG_OWNER |
  123. CMD_CFG_END_OF_CHAIN;
  124. meson_write(mmc, meson_mmc_cmd, MESON_SD_EMMC_CMD_CFG);
  125. }
  126. static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data)
  127. {
  128. struct meson_mmc_plat *pdata = mmc->priv;
  129. unsigned int data_size;
  130. uint32_t data_addr = 0;
  131. if (data) {
  132. data_size = data->blocks * data->blocksize;
  133. if (data->flags == MMC_DATA_READ) {
  134. data_addr = (ulong) data->dest;
  135. invalidate_dcache_range(data_addr,
  136. data_addr + data_size);
  137. } else {
  138. pdata->w_buf = calloc(data_size, sizeof(char));
  139. data_addr = (ulong) pdata->w_buf;
  140. memcpy(pdata->w_buf, data->src, data_size);
  141. flush_dcache_range(data_addr, data_addr + data_size);
  142. }
  143. }
  144. meson_write(mmc, data_addr, MESON_SD_EMMC_CMD_DAT);
  145. }
  146. static void meson_mmc_read_response(struct mmc *mmc, struct mmc_cmd *cmd)
  147. {
  148. if (cmd->resp_type & MMC_RSP_136) {
  149. cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP3);
  150. cmd->response[1] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP2);
  151. cmd->response[2] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP1);
  152. cmd->response[3] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
  153. } else {
  154. cmd->response[0] = meson_read(mmc, MESON_SD_EMMC_CMD_RSP);
  155. }
  156. }
  157. static int meson_dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  158. struct mmc_data *data)
  159. {
  160. struct mmc *mmc = mmc_get_mmc_dev(dev);
  161. struct meson_mmc_plat *pdata = mmc->priv;
  162. uint32_t status;
  163. ulong start;
  164. int ret = 0;
  165. /* max block size supported by chip is 512 byte */
  166. if (data && data->blocksize > 512)
  167. return -EINVAL;
  168. meson_mmc_setup_cmd(mmc, data, cmd);
  169. meson_mmc_setup_addr(mmc, data);
  170. meson_write(mmc, cmd->cmdarg, MESON_SD_EMMC_CMD_ARG);
  171. /* use 10s timeout */
  172. start = get_timer(0);
  173. do {
  174. status = meson_read(mmc, MESON_SD_EMMC_STATUS);
  175. } while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 10000);
  176. if (!(status & STATUS_END_OF_CHAIN))
  177. ret = -ETIMEDOUT;
  178. else if (status & STATUS_RESP_TIMEOUT)
  179. ret = -ETIMEDOUT;
  180. else if (status & STATUS_ERR_MASK)
  181. ret = -EIO;
  182. meson_mmc_read_response(mmc, cmd);
  183. if (data && data->flags == MMC_DATA_WRITE)
  184. free(pdata->w_buf);
  185. /* reset status bits */
  186. meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
  187. return ret;
  188. }
  189. static const struct dm_mmc_ops meson_dm_mmc_ops = {
  190. .send_cmd = meson_dm_mmc_send_cmd,
  191. .set_ios = meson_dm_mmc_set_ios,
  192. };
  193. static int meson_mmc_of_to_plat(struct udevice *dev)
  194. {
  195. struct meson_mmc_plat *pdata = dev_get_plat(dev);
  196. fdt_addr_t addr;
  197. addr = dev_read_addr(dev);
  198. if (addr == FDT_ADDR_T_NONE)
  199. return -EINVAL;
  200. pdata->regbase = (void *)addr;
  201. return 0;
  202. }
  203. static int meson_mmc_probe(struct udevice *dev)
  204. {
  205. struct meson_mmc_plat *pdata = dev_get_plat(dev);
  206. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  207. struct mmc *mmc = &pdata->mmc;
  208. struct mmc_config *cfg = &pdata->cfg;
  209. struct clk_bulk clocks;
  210. uint32_t val;
  211. int ret;
  212. /* Enable the clocks feeding the MMC controller */
  213. ret = clk_get_bulk(dev, &clocks);
  214. if (ret)
  215. return ret;
  216. ret = clk_enable_bulk(&clocks);
  217. if (ret)
  218. return ret;
  219. cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 |
  220. MMC_VDD_31_32 | MMC_VDD_165_195;
  221. cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT |
  222. MMC_MODE_HS_52MHz | MMC_MODE_HS;
  223. cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV);
  224. cfg->f_max = 100000000; /* 100 MHz */
  225. cfg->b_max = 511; /* max 512 - 1 blocks */
  226. cfg->name = dev->name;
  227. mmc->priv = pdata;
  228. upriv->mmc = mmc;
  229. mmc_set_clock(mmc, cfg->f_min, MMC_CLK_ENABLE);
  230. #ifdef CONFIG_MMC_PWRSEQ
  231. /* Enable power if needed */
  232. ret = mmc_pwrseq_get_power(dev, cfg);
  233. if (!ret) {
  234. ret = pwrseq_set_power(cfg->pwr_dev, true);
  235. if (ret)
  236. return ret;
  237. }
  238. #endif
  239. /* reset all status bits */
  240. meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
  241. /* disable interrupts */
  242. meson_write(mmc, 0, MESON_SD_EMMC_IRQ_EN);
  243. /* enable auto clock mode */
  244. val = meson_read(mmc, MESON_SD_EMMC_CFG);
  245. val &= ~CFG_SDCLK_ALWAYS_ON;
  246. val |= CFG_AUTO_CLK;
  247. meson_write(mmc, val, MESON_SD_EMMC_CFG);
  248. return 0;
  249. }
  250. int meson_mmc_bind(struct udevice *dev)
  251. {
  252. struct meson_mmc_plat *pdata = dev_get_plat(dev);
  253. return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
  254. }
  255. static const struct udevice_id meson_mmc_match[] = {
  256. { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX },
  257. { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX },
  258. { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 },
  259. { /* sentinel */ }
  260. };
  261. U_BOOT_DRIVER(meson_mmc) = {
  262. .name = "meson_gx_mmc",
  263. .id = UCLASS_MMC,
  264. .of_match = meson_mmc_match,
  265. .ops = &meson_dm_mmc_ops,
  266. .probe = meson_mmc_probe,
  267. .bind = meson_mmc_bind,
  268. .of_to_plat = meson_mmc_of_to_plat,
  269. .plat_auto = sizeof(struct meson_mmc_plat),
  270. };