iproc_sdhci.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 Broadcom.
  4. *
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <malloc.h>
  10. #include <sdhci.h>
  11. #include <asm/global_data.h>
  12. #include "mmc_private.h"
  13. #include <linux/delay.h>
  14. #define MAX_TUNING_LOOP 40
  15. DECLARE_GLOBAL_DATA_PTR;
  16. struct sdhci_iproc_host {
  17. struct sdhci_host host;
  18. u32 shadow_cmd;
  19. u32 shadow_blk;
  20. };
  21. #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
  22. static inline struct sdhci_iproc_host *to_iproc(struct sdhci_host *host)
  23. {
  24. return (struct sdhci_iproc_host *)host;
  25. }
  26. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
  27. static u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
  28. {
  29. u32 val = readl(host->ioaddr + reg);
  30. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS_TRACE
  31. printf("%s %d: readl [0x%02x] 0x%08x\n",
  32. host->name, host->index, reg, val);
  33. #endif
  34. return val;
  35. }
  36. static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
  37. {
  38. u32 val = sdhci_iproc_readl(host, (reg & ~3));
  39. u16 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
  40. return word;
  41. }
  42. static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
  43. {
  44. u32 val = sdhci_iproc_readl(host, (reg & ~3));
  45. u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
  46. return byte;
  47. }
  48. static void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
  49. {
  50. u32 clock = 0;
  51. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS_TRACE
  52. printf("%s %d: writel [0x%02x] 0x%08x\n",
  53. host->name, host->index, reg, val);
  54. #endif
  55. writel(val, host->ioaddr + reg);
  56. if (host->mmc)
  57. clock = host->mmc->clock;
  58. if (clock <= 400000) {
  59. /* Round up to micro-second four SD clock delay */
  60. if (clock)
  61. udelay((4 * 1000000 + clock - 1) / clock);
  62. else
  63. udelay(10);
  64. }
  65. }
  66. /*
  67. * The Arasan has a bugette whereby it may lose the content of successive
  68. * writes to the same register that are within two SD-card clock cycles of
  69. * each other (a clock domain crossing problem). The data
  70. * register does not have this problem, which is just as well - otherwise we'd
  71. * have to nobble the DMA engine too.
  72. *
  73. * This wouldn't be a problem with the code except that we can only write the
  74. * controller with 32-bit writes. So two different 16-bit registers are
  75. * written back to back creates the problem.
  76. *
  77. * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
  78. * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
  79. * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
  80. * the work around can be further optimized. We can keep shadow values of
  81. * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
  82. * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
  83. * by the TRANSFER+COMMAND in another 32-bit write.
  84. */
  85. static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
  86. {
  87. struct sdhci_iproc_host *iproc_host = to_iproc(host);
  88. u32 word_shift = REG_OFFSET_IN_BITS(reg);
  89. u32 mask = 0xffff << word_shift;
  90. u32 oldval, newval;
  91. if (reg == SDHCI_COMMAND) {
  92. /* Write the block now as we are issuing a command */
  93. if (iproc_host->shadow_blk != 0) {
  94. sdhci_iproc_writel(host, iproc_host->shadow_blk,
  95. SDHCI_BLOCK_SIZE);
  96. iproc_host->shadow_blk = 0;
  97. }
  98. oldval = iproc_host->shadow_cmd;
  99. } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
  100. /* Block size and count are stored in shadow reg */
  101. oldval = iproc_host->shadow_blk;
  102. } else {
  103. /* Read reg, all other registers are not shadowed */
  104. oldval = sdhci_iproc_readl(host, (reg & ~3));
  105. }
  106. newval = (oldval & ~mask) | (val << word_shift);
  107. if (reg == SDHCI_TRANSFER_MODE) {
  108. /* Save the transfer mode until the command is issued */
  109. iproc_host->shadow_cmd = newval;
  110. } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
  111. /* Save the block info until the command is issued */
  112. iproc_host->shadow_blk = newval;
  113. } else {
  114. /* Command or other regular 32-bit write */
  115. sdhci_iproc_writel(host, newval, reg & ~3);
  116. }
  117. }
  118. static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
  119. {
  120. u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
  121. u32 byte_shift = REG_OFFSET_IN_BITS(reg);
  122. u32 mask = 0xff << byte_shift;
  123. u32 newval = (oldval & ~mask) | (val << byte_shift);
  124. sdhci_iproc_writel(host, newval, reg & ~3);
  125. }
  126. #endif
  127. static int sdhci_iproc_set_ios_post(struct sdhci_host *host)
  128. {
  129. struct mmc *mmc = (struct mmc *)host->mmc;
  130. u32 ctrl;
  131. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  132. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  133. ctrl |= SDHCI_CTRL_VDD_180;
  134. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  135. }
  136. sdhci_set_uhs_timing(host);
  137. return 0;
  138. }
  139. static void sdhci_start_tuning(struct sdhci_host *host)
  140. {
  141. u32 ctrl;
  142. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  143. ctrl |= SDHCI_CTRL_EXEC_TUNING;
  144. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  145. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
  146. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
  147. }
  148. static void sdhci_end_tuning(struct sdhci_host *host)
  149. {
  150. /* Enable only interrupts served by the SD controller */
  151. sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
  152. SDHCI_INT_ENABLE);
  153. /* Mask all sdhci interrupt sources */
  154. sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
  155. }
  156. static int sdhci_iproc_execute_tuning(struct mmc *mmc, u8 opcode)
  157. {
  158. struct mmc_cmd cmd;
  159. u32 ctrl;
  160. u32 blocksize = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 64);
  161. struct sdhci_host *host = dev_get_priv(mmc->dev);
  162. char tuning_loop_counter = MAX_TUNING_LOOP;
  163. int ret = 0;
  164. sdhci_start_tuning(host);
  165. cmd.cmdidx = opcode;
  166. cmd.resp_type = MMC_RSP_R1;
  167. cmd.cmdarg = 0;
  168. if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200 && mmc->bus_width == 8)
  169. blocksize = SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, 128);
  170. sdhci_writew(host, blocksize, SDHCI_BLOCK_SIZE);
  171. sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
  172. sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
  173. do {
  174. mmc_send_cmd(mmc, &cmd, NULL);
  175. if (opcode == MMC_CMD_SEND_TUNING_BLOCK)
  176. /*
  177. * For tuning command, do not do busy loop. As tuning
  178. * is happening (CLK-DATA latching for setup/hold time
  179. * requirements), give time to complete
  180. */
  181. udelay(1);
  182. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  183. if (tuning_loop_counter-- == 0)
  184. break;
  185. } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
  186. if (tuning_loop_counter < 0 || (!(ctrl & SDHCI_CTRL_TUNED_CLK))) {
  187. ctrl &= ~(SDHCI_CTRL_TUNED_CLK | SDHCI_CTRL_EXEC_TUNING);
  188. sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
  189. printf("%s:Tuning failed, opcode = 0x%02x\n", __func__, opcode);
  190. ret = -EIO;
  191. }
  192. sdhci_end_tuning(host);
  193. return ret;
  194. }
  195. static struct sdhci_ops sdhci_platform_ops = {
  196. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
  197. .read_l = sdhci_iproc_readl,
  198. .read_w = sdhci_iproc_readw,
  199. .read_b = sdhci_iproc_readb,
  200. .write_l = sdhci_iproc_writel,
  201. .write_w = sdhci_iproc_writew,
  202. .write_b = sdhci_iproc_writeb,
  203. #endif
  204. .set_ios_post = sdhci_iproc_set_ios_post,
  205. .platform_execute_tuning = sdhci_iproc_execute_tuning,
  206. };
  207. struct iproc_sdhci_plat {
  208. struct mmc_config cfg;
  209. struct mmc mmc;
  210. };
  211. static int iproc_sdhci_probe(struct udevice *dev)
  212. {
  213. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  214. struct iproc_sdhci_plat *plat = dev_get_plat(dev);
  215. struct sdhci_host *host = dev_get_priv(dev);
  216. struct sdhci_iproc_host *iproc_host;
  217. int node = dev_of_offset(dev);
  218. u32 f_min_max[2];
  219. int ret;
  220. iproc_host = malloc(sizeof(struct sdhci_iproc_host));
  221. if (!iproc_host) {
  222. printf("%s: sdhci host malloc fail!\n", __func__);
  223. return -ENOMEM;
  224. }
  225. iproc_host->shadow_cmd = 0;
  226. iproc_host->shadow_blk = 0;
  227. host->name = dev->name;
  228. host->ioaddr = dev_read_addr_ptr(dev);
  229. host->quirks = SDHCI_QUIRK_BROKEN_R1B;
  230. host->host_caps = MMC_MODE_DDR_52MHz;
  231. host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
  232. host->ops = &sdhci_platform_ops;
  233. host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
  234. ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
  235. "clock-freq-min-max", f_min_max, 2);
  236. if (ret) {
  237. printf("sdhci: clock-freq-min-max not found\n");
  238. free(iproc_host);
  239. return ret;
  240. }
  241. host->max_clk = f_min_max[1];
  242. host->bus_width = fdtdec_get_int(gd->fdt_blob,
  243. dev_of_offset(dev), "bus-width", 4);
  244. /* Update host_caps for 8 bit bus width */
  245. if (host->bus_width == 8)
  246. host->host_caps |= MMC_MODE_8BIT;
  247. memcpy(&iproc_host->host, host, sizeof(struct sdhci_host));
  248. iproc_host->host.mmc = &plat->mmc;
  249. iproc_host->host.mmc->dev = dev;
  250. iproc_host->host.mmc->priv = &iproc_host->host;
  251. upriv->mmc = iproc_host->host.mmc;
  252. ret = sdhci_setup_cfg(&plat->cfg, &iproc_host->host,
  253. f_min_max[1], f_min_max[0]);
  254. if (ret) {
  255. free(iproc_host);
  256. return ret;
  257. }
  258. return sdhci_probe(dev);
  259. }
  260. static int iproc_sdhci_bind(struct udevice *dev)
  261. {
  262. struct iproc_sdhci_plat *plat = dev_get_plat(dev);
  263. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  264. }
  265. static const struct udevice_id iproc_sdhci_ids[] = {
  266. { .compatible = "brcm,iproc-sdhci" },
  267. { }
  268. };
  269. U_BOOT_DRIVER(iproc_sdhci_drv) = {
  270. .name = "iproc_sdhci",
  271. .id = UCLASS_MMC,
  272. .of_match = iproc_sdhci_ids,
  273. .ops = &sdhci_ops,
  274. .bind = iproc_sdhci_bind,
  275. .probe = iproc_sdhci_probe,
  276. .priv_auto = sizeof(struct sdhci_host),
  277. .plat_auto = sizeof(struct iproc_sdhci_plat),
  278. };