socfpga_gen5.c 6.4 KB

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  1. // SPDX-License-Identifier: BSD-3-Clause
  2. /*
  3. * Copyright (C) 2012 Altera Corporation <www.altera.com>
  4. * All rights reserved.
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <linux/errno.h>
  9. #include <asm/arch/fpga_manager.h>
  10. #include <asm/arch/reset_manager.h>
  11. #include <asm/arch/system_manager.h>
  12. #define FPGA_TIMEOUT_CNT 0x1000000
  13. static struct socfpga_fpga_manager *fpgamgr_regs =
  14. (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
  15. /* Set CD ratio */
  16. static void fpgamgr_set_cd_ratio(unsigned long ratio)
  17. {
  18. clrsetbits_le32(&fpgamgr_regs->ctrl,
  19. 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
  20. (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
  21. }
  22. /* Start the FPGA programming by initialize the FPGA Manager */
  23. static int fpgamgr_program_init(void)
  24. {
  25. unsigned long msel, i;
  26. /* Get the MSEL value */
  27. msel = readl(&fpgamgr_regs->stat);
  28. msel &= FPGAMGRREGS_STAT_MSEL_MASK;
  29. msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
  30. /*
  31. * Set the cfg width
  32. * If MSEL[3] = 1, cfg width = 32 bit
  33. */
  34. if (msel & 0x8) {
  35. setbits_le32(&fpgamgr_regs->ctrl,
  36. FPGAMGRREGS_CTRL_CFGWDTH_MASK);
  37. /* To determine the CD ratio */
  38. /* MSEL[1:0] = 0, CD Ratio = 1 */
  39. if ((msel & 0x3) == 0x0)
  40. fpgamgr_set_cd_ratio(CDRATIO_x1);
  41. /* MSEL[1:0] = 1, CD Ratio = 4 */
  42. else if ((msel & 0x3) == 0x1)
  43. fpgamgr_set_cd_ratio(CDRATIO_x4);
  44. /* MSEL[1:0] = 2, CD Ratio = 8 */
  45. else if ((msel & 0x3) == 0x2)
  46. fpgamgr_set_cd_ratio(CDRATIO_x8);
  47. } else { /* MSEL[3] = 0 */
  48. clrbits_le32(&fpgamgr_regs->ctrl,
  49. FPGAMGRREGS_CTRL_CFGWDTH_MASK);
  50. /* To determine the CD ratio */
  51. /* MSEL[1:0] = 0, CD Ratio = 1 */
  52. if ((msel & 0x3) == 0x0)
  53. fpgamgr_set_cd_ratio(CDRATIO_x1);
  54. /* MSEL[1:0] = 1, CD Ratio = 2 */
  55. else if ((msel & 0x3) == 0x1)
  56. fpgamgr_set_cd_ratio(CDRATIO_x2);
  57. /* MSEL[1:0] = 2, CD Ratio = 4 */
  58. else if ((msel & 0x3) == 0x2)
  59. fpgamgr_set_cd_ratio(CDRATIO_x4);
  60. }
  61. /* To enable FPGA Manager configuration */
  62. clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);
  63. /* To enable FPGA Manager drive over configuration line */
  64. setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
  65. /* Put FPGA into reset phase */
  66. setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
  67. /* (1) wait until FPGA enter reset phase */
  68. for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
  69. if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE)
  70. break;
  71. }
  72. /* If not in reset state, return error */
  73. if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
  74. puts("FPGA: Could not reset\n");
  75. return -1;
  76. }
  77. /* Release FPGA from reset phase */
  78. clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
  79. /* (2) wait until FPGA enter configuration phase */
  80. for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
  81. if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE)
  82. break;
  83. }
  84. /* If not in configuration state, return error */
  85. if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
  86. puts("FPGA: Could not configure\n");
  87. return -2;
  88. }
  89. /* Clear all interrupts in CB Monitor */
  90. writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
  91. /* Enable AXI configuration */
  92. setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
  93. return 0;
  94. }
  95. /* Ensure the FPGA entering config done */
  96. static int fpgamgr_program_poll_cd(void)
  97. {
  98. const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
  99. FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK;
  100. unsigned long reg, i;
  101. /* (3) wait until full config done */
  102. for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
  103. reg = readl(&fpgamgr_regs->gpio_ext_porta);
  104. /* Config error */
  105. if (!(reg & mask)) {
  106. printf("FPGA: Configuration error.\n");
  107. return -3;
  108. }
  109. /* Config done without error */
  110. if (reg & mask)
  111. break;
  112. }
  113. /* Timeout happened, return error */
  114. if (i == FPGA_TIMEOUT_CNT) {
  115. printf("FPGA: Timeout waiting for program.\n");
  116. return -4;
  117. }
  118. /* Disable AXI configuration */
  119. clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
  120. return 0;
  121. }
  122. /* Ensure the FPGA entering init phase */
  123. static int fpgamgr_program_poll_initphase(void)
  124. {
  125. unsigned long i;
  126. /* Additional clocks for the CB to enter initialization phase */
  127. if (fpgamgr_dclkcnt_set(0x4))
  128. return -5;
  129. /* (4) wait until FPGA enter init phase or user mode */
  130. for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
  131. if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
  132. break;
  133. if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
  134. break;
  135. }
  136. /* If not in configuration state, return error */
  137. if (i == FPGA_TIMEOUT_CNT)
  138. return -6;
  139. return 0;
  140. }
  141. /* Ensure the FPGA entering user mode */
  142. static int fpgamgr_program_poll_usermode(void)
  143. {
  144. unsigned long i;
  145. /* Additional clocks for the CB to exit initialization phase */
  146. if (fpgamgr_dclkcnt_set(0x5000))
  147. return -7;
  148. /* (5) wait until FPGA enter user mode */
  149. for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
  150. if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
  151. break;
  152. }
  153. /* If not in configuration state, return error */
  154. if (i == FPGA_TIMEOUT_CNT)
  155. return -8;
  156. /* To release FPGA Manager drive over configuration line */
  157. clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
  158. return 0;
  159. }
  160. /*
  161. * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
  162. * Return 0 for sucess, non-zero for error.
  163. */
  164. int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
  165. {
  166. int status;
  167. if ((uint32_t)rbf_data & 0x3) {
  168. puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
  169. return -EINVAL;
  170. }
  171. /* Prior programming the FPGA, all bridges need to be shut off */
  172. /* Disable all signals from hps peripheral controller to fpga */
  173. writel(0, socfpga_get_sysmgr_addr() + SYSMGR_GEN5_FPGAINFGRP_MODULE);
  174. /* Disable all signals from FPGA to HPS SDRAM */
  175. #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
  176. writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
  177. /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
  178. socfpga_bridges_reset(1);
  179. /* Unmap the bridges from NIC-301 */
  180. writel(0x1, SOCFPGA_L3REGS_ADDRESS);
  181. /* Initialize the FPGA Manager */
  182. status = fpgamgr_program_init();
  183. if (status)
  184. return status;
  185. /* Write the RBF data to FPGA Manager */
  186. fpgamgr_program_write(rbf_data, rbf_size);
  187. /* Ensure the FPGA entering config done */
  188. status = fpgamgr_program_poll_cd();
  189. if (status)
  190. return status;
  191. /* Ensure the FPGA entering init phase */
  192. status = fpgamgr_program_poll_initphase();
  193. if (status)
  194. return status;
  195. /* Ensure the FPGA entering user mode */
  196. return fpgamgr_program_poll_usermode();
  197. }