sata_sil.h 6.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. * Author: Tang Yuantian <b29983@freescale.com>
  6. */
  7. #ifndef SATA_SIL3132_H
  8. #define SATA_SIL3132_H
  9. #define READ_CMD 0
  10. #define WRITE_CMD 1
  11. /*
  12. * SATA device driver struct for each dev
  13. */
  14. struct sil_sata {
  15. char name[12];
  16. void *port; /* the port base address */
  17. int lba48;
  18. u16 pio;
  19. u16 mwdma;
  20. u16 udma;
  21. struct udevice *devno;
  22. int wcache;
  23. int flush;
  24. int flush_ext;
  25. int id;
  26. };
  27. /* sata info for each controller */
  28. struct sata_info {
  29. ulong iobase[3];
  30. pci_dev_t devno;
  31. int portbase;
  32. int maxport;
  33. };
  34. /*
  35. * Scatter gather entry (SGE),MUST 8 bytes aligned
  36. */
  37. struct sil_sge {
  38. __le64 addr;
  39. __le32 cnt;
  40. __le32 flags;
  41. } __attribute__ ((aligned(8), packed));
  42. /*
  43. * Port request block, MUST 8 bytes aligned
  44. */
  45. struct sil_prb {
  46. __le16 ctrl;
  47. __le16 prot;
  48. __le32 rx_cnt;
  49. struct sata_fis_h2d fis;
  50. } __attribute__ ((aligned(8), packed));
  51. struct sil_cmd_block {
  52. struct sil_prb prb;
  53. struct sil_sge sge;
  54. };
  55. enum {
  56. HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
  57. HOST_CTRL = 0x40,
  58. HOST_IRQ_STAT = 0x44,
  59. HOST_PHY_CFG = 0x48,
  60. HOST_BIST_CTRL = 0x50,
  61. HOST_BIST_PTRN = 0x54,
  62. HOST_BIST_STAT = 0x58,
  63. HOST_MEM_BIST_STAT = 0x5c,
  64. HOST_FLASH_CMD = 0x70,
  65. /* 8 bit regs */
  66. HOST_FLASH_DATA = 0x74,
  67. HOST_TRANSITION_DETECT = 0x75,
  68. HOST_GPIO_CTRL = 0x76,
  69. HOST_I2C_ADDR = 0x78, /* 32 bit */
  70. HOST_I2C_DATA = 0x7c,
  71. HOST_I2C_XFER_CNT = 0x7e,
  72. HOST_I2C_CTRL = 0x7f,
  73. /* HOST_SLOT_STAT bits */
  74. HOST_SSTAT_ATTN = (1 << 31),
  75. /* HOST_CTRL bits */
  76. HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
  77. HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
  78. HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
  79. HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
  80. HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
  81. HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
  82. /*
  83. * Port registers
  84. * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
  85. */
  86. PORT_REGS_SIZE = 0x2000,
  87. PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
  88. PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
  89. PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
  90. PORT_PMP_STATUS = 0x0000, /* port device status offset */
  91. PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
  92. PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
  93. /* 32 bit regs */
  94. PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
  95. PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
  96. PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
  97. PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
  98. PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
  99. PORT_ACTIVATE_UPPER_ADDR = 0x101c,
  100. PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
  101. PORT_CMD_ERR = 0x1024, /* command error number */
  102. PORT_FIS_CFG = 0x1028,
  103. PORT_FIFO_THRES = 0x102c,
  104. /* 16 bit regs */
  105. PORT_DECODE_ERR_CNT = 0x1040,
  106. PORT_DECODE_ERR_THRESH = 0x1042,
  107. PORT_CRC_ERR_CNT = 0x1044,
  108. PORT_CRC_ERR_THRESH = 0x1046,
  109. PORT_HSHK_ERR_CNT = 0x1048,
  110. PORT_HSHK_ERR_THRESH = 0x104a,
  111. /* 32 bit regs */
  112. PORT_PHY_CFG = 0x1050,
  113. PORT_SLOT_STAT = 0x1800,
  114. PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 */
  115. PORT_CONTEXT = 0x1e04,
  116. PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 */
  117. PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 */
  118. PORT_SCONTROL = 0x1f00,
  119. PORT_SSTATUS = 0x1f04,
  120. PORT_SERROR = 0x1f08,
  121. PORT_SACTIVE = 0x1f0c,
  122. /* PORT_CTRL_STAT bits */
  123. PORT_CS_PORT_RST = (1 << 0), /* port reset */
  124. PORT_CS_DEV_RST = (1 << 1), /* device reset */
  125. PORT_CS_INIT = (1 << 2), /* port initialize */
  126. PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
  127. PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
  128. PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
  129. PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
  130. PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
  131. PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
  132. /* PORT_IRQ_STAT/ENABLE_SET/CLR */
  133. /* bits[11:0] are masked */
  134. PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
  135. PORT_IRQ_ERROR = (1 << 1), /* command execution error */
  136. PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
  137. PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
  138. PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
  139. PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
  140. PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
  141. PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
  142. PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
  143. PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
  144. PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
  145. PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
  146. DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
  147. PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
  148. PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
  149. /* bits[27:16] are unmasked (raw) */
  150. PORT_IRQ_RAW_SHIFT = 16,
  151. PORT_IRQ_MASKED_MASK = 0x7ff,
  152. PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
  153. /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
  154. PORT_IRQ_STEER_SHIFT = 30,
  155. PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
  156. /* PORT_CMD_ERR constants */
  157. PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
  158. PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
  159. PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
  160. PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
  161. PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
  162. PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
  163. PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
  164. PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
  165. /* bits of PRB control field */
  166. PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
  167. PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
  168. PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
  169. PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
  170. PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
  171. /* PRB protocol field */
  172. PRB_PROT_PACKET = (1 << 0),
  173. PRB_PROT_TCQ = (1 << 1),
  174. PRB_PROT_NCQ = (1 << 2),
  175. PRB_PROT_READ = (1 << 3),
  176. PRB_PROT_WRITE = (1 << 4),
  177. PRB_PROT_TRANSPARENT = (1 << 5),
  178. /*
  179. * Other constants
  180. */
  181. SGE_TRM = (1 << 31), /* Last SGE in chain */
  182. SGE_LNK = (1 << 30), /* linked list
  183. Points to SGT, not SGE */
  184. SGE_DRD = (1 << 29), /* discard data read (/dev/null)
  185. data address ignored */
  186. CMD_ERR = 0x21,
  187. };
  188. #if CONFIG_IS_ENABLED(BLK)
  189. #define ATA_MAX_PORTS 32
  190. struct sil_sata_priv {
  191. int port_num;
  192. struct sil_sata *sil_sata_desc[ATA_MAX_PORTS];
  193. };
  194. #endif
  195. #endif