warp.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014, 2015 O.S. Systems Software LTDA.
  4. * Copyright (C) 2014 Kynetics LLC.
  5. * Copyright (C) 2014 Revolution Robotics, Inc.
  6. *
  7. * Author: Otavio Salvador <otavio@ossystems.com.br>
  8. */
  9. #include <init.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/mx6-pins.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/global_data.h>
  16. #include <asm/gpio.h>
  17. #include <asm/mach-imx/iomux-v3.h>
  18. #include <asm/mach-imx/mxc_i2c.h>
  19. #include <asm/io.h>
  20. #include <linux/sizes.h>
  21. #include <common.h>
  22. #include <watchdog.h>
  23. #include <fsl_esdhc_imx.h>
  24. #include <i2c.h>
  25. #include <mmc.h>
  26. #include <usb.h>
  27. #include <power/pmic.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  30. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  31. PAD_CTL_SRE_FAST | PAD_CTL_HYS | \
  32. PAD_CTL_LVE)
  33. #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
  34. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  35. PAD_CTL_SRE_FAST | PAD_CTL_HYS | \
  36. PAD_CTL_LVE)
  37. #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  38. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  39. PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  40. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  41. #define CONFIG_POWER_MAX77696_I2C_ADDR 0x3C
  42. enum {
  43. L01_CNFG1 = 0x43,
  44. L01_CNFG2,
  45. L02_CNFG1,
  46. L02_CNFG2,
  47. L03_CNFG1,
  48. L03_CNFG2,
  49. L04_CNFG1,
  50. L04_CNFG2,
  51. L05_CNFG1,
  52. L05_CNFG2,
  53. L06_CNFG1,
  54. L06_CNFG2,
  55. L07_CNFG1,
  56. L07_CNFG2,
  57. L08_CNFG1,
  58. L08_CNFG2,
  59. L09_CNFG1,
  60. L09_CNFG2,
  61. L10_CNFG1,
  62. L10_CNFG2,
  63. LDO_INT1,
  64. LDO_INT2,
  65. LDO_INT1M,
  66. LDO_INT2M,
  67. LDO_CNFG3,
  68. SW1_CNTRL,
  69. SW2_CNTRL,
  70. SW3_CNTRL,
  71. SW4_CNTRL,
  72. EPDCNFG,
  73. EPDINTS,
  74. EPDINT,
  75. EPDINTM,
  76. EPDVCOM,
  77. EPDVEE,
  78. EPDVNEG,
  79. EPDVPOS,
  80. EPDVDDH,
  81. EPDSEQ,
  82. EPDOKINTS,
  83. CID = 0x9c,
  84. PMIC_NUM_OF_REGS,
  85. };
  86. int dram_init(void)
  87. {
  88. gd->ram_size = imx_ddr_size();
  89. return 0;
  90. }
  91. static void setup_iomux_uart(void)
  92. {
  93. static iomux_v3_cfg_t const uart1_pads[] = {
  94. MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  95. MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  96. };
  97. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  98. }
  99. static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  100. {USDHC2_BASE_ADDR, 0, 0, 0, 1},
  101. };
  102. int board_mmc_getcd(struct mmc *mmc)
  103. {
  104. return 1; /* Assume boot SD always present */
  105. }
  106. int board_mmc_init(struct bd_info *bis)
  107. {
  108. static iomux_v3_cfg_t const usdhc2_pads[] = {
  109. MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  110. MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  111. MX6_PAD_SD2_RST__USDHC2_RST | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  112. MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  113. MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  114. MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  115. MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  116. MX6_PAD_SD2_DAT4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  117. MX6_PAD_SD2_DAT5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  118. MX6_PAD_SD2_DAT6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  119. MX6_PAD_SD2_DAT7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  120. };
  121. imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  122. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  123. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  124. }
  125. int board_usb_phy_mode(int port)
  126. {
  127. return USB_INIT_DEVICE;
  128. }
  129. /* I2C1 for PMIC */
  130. #define I2C_PMIC 0
  131. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  132. struct i2c_pads_info i2c_pad_info1 = {
  133. .sda = {
  134. .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
  135. .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
  136. .gp = IMX_GPIO_NR(3, 13),
  137. },
  138. .scl = {
  139. .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
  140. .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
  141. .gp = IMX_GPIO_NR(3, 12),
  142. },
  143. };
  144. static int power_max77696_init(unsigned char bus)
  145. {
  146. static const char name[] = "MAX77696";
  147. struct pmic *p = pmic_alloc();
  148. if (!p) {
  149. printf("%s: POWER allocation error!\n", __func__);
  150. return -ENOMEM;
  151. }
  152. p->name = name;
  153. p->interface = PMIC_I2C;
  154. p->number_of_regs = PMIC_NUM_OF_REGS;
  155. p->hw.i2c.addr = CONFIG_POWER_MAX77696_I2C_ADDR;
  156. p->hw.i2c.tx_num = 1;
  157. p->bus = bus;
  158. return 0;
  159. }
  160. int power_init_board(void)
  161. {
  162. struct pmic *p;
  163. int ret;
  164. unsigned int reg;
  165. ret = power_max77696_init(I2C_PMIC);
  166. if (ret)
  167. return ret;
  168. p = pmic_get("MAX77696");
  169. if (!p)
  170. return -EINVAL;
  171. ret = pmic_reg_read(p, CID, &reg);
  172. if (ret)
  173. return ret;
  174. printf("PMIC: MAX77696 detected, rev=0x%x\n", reg);
  175. return pmic_probe(p);
  176. }
  177. int board_early_init_f(void)
  178. {
  179. setup_iomux_uart();
  180. return 0;
  181. }
  182. int board_init(void)
  183. {
  184. /* address of boot parameters */
  185. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  186. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  187. return 0;
  188. }
  189. int board_late_init(void)
  190. {
  191. #ifdef CONFIG_HW_WATCHDOG
  192. hw_watchdog_init();
  193. #endif
  194. return 0;
  195. }
  196. int checkboard(void)
  197. {
  198. puts("Board: WaRP Board\n");
  199. return 0;
  200. }