o2dnt2.c 9.4 KB

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  1. /*
  2. * Partially derived from board code for digsyMTC,
  3. * (C) Copyright 2009
  4. * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
  5. *
  6. * (C) Copyright 2012
  7. * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #include <common.h>
  12. #include <mpc5xxx.h>
  13. #include <asm/processor.h>
  14. #include <asm/io.h>
  15. #include <libfdt.h>
  16. #include <fdt_support.h>
  17. #include <i2c.h>
  18. #include <miiphy.h>
  19. #include <net.h>
  20. #include <pci.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #define SDRAM_MODE 0x00CD0000
  23. #define SDRAM_CONTROL 0x504F0000
  24. #define SDRAM_CONFIG1 0xD2322800
  25. #define SDRAM_CONFIG2 0x8AD70000
  26. enum ifm_sensor_type {
  27. O2DNT = 0x00, /* !< O2DNT 32MB */
  28. O2DNT2 = 0x01, /* !< O2DNT2 64MB */
  29. O3DNT = 0x02, /* !< O3DNT 32MB */
  30. O3DNT_MIN = 0x40, /* !< O3DNT Minerva 32MB */
  31. UNKNOWN = 0xff, /* !< Unknow sensor */
  32. };
  33. static enum ifm_sensor_type gt_ifm_sensor_type;
  34. #ifndef CONFIG_SYS_RAMBOOT
  35. static void sdram_start(int hi_addr)
  36. {
  37. struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
  38. long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  39. long control = SDRAM_CONTROL | hi_addr_bit;
  40. /* unlock mode register */
  41. out_be32(&sdram->ctrl, control | 0x80000000);
  42. /* precharge all banks */
  43. out_be32(&sdram->ctrl, control | 0x80000002);
  44. /* auto refresh */
  45. out_be32(&sdram->ctrl, control | 0x80000004);
  46. /* set mode register */
  47. out_be32(&sdram->mode, SDRAM_MODE);
  48. /* normal operation */
  49. out_be32(&sdram->ctrl, control);
  50. }
  51. #endif
  52. /*
  53. * ATTENTION: Although partially referenced dram_init does NOT make real use
  54. * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
  55. * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
  56. */
  57. int dram_init(void)
  58. {
  59. struct mpc5xxx_mmap_ctl *mmap_ctl =
  60. (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
  61. struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
  62. ulong dramsize = 0;
  63. ulong dramsize2 = 0;
  64. uint svr, pvr;
  65. if (gt_ifm_sensor_type == O2DNT2) {
  66. /* activate SDRAM CS1 */
  67. setbits_be32((void *)MPC5XXX_GPS_PORT_CONFIG, 0x80000000);
  68. }
  69. #ifndef CONFIG_SYS_RAMBOOT
  70. ulong test1, test2;
  71. /* setup SDRAM chip selects */
  72. out_be32(&mmap_ctl->sdram0, 0x0000001E); /* 2 GB at 0x0 */
  73. out_be32(&mmap_ctl->sdram1, 0x00000000); /* disabled */
  74. /* setup config registers */
  75. out_be32(&sdram->config1, SDRAM_CONFIG1);
  76. out_be32(&sdram->config2, SDRAM_CONFIG2);
  77. /* find RAM size using SDRAM CS0 only */
  78. sdram_start(0);
  79. test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
  80. sdram_start(1);
  81. test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
  82. if (test1 > test2) {
  83. sdram_start(0);
  84. dramsize = test1;
  85. } else {
  86. dramsize = test2;
  87. }
  88. /* memory smaller than 1MB is impossible */
  89. if (dramsize < (1 << 20))
  90. dramsize = 0;
  91. /* set SDRAM CS0 size according to the amount of RAM found */
  92. if (dramsize > 0) {
  93. out_be32(&mmap_ctl->sdram0,
  94. (0x13 + __builtin_ffs(dramsize >> 20) - 1));
  95. } else {
  96. out_be32(&mmap_ctl->sdram0, 0); /* disabled */
  97. }
  98. /* let SDRAM CS1 start right after CS0 */
  99. out_be32(&mmap_ctl->sdram1, dramsize + 0x0000001E); /* 2G */
  100. /* find RAM size using SDRAM CS1 only */
  101. if (!dramsize)
  102. sdram_start(0);
  103. test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
  104. 0x80000000);
  105. if (!dramsize) {
  106. sdram_start(1);
  107. test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
  108. 0x80000000);
  109. }
  110. if (test1 > test2) {
  111. sdram_start(0);
  112. dramsize2 = test1;
  113. } else {
  114. dramsize2 = test2;
  115. }
  116. /* memory smaller than 1MB is impossible */
  117. if (dramsize2 < (1 << 20))
  118. dramsize2 = 0;
  119. /* set SDRAM CS1 size according to the amount of RAM found */
  120. if (dramsize2 > 0) {
  121. out_be32(&mmap_ctl->sdram1, (dramsize |
  122. (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
  123. } else {
  124. out_be32(&mmap_ctl->sdram1, dramsize); /* disabled */
  125. }
  126. #else /* CONFIG_SYS_RAMBOOT */
  127. /* retrieve size of memory connected to SDRAM CS0 */
  128. dramsize = in_be32(&mmap_ctl->sdram0) & 0xFF;
  129. if (dramsize >= 0x13)
  130. dramsize = (1 << (dramsize - 0x13)) << 20;
  131. else
  132. dramsize = 0;
  133. /* retrieve size of memory connected to SDRAM CS1 */
  134. dramsize2 = in_be32(&mmap_ctl->sdram1) & 0xFF;
  135. if (dramsize2 >= 0x13)
  136. dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
  137. else
  138. dramsize2 = 0;
  139. #endif /* CONFIG_SYS_RAMBOOT */
  140. /*
  141. * On MPC5200B we need to set the special configuration delay in the
  142. * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
  143. * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
  144. *
  145. * "The SDelay should be written to a value of 0x00000004. It is
  146. * required to account for changes caused by normal wafer processing
  147. * parameters."
  148. */
  149. svr = get_svr();
  150. pvr = get_pvr();
  151. if ((SVR_MJREV(svr) >= 2) &&
  152. (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
  153. out_be32(&sdram->sdelay, 0x04);
  154. gd->ram_size = dramsize + dramsize2;
  155. return 0;
  156. }
  157. #define GPT_GPIO_IN 0x4
  158. int checkboard(void)
  159. {
  160. struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
  161. unsigned char board_config = 0;
  162. int i;
  163. /* switch gpt0 - gpt7 to input */
  164. for (i = 0; i < 7; i++)
  165. out_be32(&gpt[i].emsr, GPT_GPIO_IN);
  166. /* get configuration byte on timer-port */
  167. for (i = 0; i < 7; i++)
  168. board_config |= (in_be32(&gpt[i].sr) & 0x100) >> (8 - i);
  169. puts("Board: ");
  170. switch (board_config) {
  171. case 0:
  172. puts("O2DNT\n");
  173. gt_ifm_sensor_type = O2DNT;
  174. break;
  175. case 1:
  176. puts("O3DNT\n");
  177. gt_ifm_sensor_type = O3DNT;
  178. break;
  179. case 2:
  180. puts("O2DNT2\n");
  181. gt_ifm_sensor_type = O2DNT2;
  182. break;
  183. case 64:
  184. puts("O3DNT Minerva\n");
  185. gt_ifm_sensor_type = O3DNT_MIN;
  186. break;
  187. default:
  188. puts("Unknown\n");
  189. gt_ifm_sensor_type = UNKNOWN;
  190. break;
  191. }
  192. return 0;
  193. }
  194. int board_early_init_r(void)
  195. {
  196. struct mpc5xxx_lpb *lpb_regs = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
  197. /*
  198. * Now, when we are in RAM, enable flash write access for detection
  199. * process. Note that CS_BOOT cannot be cleared when executing in flash.
  200. */
  201. clrbits_be32(&lpb_regs->cs0_cfg, 1); /* clear RO */
  202. /* disable CS_BOOT */
  203. clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
  204. /* enable CS0 */
  205. setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
  206. return 0;
  207. }
  208. #define MIIM_LXT971_LED_CFG_REG 0x14
  209. #define LXT971_LED_CFG_LINK_STATUS 0x4000
  210. #define LXT971_LED_CFG_RX_TX_ACTIVITY 0x0700
  211. #define LXT971_LED_CFG_LINK_ACTIVITY 0x00D0
  212. #define LXT971_LED_CFG_PULSE_STRETCH 0x0002
  213. /*
  214. * Additional PHY intialization after reset in mpc5xxx_fec_init_phy()
  215. */
  216. void reset_phy(void)
  217. {
  218. /*
  219. * Set LED configuration bits.
  220. * It can't be done in misc_init_r() since FEC is not
  221. * initialized at this time. Therefore we do it here.
  222. */
  223. miiphy_write("FEC", CONFIG_PHY_ADDR, MIIM_LXT971_LED_CFG_REG,
  224. LXT971_LED_CFG_LINK_STATUS |
  225. LXT971_LED_CFG_RX_TX_ACTIVITY |
  226. LXT971_LED_CFG_LINK_ACTIVITY |
  227. LXT971_LED_CFG_PULSE_STRETCH);
  228. }
  229. #if defined(CONFIG_POST)
  230. /*
  231. * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
  232. * is left open, no keypress is detected.
  233. */
  234. int post_hotkeys_pressed(void)
  235. {
  236. struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
  237. /*
  238. * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
  239. * CODEC or UART mode. Consumer IrDA should still be possible.
  240. */
  241. clrbits_be32(&gpio->port_config, 0x07000000);
  242. setbits_be32(&gpio->port_config, 0x03000000);
  243. /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
  244. setbits_be32(&gpio->simple_gpioe, 0x20000000);
  245. /* Configure GPIO_IRDA_1 as input */
  246. clrbits_be32(&gpio->simple_ddr, 0x20000000);
  247. return (in_be32(&gpio->simple_ival) & 0x20000000) ? 0 : 1;
  248. }
  249. #endif
  250. #ifdef CONFIG_PCI
  251. static struct pci_controller hose;
  252. void pci_init_board(void)
  253. {
  254. pci_mpc5xxx_init(&hose);
  255. }
  256. #endif
  257. #ifdef CONFIG_OF_BOARD_SETUP
  258. #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
  259. static void ft_adapt_flash_base(void *blob)
  260. {
  261. flash_info_t *dev = &flash_info[0];
  262. int off;
  263. struct fdt_property *prop;
  264. int len;
  265. u32 *reg, *reg2;
  266. off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
  267. if (off < 0) {
  268. printf("Could not find fsl,mpc5200b-lpb node.\n");
  269. return;
  270. }
  271. /* found compatible property */
  272. prop = fdt_get_property_w(blob, off, "ranges", &len);
  273. if (prop) {
  274. reg = reg2 = (u32 *)&prop->data[0];
  275. reg[2] = dev->start[0];
  276. reg[3] = dev->size;
  277. fdt_setprop(blob, off, "ranges", reg2, len);
  278. } else
  279. printf("Could not find ranges\n");
  280. }
  281. extern ulong flash_get_size(phys_addr_t base, int banknum);
  282. /* Update the flash baseaddr settings */
  283. int update_flash_size(int flash_size)
  284. {
  285. struct mpc5xxx_mmap_ctl *mm =
  286. (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
  287. flash_info_t *dev;
  288. int i;
  289. int size = 0;
  290. unsigned long base = 0x0;
  291. u32 *cs_reg = (u32 *)&mm->cs0_start;
  292. for (i = 0; i < 2; i++) {
  293. dev = &flash_info[i];
  294. if (dev->size) {
  295. /* calculate new base addr for this chipselect */
  296. base -= dev->size;
  297. out_be32(cs_reg, START_REG(base));
  298. cs_reg++;
  299. out_be32(cs_reg, STOP_REG(base, dev->size));
  300. cs_reg++;
  301. /* recalculate the sectoraddr in the cfi driver */
  302. size += flash_get_size(base, i);
  303. }
  304. }
  305. flash_protect_default();
  306. gd->bd->bi_flashstart = base;
  307. return 0;
  308. }
  309. #endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
  310. int ft_board_setup(void *blob, bd_t *bd)
  311. {
  312. int phy_addr = CONFIG_PHY_ADDR;
  313. char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
  314. ft_cpu_setup(blob, bd);
  315. #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
  316. #ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
  317. /* Update reg property in all nor flash nodes too */
  318. fdt_fixup_nor_flash_size(blob);
  319. #endif
  320. ft_adapt_flash_base(blob);
  321. #endif
  322. /* fix up the phy address */
  323. do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
  324. return 0;
  325. }
  326. #endif /* CONFIG_OF_BOARD_SETUP */