mpc5121ads.c 6.7 KB

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  1. /*
  2. * (C) Copyright 2007-2009 DENX Software Engineering
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/bitops.h>
  8. #include <command.h>
  9. #include <asm/io.h>
  10. #include <asm/processor.h>
  11. #include <asm/mpc512x.h>
  12. #include <fdt_support.h>
  13. #ifdef CONFIG_MISC_INIT_R
  14. #include <i2c.h>
  15. #endif
  16. #include <net.h>
  17. #include <linux/mtd/mtd.h>
  18. #include <linux/mtd/nand.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
  21. /* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
  22. extern int mpc5121_nfc_chip;
  23. /* Control chips select signal on MPC5121ADS board */
  24. void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
  25. {
  26. unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
  27. u8 v;
  28. v = in_8(csreg);
  29. v |= 0x0F;
  30. if (chip >= 0) {
  31. __mpc5121_nfc_select_chip(mtd, 0);
  32. v &= ~(1 << mpc5121_nfc_chip);
  33. } else {
  34. __mpc5121_nfc_select_chip(mtd, -1);
  35. }
  36. out_8(csreg, v);
  37. }
  38. int board_early_init_f(void)
  39. {
  40. /*
  41. * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
  42. *
  43. * Without this the flash identification routine fails, as it needs to issue
  44. * write commands in order to establish the device ID.
  45. */
  46. #ifdef CONFIG_MPC5121ADS_REV2
  47. out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
  48. #else
  49. if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
  50. out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
  51. } else {
  52. /* running from Backup flash */
  53. out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
  54. }
  55. #endif
  56. return 0;
  57. }
  58. int is_micron(void){
  59. ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
  60. uchar macaddr[6];
  61. u32 brddate, macchk, ismicron;
  62. /*
  63. * MAC address has serial number with date of manufacture
  64. * Boards made before Nov-08 #1180 use Micron memory;
  65. * 001e59 is the STx vendor #
  66. * Default is Elpida since it works for both but is slightly slower
  67. */
  68. ismicron = 0;
  69. if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
  70. brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
  71. macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
  72. debug("brddate = %d\n\t", brddate);
  73. if (macchk == 0x001e59 && brddate <= 8111180)
  74. ismicron = 1;
  75. } else if (brd_rev < 0x400) {
  76. ismicron = 1;
  77. }
  78. debug("Using %s Memory settings\n\t",
  79. ismicron ? "Micron" : "Elpida");
  80. return(ismicron);
  81. }
  82. int dram_init(void)
  83. {
  84. u32 msize = 0;
  85. /*
  86. * Elpida MDDRC and initialization settings are an alternative
  87. * to the Default Micron ones for all but the earliest Rev 4 boards
  88. */
  89. ddr512x_config_t elpida_mddrc_config = {
  90. .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
  91. .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
  92. .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
  93. .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
  94. };
  95. u32 elpida_init_sequence[] = {
  96. CONFIG_SYS_DDRCMD_NOP,
  97. CONFIG_SYS_DDRCMD_NOP,
  98. CONFIG_SYS_DDRCMD_NOP,
  99. CONFIG_SYS_DDRCMD_NOP,
  100. CONFIG_SYS_DDRCMD_NOP,
  101. CONFIG_SYS_DDRCMD_NOP,
  102. CONFIG_SYS_DDRCMD_NOP,
  103. CONFIG_SYS_DDRCMD_NOP,
  104. CONFIG_SYS_DDRCMD_NOP,
  105. CONFIG_SYS_DDRCMD_NOP,
  106. CONFIG_SYS_DDRCMD_PCHG_ALL,
  107. CONFIG_SYS_DDRCMD_NOP,
  108. CONFIG_SYS_DDRCMD_RFSH,
  109. CONFIG_SYS_DDRCMD_NOP,
  110. CONFIG_SYS_DDRCMD_RFSH,
  111. CONFIG_SYS_DDRCMD_NOP,
  112. CONFIG_SYS_DDRCMD_EM2,
  113. CONFIG_SYS_DDRCMD_EM3,
  114. CONFIG_SYS_DDRCMD_EN_DLL,
  115. CONFIG_SYS_ELPIDA_RES_DLL,
  116. CONFIG_SYS_DDRCMD_PCHG_ALL,
  117. CONFIG_SYS_DDRCMD_RFSH,
  118. CONFIG_SYS_DDRCMD_RFSH,
  119. CONFIG_SYS_DDRCMD_RFSH,
  120. CONFIG_SYS_ELPIDA_INIT_DEV_OP,
  121. CONFIG_SYS_DDRCMD_NOP,
  122. CONFIG_SYS_DDRCMD_NOP,
  123. CONFIG_SYS_DDRCMD_NOP,
  124. CONFIG_SYS_DDRCMD_NOP,
  125. CONFIG_SYS_DDRCMD_NOP,
  126. CONFIG_SYS_DDRCMD_NOP,
  127. CONFIG_SYS_DDRCMD_NOP,
  128. CONFIG_SYS_DDRCMD_NOP,
  129. CONFIG_SYS_DDRCMD_NOP,
  130. CONFIG_SYS_DDRCMD_NOP,
  131. CONFIG_SYS_DDRCMD_OCD_DEFAULT,
  132. CONFIG_SYS_ELPIDA_OCD_EXIT,
  133. CONFIG_SYS_DDRCMD_NOP,
  134. CONFIG_SYS_DDRCMD_NOP,
  135. CONFIG_SYS_DDRCMD_NOP,
  136. CONFIG_SYS_DDRCMD_NOP,
  137. CONFIG_SYS_DDRCMD_NOP,
  138. CONFIG_SYS_DDRCMD_NOP,
  139. CONFIG_SYS_DDRCMD_NOP,
  140. CONFIG_SYS_DDRCMD_NOP,
  141. CONFIG_SYS_DDRCMD_NOP,
  142. CONFIG_SYS_DDRCMD_NOP
  143. };
  144. if (is_micron()) {
  145. msize = fixed_sdram(NULL, NULL, 0);
  146. } else {
  147. msize = fixed_sdram(&elpida_mddrc_config,
  148. elpida_init_sequence,
  149. sizeof(elpida_init_sequence)/sizeof(u32));
  150. }
  151. gd->ram_size = msize;
  152. return 0;
  153. }
  154. int misc_init_r(void)
  155. {
  156. return 0;
  157. }
  158. static iopin_t ioregs_init[] = {
  159. /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
  160. {
  161. offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
  162. IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  163. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  164. },
  165. /* Set highest Slew on 9 PATA pins */
  166. {
  167. offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
  168. IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  169. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  170. },
  171. /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
  172. {
  173. offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
  174. IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  175. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  176. },
  177. /* FUNC1=SPDIF_TXCLK */
  178. {
  179. offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
  180. IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  181. IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
  182. },
  183. /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
  184. {
  185. offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
  186. IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  187. IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
  188. },
  189. /* FUNC2=DIU CLK */
  190. {
  191. offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
  192. IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  193. IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
  194. },
  195. /* FUNC2=DIU_HSYNC */
  196. {
  197. offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
  198. IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  199. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  200. },
  201. /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
  202. {
  203. offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
  204. IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  205. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  206. }
  207. };
  208. static iopin_t rev2_silicon_pci_ioregs_init[] = {
  209. /* FUNC0=PCI Sets next 54 to PCI pads */
  210. {
  211. offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
  212. IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
  213. }
  214. };
  215. int checkboard (void)
  216. {
  217. ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
  218. uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
  219. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  220. u32 spridr = in_be32(&im->sysconf.spridr);
  221. printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
  222. brd_rev, cpld_rev);
  223. /* initialize function mux & slew rate IO inter alia on IO Pins */
  224. iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
  225. if (SVR_MJREV (spridr) >= 2)
  226. iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
  227. return 0;
  228. }
  229. #ifdef CONFIG_OF_BOARD_SETUP
  230. int ft_board_setup(void *blob, bd_t *bd)
  231. {
  232. ft_cpu_setup(blob, bd);
  233. return 0;
  234. }
  235. #endif /* CONFIG_OF_BOARD_SETUP */