mecp5123.c 4.9 KB

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  1. /*
  2. * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
  3. * (C) Copyright 2009 Dave Srl www.dave.eu
  4. * (C) Copyright 2009 Stefan Roese <sr@denx.de>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <common.h>
  9. #include <asm/bitops.h>
  10. #include <command.h>
  11. #include <asm/io.h>
  12. #include <asm/processor.h>
  13. #include <asm/mpc512x.h>
  14. #include <fdt_support.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. int eeprom_write_enable(unsigned dev_addr, int state)
  17. {
  18. return -ENOSYS;
  19. }
  20. int board_early_init_f(void)
  21. {
  22. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  23. int i;
  24. /*
  25. * Initialize Local Window for boot access
  26. */
  27. out_be32(&im->sysconf.lpbaw,
  28. CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
  29. sync_law(&im->sysconf.lpbaw);
  30. /*
  31. * Configure MSCAN clocks
  32. */
  33. for (i=0; i<4; ++i) {
  34. out_be32(&im->clk.msccr[i], 0x00300000);
  35. out_be32(&im->clk.msccr[i], 0x00310000);
  36. }
  37. /*
  38. * Configure GPIO's
  39. */
  40. clrbits_be32(&im->gpio.gpodr, 0x000000e0);
  41. clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
  42. setbits_be32(&im->gpio.gpdir, 0x001000e0);
  43. setbits_be32(&im->gpio.gpdat, 0x00100000);
  44. return 0;
  45. }
  46. int dram_init(void)
  47. {
  48. gd->ram_size = get_ram_size(0, fixed_sdram(NULL, NULL, 0));
  49. return 0;
  50. }
  51. int misc_init_r(void)
  52. {
  53. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  54. u32 val;
  55. /*
  56. * Optimize access to profibus chip (VPC3) on the local bus
  57. */
  58. /*
  59. * Select 1:1 for LPC_DIV
  60. */
  61. val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK;
  62. out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT));
  63. /*
  64. * Configure LPC Chips Select Deadcycle Control Register
  65. * CS0 - device can drive data 2 clock cycle(s) after CS deassertion
  66. * CS1 - device can drive data 1 clock cycle(s) after CS deassertion
  67. */
  68. clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
  69. setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
  70. /*
  71. * Configure LPC Chips Select Holdcycle Control Register
  72. * CS0 - data is valid 2 clock cycle(s) after CS deassertion
  73. * CS1 - data is valid 1 clock cycle(s) after CS deassertion
  74. */
  75. clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
  76. setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
  77. return 0;
  78. }
  79. static iopin_t ioregs_init[] = {
  80. /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
  81. {
  82. offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
  83. IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  84. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  85. },
  86. /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
  87. {
  88. offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
  89. IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  90. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  91. },
  92. /* FUNC1=SELECT LPC_CS1 */
  93. {
  94. offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
  95. IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  96. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  97. },
  98. /* FUNC3=SELECT PSC5_2 */
  99. {
  100. offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
  101. IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  102. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  103. },
  104. /* FUNC3=SELECT PSC5_3 */
  105. {
  106. offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
  107. IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  108. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  109. },
  110. /* FUNC3=SELECT PSC7_3 */
  111. {
  112. offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
  113. IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  114. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  115. },
  116. /* FUNC3=SELECT PSC9_0 */
  117. {
  118. offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
  119. IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  120. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  121. },
  122. /* FUNC3=SELECT PSC10_0 */
  123. {
  124. offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
  125. IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  126. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  127. },
  128. /* FUNC3=SELECT PSC10_3 */
  129. {
  130. offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
  131. IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  132. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  133. },
  134. /* FUNC3=SELECT PSC11_0 */
  135. {
  136. offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
  137. IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  138. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  139. },
  140. /* FUNC0=SELECT IRQ0 */
  141. {
  142. offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
  143. IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
  144. IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
  145. }
  146. };
  147. static iopin_t rev2_silicon_pci_ioregs_init[] = {
  148. /* FUNC0=PCI Sets next 54 to PCI pads */
  149. {
  150. offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
  151. IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
  152. }
  153. };
  154. int checkboard(void)
  155. {
  156. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  157. u32 spridr;
  158. puts("Board: MECP_5123\n");
  159. /*
  160. * Initialize function mux & slew rate IO inter alia on IO
  161. * Pins
  162. */
  163. iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
  164. spridr = in_be32(&im->sysconf.spridr);
  165. if (SVR_MJREV(spridr) >= 2)
  166. iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
  167. return 0;
  168. }
  169. #ifdef CONFIG_OF_BOARD_SETUP
  170. int ft_board_setup(void *blob, bd_t *bd)
  171. {
  172. ft_cpu_setup(blob, bd);
  173. return 0;
  174. }
  175. #endif /* CONFIG_OF_BOARD_SETUP */