cm5200.h 3.7 KB

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  1. /*
  2. * (C) Copyright 2007 DENX Software Engineering
  3. *
  4. * Author: Bartlomiej Sieka <tur@semihalf.com>
  5. * Author: Grzegorz Bernacki <gjb@semihalf.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #ifndef _CM5200_H
  10. #define _CM5200_H
  11. /*
  12. * Definitions and declarations for the modules of the cm5200 platform. Mostly
  13. * related to reading the hardware identification data (HW ID) from the I2C
  14. * EEPROM, detection of the particular module we are executing on, and
  15. * appropriate SDRAM controller initialization.
  16. */
  17. #define CM5200_UNKNOWN_MODULE 0xffffffff
  18. enum {
  19. DEVICE_NAME, /* 0 */
  20. GENERATION, /* 1 */
  21. PCB_NAME, /* 2 */
  22. FORM, /* 3 */
  23. VERSION, /* 4 */
  24. IDENTIFICATION_NUMBER, /* 5 */
  25. MAJOR_SW_VERSION, /* 6 */
  26. MINOR_SW_VERSION, /* 7 */
  27. /* add new alements above this line */
  28. HW_ID_ELEM_COUNT /* count */
  29. };
  30. /*
  31. * Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition"
  32. */
  33. #define DEVICE_NAME_OFFSET 0x02
  34. #define GENERATION_OFFSET 0x0b
  35. #define PCB_NAME_OFFSET 0x0c
  36. #define FORM_OFFSET 0x15
  37. #define VERSION_OFFSET 0x16
  38. #define IDENTIFICATION_NUMBER_OFFSET 0x19
  39. #define MAJOR_SW_VERSION_OFFSET 0x0480
  40. #define MINOR_SW_VERSION_OFFSET 0x0481
  41. #define DEVICE_NAME_LEN 0x09
  42. #define GENERATION_LEN 0x01
  43. #define PCB_NAME_LEN 0x09
  44. #define FORM_LEN 0x01
  45. #define VERSION_LEN 0x03
  46. #define IDENTIFICATION_NUMBER_LEN 0x09
  47. #define MAJOR_SW_VERSION_LEN 0x01
  48. #define MINOR_SW_VERSION_LEN 0x01
  49. #define HW_ID_ELEM_MAXLEN 0x09 /* MAX(XXX_LEN) */
  50. /* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */
  51. #define MODULE_NAME_MAXLEN 64
  52. /* storage for HW ID read from EEPROM */
  53. typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN];
  54. /* HW ID layout in EEPROM */
  55. static struct {
  56. unsigned int offset;
  57. unsigned int length;
  58. } hw_id_format[HW_ID_ELEM_COUNT] = {
  59. {DEVICE_NAME_OFFSET, DEVICE_NAME_LEN},
  60. {GENERATION_OFFSET, GENERATION_LEN},
  61. {PCB_NAME_OFFSET, PCB_NAME_LEN},
  62. {FORM_OFFSET, FORM_LEN},
  63. {VERSION_OFFSET, VERSION_LEN},
  64. {IDENTIFICATION_NUMBER_OFFSET, IDENTIFICATION_NUMBER_LEN},
  65. {MAJOR_SW_VERSION_OFFSET, MAJOR_SW_VERSION_LEN},
  66. {MINOR_SW_VERSION_OFFSET, MINOR_SW_VERSION_LEN},
  67. };
  68. /* HW ID data found in EEPROM on supported modules */
  69. static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = {
  70. "CM", /* DEVICE_NAME */
  71. "1", /* GENERATION */
  72. "CM1", /* PCB_NAME */
  73. "Q", /* FORM */
  74. "A", /* VERSION */
  75. "591881", /* IDENTIFICATION_NUMBER */
  76. "", /* MAJOR_SW_VERSION */
  77. "", /* MINOR_SW_VERSION */
  78. };
  79. static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = {
  80. "CM", /* DEVICE_NAME */
  81. "1", /* GENERATION */
  82. "CM11", /* PCB_NAME */
  83. "Q", /* FORM */
  84. "A", /* VERSION */
  85. "594200", /* IDENTIFICATION_NUMBER */
  86. "", /* MAJOR_SW_VERSION */
  87. "", /* MINOR_SW_VERSION */
  88. };
  89. static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = {
  90. "CMU", /* DEVICE_NAME */
  91. "1", /* GENERATION */
  92. "CMU1", /* PCB_NAME */
  93. "Q", /* FORM */
  94. "A", /* VERSION */
  95. "594128", /* IDENTIFICATION_NUMBER */
  96. "", /* MAJOR_SW_VERSION */
  97. "", /* MINOR_SW_VERSION */
  98. };
  99. /* list of known modules */
  100. static char **hw_id_list[] = {
  101. cm1_qa_hw_id,
  102. cm11_qa_hw_id,
  103. cmu1_qa_hw_id,
  104. };
  105. /* indices to the above list - keep in sync */
  106. enum {
  107. CM1_QA,
  108. CM11_QA,
  109. CMU1_QA,
  110. };
  111. /* identify modules based on these hw id elements */
  112. static int hw_id_identify[] = {
  113. PCB_NAME,
  114. FORM,
  115. VERSION,
  116. };
  117. /* Registers' settings for SDRAM controller intialization */
  118. typedef struct {
  119. ulong mode;
  120. ulong control;
  121. ulong config1;
  122. ulong config2;
  123. } mem_conf_t;
  124. static mem_conf_t k4s561632E = {
  125. 0x00CD0000, /* CASL 3, burst length 8 */
  126. 0x514F0000,
  127. 0xE2333900,
  128. 0x8EE70000
  129. };
  130. static mem_conf_t mt48lc32m16a2 = {
  131. 0x00CD0000, /* CASL 3, burst length 8 */
  132. 0x514F0000,
  133. 0xD2322800,
  134. 0x8AD70000
  135. };
  136. static mem_conf_t* memory_config[] = {
  137. &k4s561632E,
  138. &mt48lc32m16a2
  139. };
  140. #endif /* _CM5200_H */