mt48lc16m32s2-75.h 332 B

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  1. /*
  2. * (C) Copyright 2004
  3. * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #define SDRAM_DDR 0 /* is SDR */
  8. /* Settings for XLB = 132 MHz */
  9. #define SDRAM_MODE 0x00CD0000
  10. #define SDRAM_CONTROL 0x504F0000
  11. #define SDRAM_CONFIG1 0xD2322800
  12. #define SDRAM_CONFIG2 0x8AD70000