immap_512x.h 40 KB

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  1. /*
  2. * (C) Copyright 2007-2009 DENX Software Engineering
  3. *
  4. * MPC512x Internal Memory Map
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. *
  8. * Based on the MPC83xx header.
  9. */
  10. #ifndef __IMMAP_512x__
  11. #define __IMMAP_512x__
  12. #include <asm/types.h>
  13. #if defined(CONFIG_E300)
  14. #include <asm/e300.h>
  15. #endif
  16. /*
  17. * System reset offset (PowerPC standard)
  18. */
  19. #define EXC_OFF_SYS_RESET 0x0100
  20. #define _START_OFFSET EXC_OFF_SYS_RESET
  21. #define SPR_5121E 0x80180000
  22. /*
  23. * IMMRBAR - Internal Memory Register Base Address
  24. */
  25. #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */
  26. #define IMMRBAR 0x0000 /* Register offset to immr */
  27. #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */
  28. #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
  29. #ifndef __ASSEMBLY__
  30. typedef struct law512x {
  31. u32 bar; /* Base Addr Register */
  32. u32 ar; /* Attributes Register */
  33. } law512x_t;
  34. /*
  35. * System configuration registers
  36. */
  37. typedef struct sysconf512x {
  38. u32 immrbar; /* Internal memory map base address register */
  39. u8 res0[0x1c];
  40. u32 lpbaw; /* LP Boot Access Window */
  41. u32 lpcs0aw; /* LP CS0 Access Window */
  42. u32 lpcs1aw; /* LP CS1 Access Window */
  43. u32 lpcs2aw; /* LP CS2 Access Window */
  44. u32 lpcs3aw; /* LP CS3 Access Window */
  45. u32 lpcs4aw; /* LP CS4 Access Window */
  46. u32 lpcs5aw; /* LP CS5 Access Window */
  47. u32 lpcs6aw; /* LP CS6 Access Window */
  48. u32 lpcs7aw; /* LP CS7 Access Window */
  49. u8 res1[0x1c];
  50. law512x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */
  51. u8 res2[0x28];
  52. law512x_t ddrlaw; /* DDR Local Access Window */
  53. u8 res3[0x18];
  54. u32 mbxbar; /* MBX Base Address */
  55. u32 srambar; /* SRAM Base Address */
  56. u32 nfcbar; /* NFC Base Address */
  57. u8 res4[0x34];
  58. u32 spridr; /* System Part and Revision ID Register */
  59. u32 spcr; /* System Priority Configuration Register */
  60. u8 res5[0xf8];
  61. } sysconf512x_t;
  62. #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */
  63. /*
  64. * Watch Dog Timer (WDT) Registers
  65. */
  66. typedef struct wdt512x {
  67. u8 res0[4];
  68. u32 swcrr; /* System watchdog control register */
  69. u32 swcnr; /* System watchdog count register */
  70. u8 res1[2];
  71. u16 swsrr; /* System watchdog service register */
  72. u8 res2[0xF0];
  73. } wdt512x_t;
  74. /*
  75. * RTC Module Registers
  76. */
  77. typedef struct rtclk512x {
  78. u8 fixme[0x100];
  79. } rtclk512x_t;
  80. /*
  81. * General Purpose Timer
  82. */
  83. typedef struct gpt512x {
  84. u8 fixme[0x100];
  85. } gpt512x_t;
  86. /*
  87. * Integrated Programmable Interrupt Controller
  88. */
  89. typedef struct ipic512x {
  90. u8 fixme[0x100];
  91. } ipic512x_t;
  92. /*
  93. * System Arbiter Registers
  94. */
  95. typedef struct arbiter512x {
  96. u32 acr; /* Arbiter Configuration Register */
  97. u32 atr; /* Arbiter Timers Register */
  98. u32 ater; /* Arbiter Transfer Error Register */
  99. u32 aer; /* Arbiter Event Register */
  100. u32 aidr; /* Arbiter Interrupt Definition Register */
  101. u32 amr; /* Arbiter Mask Register */
  102. u32 aeatr; /* Arbiter Event Attributes Register */
  103. u32 aeadr; /* Arbiter Event Address Register */
  104. u32 aerr; /* Arbiter Event Response Register */
  105. u8 res1[0xDC];
  106. } arbiter512x_t;
  107. /*
  108. * Reset Module
  109. */
  110. typedef struct reset512x {
  111. u32 rcwl; /* Reset Configuration Word Low Register */
  112. u32 rcwh; /* Reset Configuration Word High Register */
  113. u8 res0[8];
  114. u32 rsr; /* Reset Status Register */
  115. u32 rmr; /* Reset Mode Register */
  116. u32 rpr; /* Reset protection Register */
  117. u32 rcr; /* Reset Control Register */
  118. u32 rcer; /* Reset Control Enable Register */
  119. u8 res1[0xDC];
  120. } reset512x_t;
  121. /* RSR - Reset Status Register */
  122. #define RSR_SWSR 0x00002000 /* software soft reset */
  123. #define RSR_SWHR 0x00001000 /* software hard reset */
  124. #define RSR_JHRS 0x00000200 /* jtag hreset */
  125. #define RSR_JSRS 0x00000100 /* jtag sreset status */
  126. #define RSR_CSHR 0x00000010 /* checkstop reset status */
  127. #define RSR_SWRS 0x00000008 /* software watchdog reset status */
  128. #define RSR_BMRS 0x00000004 /* bus monitop reset status */
  129. #define RSR_SRS 0x00000002 /* soft reset status */
  130. #define RSR_HRS 0x00000001 /* hard reset status */
  131. #define RSR_RES ~(RSR_SWSR | RSR_SWHR |\
  132. RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
  133. RSR_BMRS | RSR_SRS | RSR_HRS)
  134. /* RMR - Reset Mode Register */
  135. #define RMR_CSRE 0x00000001 /* checkstop reset enable */
  136. #define RMR_CSRE_SHIFT 0
  137. #define RMR_RES (~(RMR_CSRE))
  138. /* RCR - Reset Control Register */
  139. #define RCR_SWHR 0x00000002 /* software hard reset */
  140. #define RCR_SWSR 0x00000001 /* software soft reset */
  141. #define RCR_RES (~(RCR_SWHR | RCR_SWSR))
  142. /* RCER - Reset Control Enable Register */
  143. #define RCER_CRE 0x00000001 /* software hard reset */
  144. #define RCER_RES (~(RCER_CRE))
  145. /*
  146. * Clock Module
  147. */
  148. typedef struct clk512x {
  149. u32 spmr; /* System PLL Mode Register */
  150. u32 sccr[2]; /* System Clock Control Registers */
  151. u32 scfr[2]; /* System Clock Frequency Registers */
  152. u8 res0[4];
  153. u32 bcr; /* Bread Crumb Register */
  154. u32 pscccr[12]; /* PSC0-11 Clock Control Registers */
  155. u32 spccr; /* SPDIF Clock Control Register */
  156. u32 cccr; /* CFM Clock Control Register */
  157. u32 dccr; /* DIU Clock Control Register */
  158. u32 msccr[4]; /* MSCAN1-4 Clock Control Registers */
  159. u8 res1[0x98];
  160. } clk512x_t;
  161. /* SPMR - System PLL Mode Register */
  162. #define SPMR_SPMF 0x0F000000
  163. #define SPMR_SPMF_SHIFT 24
  164. #define SPMR_CPMF 0x000F0000
  165. #define SPMR_CPMF_SHIFT 16
  166. /* System Clock Control Register 1 commands */
  167. #define CLOCK_SCCR1_CFG_EN 0x80000000
  168. #define CLOCK_SCCR1_LPC_EN 0x40000000
  169. #define CLOCK_SCCR1_NFC_EN 0x20000000
  170. #define CLOCK_SCCR1_PATA_EN 0x10000000
  171. #define CLOCK_SCCR1_PSC_EN(cn) (0x08000000 >> (cn))
  172. #define CLOCK_SCCR1_PSCFIFO_EN 0x00008000
  173. #define CLOCK_SCCR1_SATA_EN 0x00004000
  174. #define CLOCK_SCCR1_FEC_EN 0x00002000
  175. #define CLOCK_SCCR1_TPR_EN 0x00001000
  176. #define CLOCK_SCCR1_PCI_EN 0x00000800
  177. #define CLOCK_SCCR1_DDR_EN 0x00000400
  178. /* System Clock Control Register 2 commands */
  179. #define CLOCK_SCCR2_DIU_EN 0x80000000
  180. #define CLOCK_SCCR2_AXE_EN 0x40000000
  181. #define CLOCK_SCCR2_MEM_EN 0x20000000
  182. #define CLOCK_SCCR2_USB1_EN 0x10000000
  183. #define CLOCK_SCCR2_USB2_EN 0x08000000
  184. #define CLOCK_SCCR2_I2C_EN 0x04000000
  185. #define CLOCK_SCCR2_BDLC_EN 0x02000000
  186. #define CLOCK_SCCR2_SDHC_EN 0x01000000
  187. #define CLOCK_SCCR2_SPDIF_EN 0x00800000
  188. #define CLOCK_SCCR2_MBX_BUS_EN 0x00400000
  189. #define CLOCK_SCCR2_MBX_EN 0x00200000
  190. #define CLOCK_SCCR2_MBX_3D_EN 0x00100000
  191. #define CLOCK_SCCR2_IIM_EN 0x00080000
  192. /* SCFR1 System Clock Frequency Register 1 */
  193. #ifndef SCFR1_IPS_DIV
  194. #define SCFR1_IPS_DIV 0x3
  195. #endif
  196. #define SCFR1_IPS_DIV_MASK 0x03800000
  197. #define SCFR1_IPS_DIV_SHIFT 23
  198. #define SCFR1_PCI_DIV 0x6
  199. #define SCFR1_PCI_DIV_MASK 0x00700000
  200. #define SCFR1_PCI_DIV_SHIFT 20
  201. #define SCFR1_LPC_DIV_MASK 0x00003800
  202. #define SCFR1_LPC_DIV_SHIFT 11
  203. #define SCFR1_NFC_DIV_MASK 0x00000700
  204. #define SCFR1_NFC_DIV_SHIFT 8
  205. #define SCFR1_DIU_DIV_MASK 0x000000FF
  206. #define SCFR1_DIU_DIV_SHIFT 0
  207. /* SCFR2 System Clock Frequency Register 2 */
  208. #define SCFR2_SYS_DIV 0xFC000000
  209. #define SCFR2_SYS_DIV_SHIFT 26
  210. /* SPCR - System Priority Configuration Register */
  211. #define SPCR_TBEN 0x00400000 /* E300 core time base unit enable */
  212. /*
  213. * Power Management Control Module
  214. */
  215. typedef struct pmc512x {
  216. u8 fixme[0x100];
  217. } pmc512x_t;
  218. /*
  219. * General purpose I/O module
  220. */
  221. typedef struct gpio512x {
  222. u32 gpdir;
  223. u32 gpodr;
  224. u32 gpdat;
  225. u32 gpier;
  226. u32 gpimr;
  227. u32 gpicr1;
  228. u32 gpicr2;
  229. u8 res0[0xE4];
  230. } gpio512x_t;
  231. /*
  232. * DDR Memory Controller Memory Map
  233. */
  234. typedef struct ddr512x {
  235. u32 ddr_sys_config; /* System Configuration Register */
  236. u32 ddr_time_config0; /* Timing Configuration Register */
  237. u32 ddr_time_config1; /* Timing Configuration Register */
  238. u32 ddr_time_config2; /* Timing Configuration Register */
  239. u32 ddr_command; /* Command Register */
  240. u32 ddr_compact_command; /* Compact Command Register */
  241. u32 self_refresh_cmd_0; /* Enter/Exit Self Refresh Registers */
  242. u32 self_refresh_cmd_1; /* Enter/Exit Self Refresh Registers */
  243. u32 self_refresh_cmd_2; /* Enter/Exit Self Refresh Registers */
  244. u32 self_refresh_cmd_3; /* Enter/Exit Self Refresh Registers */
  245. u32 self_refresh_cmd_4; /* Enter/Exit Self Refresh Registers */
  246. u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */
  247. u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */
  248. u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */
  249. u32 dqs_config_offset_count; /* DQS Config Offset Count */
  250. u32 dqs_config_offset_time; /* DQS Config Offset Time */
  251. u32 DQS_delay_status; /* DQS Delay Status */
  252. u32 res0[0xF];
  253. u32 prioman_config1; /* Priority Manager Configuration */
  254. u32 prioman_config2; /* Priority Manager Configuration */
  255. u32 hiprio_config; /* High Priority Configuration */
  256. u32 lut_table0_main_upper; /* LUT0 Main Upper */
  257. u32 lut_table1_main_upper; /* LUT1 Main Upper */
  258. u32 lut_table2_main_upper; /* LUT2 Main Upper */
  259. u32 lut_table3_main_upper; /* LUT3 Main Upper */
  260. u32 lut_table4_main_upper; /* LUT4 Main Upper */
  261. u32 lut_table0_main_lower; /* LUT0 Main Lower */
  262. u32 lut_table1_main_lower; /* LUT1 Main Lower */
  263. u32 lut_table2_main_lower; /* LUT2 Main Lower */
  264. u32 lut_table3_main_lower; /* LUT3 Main Lower */
  265. u32 lut_table4_main_lower; /* LUT4 Main Lower */
  266. u32 lut_table0_alternate_upper; /* LUT0 Alternate Upper */
  267. u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */
  268. u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */
  269. u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */
  270. u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */
  271. u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */
  272. u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */
  273. u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */
  274. u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */
  275. u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */
  276. u32 performance_monitor_config;
  277. u32 event_time_counter;
  278. u32 event_time_preset;
  279. u32 performance_monitor1_address_low;
  280. u32 performance_monitor2_address_low;
  281. u32 performance_monitor1_address_hi;
  282. u32 performance_monitor2_address_hi;
  283. u32 res1[2];
  284. u32 performance_monitor1_read_counter;
  285. u32 performance_monitor2_read_counter;
  286. u32 performance_monitor1_write_counter;
  287. u32 performance_monitor2_write_counter;
  288. u32 granted_ack_counter0;
  289. u32 granted_ack_counter1;
  290. u32 granted_ack_counter2;
  291. u32 granted_ack_counter3;
  292. u32 granted_ack_counter4;
  293. u32 cumulative_wait_counter0;
  294. u32 cumulative_wait_counter1;
  295. u32 cumulative_wait_counter2;
  296. u32 cumulative_wait_counter3;
  297. u32 cumulative_wait_counter4;
  298. u32 summed_priority_counter0;
  299. u32 summed_priority_counter1;
  300. u32 summed_priority_counter2;
  301. u32 summed_priority_counter3;
  302. u32 summed_priority_counter4;
  303. u32 res2[0x3AD];
  304. } ddr512x_t;
  305. /* MDDRC SYS CFG and Timing CFG0 Registers */
  306. #define MDDRC_SYS_CFG_EN 0xF0000000
  307. #define MDDRC_SYS_CFG_CKE_MASK 0x40000000
  308. #define MDDRC_SYS_CFG_CMD_MASK 0x10000000
  309. #define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF
  310. /*
  311. * DDR Memory Controller Configuration settings
  312. */
  313. typedef struct ddr512x_config {
  314. u32 ddr_sys_config; /* System Configuration Register */
  315. u32 ddr_time_config0; /* Timing Configuration Register */
  316. u32 ddr_time_config1; /* Timing Configuration Register */
  317. u32 ddr_time_config2; /* Timing Configuration Register */
  318. } ddr512x_config_t;
  319. typedef struct sdram_conf_s {
  320. unsigned long size;
  321. ddr512x_config_t cfg;
  322. } sdram_conf_t;
  323. /*
  324. * DMA/Messaging Unit
  325. */
  326. typedef struct dma512x {
  327. u8 fixme[0x1800];
  328. } dma512x_t;
  329. /*
  330. * PCI Software Configuration Registers
  331. */
  332. typedef struct pciconf512x {
  333. u32 config_address;
  334. u32 config_data;
  335. u32 int_ack;
  336. u8 res[116];
  337. } pciconf512x_t;
  338. /*
  339. * PCI Outbound Translation Register
  340. */
  341. typedef struct pci_outbound_window {
  342. u32 potar;
  343. u8 res0[4];
  344. u32 pobar;
  345. u8 res1[4];
  346. u32 pocmr;
  347. u8 res2[4];
  348. } pot512x_t;
  349. /* POTAR - PCI Outbound Translation Address Register */
  350. #define POTAR_TA_MASK 0x000fffff
  351. /* POBAR - PCI Outbound Base Address Register */
  352. #define POBAR_BA_MASK 0x000fffff
  353. /* POCMR - PCI Outbound Comparision Mask Register */
  354. #define POCMR_EN 0x80000000
  355. #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */
  356. #define POCMR_PRE 0x20000000 /* prefetch enable */
  357. #define POCMR_SBS 0x00100000 /* special byte swap enable */
  358. #define POCMR_CM_MASK 0x000fffff
  359. #define POCMR_CM_4G 0x00000000
  360. #define POCMR_CM_2G 0x00080000
  361. #define POCMR_CM_1G 0x000C0000
  362. #define POCMR_CM_512M 0x000E0000
  363. #define POCMR_CM_256M 0x000F0000
  364. #define POCMR_CM_128M 0x000F8000
  365. #define POCMR_CM_64M 0x000FC000
  366. #define POCMR_CM_32M 0x000FE000
  367. #define POCMR_CM_16M 0x000FF000
  368. #define POCMR_CM_8M 0x000FF800
  369. #define POCMR_CM_4M 0x000FFC00
  370. #define POCMR_CM_2M 0x000FFE00
  371. #define POCMR_CM_1M 0x000FFF00
  372. #define POCMR_CM_512K 0x000FFF80
  373. #define POCMR_CM_256K 0x000FFFC0
  374. #define POCMR_CM_128K 0x000FFFE0
  375. #define POCMR_CM_64K 0x000FFFF0
  376. #define POCMR_CM_32K 0x000FFFF8
  377. #define POCMR_CM_16K 0x000FFFFC
  378. #define POCMR_CM_8K 0x000FFFFE
  379. #define POCMR_CM_4K 0x000FFFFF
  380. /*
  381. * Sequencer
  382. */
  383. typedef struct ios512x {
  384. pot512x_t pot[6];
  385. u8 res0[0x60];
  386. u32 pmcr;
  387. u8 res1[4];
  388. u32 dtcr;
  389. u8 res2[4];
  390. } ios512x_t;
  391. /*
  392. * PCI Controller
  393. */
  394. typedef struct pcictrl512x {
  395. u32 esr;
  396. u32 ecdr;
  397. u32 eer;
  398. u32 eatcr;
  399. u32 eacr;
  400. u32 eeacr;
  401. u32 edlcr;
  402. u32 edhcr;
  403. u32 gcr;
  404. u32 ecr;
  405. u32 gsr;
  406. u8 res0[12];
  407. u32 pitar2;
  408. u8 res1[4];
  409. u32 pibar2;
  410. u32 piebar2;
  411. u32 piwar2;
  412. u8 res2[4];
  413. u32 pitar1;
  414. u8 res3[4];
  415. u32 pibar1;
  416. u32 piebar1;
  417. u32 piwar1;
  418. u8 res4[4];
  419. u32 pitar0;
  420. u8 res5[4];
  421. u32 pibar0;
  422. u8 res6[4];
  423. u32 piwar0;
  424. u8 res7[132];
  425. } pcictrl512x_t;
  426. /* PITAR - PCI Inbound Translation Address Register
  427. */
  428. #define PITAR_TA_MASK 0x000fffff
  429. /* PIBAR - PCI Inbound Base/Extended Address Register
  430. */
  431. #define PIBAR_MASK 0xffffffff
  432. #define PIEBAR_EBA_MASK 0x000fffff
  433. /* PIWAR - PCI Inbound Windows Attributes Register
  434. */
  435. #define PIWAR_EN 0x80000000
  436. #define PIWAR_SBS 0x40000000
  437. #define PIWAR_PF 0x20000000
  438. #define PIWAR_RTT_MASK 0x000f0000
  439. #define PIWAR_RTT_NO_SNOOP 0x00040000
  440. #define PIWAR_RTT_SNOOP 0x00050000
  441. #define PIWAR_WTT_MASK 0x0000f000
  442. #define PIWAR_WTT_NO_SNOOP 0x00004000
  443. #define PIWAR_WTT_SNOOP 0x00005000
  444. /*
  445. * MSCAN
  446. */
  447. typedef struct mscan512x {
  448. u8 fixme[0x100];
  449. } mscan512x_t;
  450. /*
  451. * BDLC
  452. */
  453. typedef struct bdlc512x {
  454. u8 fixme[0x100];
  455. } bdlc512x_t;
  456. /*
  457. * SDHC
  458. */
  459. typedef struct sdhc512x {
  460. u8 fixme[0x100];
  461. } sdhc512x_t;
  462. /*
  463. * SPDIF
  464. */
  465. typedef struct spdif512x {
  466. u8 fixme[0x100];
  467. } spdif512x_t;
  468. /*
  469. * I2C
  470. */
  471. typedef struct i2c512x_dev {
  472. volatile u32 madr; /* I2Cn + 0x00 */
  473. volatile u32 mfdr; /* I2Cn + 0x04 */
  474. volatile u32 mcr; /* I2Cn + 0x08 */
  475. volatile u32 msr; /* I2Cn + 0x0C */
  476. volatile u32 mdr; /* I2Cn + 0x10 */
  477. u8 res0[0x0C];
  478. } i2c512x_dev_t;
  479. /* Number of I2C buses */
  480. #define I2C_BUS_CNT 3
  481. typedef struct i2c512x {
  482. i2c512x_dev_t dev[I2C_BUS_CNT];
  483. volatile u32 icr;
  484. volatile u32 mifr;
  485. u8 res0[0x98];
  486. } i2c512x_t;
  487. /* I2Cn control register bits */
  488. #define I2C_EN 0x80
  489. #define I2C_IEN 0x40
  490. #define I2C_STA 0x20
  491. #define I2C_TX 0x10
  492. #define I2C_TXAK 0x08
  493. #define I2C_RSTA 0x04
  494. #define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
  495. /* I2Cn status register bits */
  496. #define I2C_CF 0x80
  497. #define I2C_AAS 0x40
  498. #define I2C_BB 0x20
  499. #define I2C_AL 0x10
  500. #define I2C_SRW 0x04
  501. #define I2C_IF 0x02
  502. #define I2C_RXAK 0x01
  503. /*
  504. * AXE
  505. */
  506. typedef struct axe512x {
  507. u8 fixme[0x100];
  508. } axe512x_t;
  509. /*
  510. * DIU
  511. */
  512. typedef struct diu512x {
  513. u8 fixme[0x100];
  514. } diu512x_t;
  515. /*
  516. * CFM
  517. */
  518. typedef struct cfm512x {
  519. u8 fixme[0x100];
  520. } cfm512x_t;
  521. /*
  522. * FEC
  523. */
  524. typedef struct fec512x {
  525. u32 fec_id; /* FEC_ID register */
  526. u32 ievent; /* Interrupt event register */
  527. u32 imask; /* Interrupt mask register */
  528. u32 reserved_01;
  529. u32 r_des_active; /* Receive ring updated flag */
  530. u32 x_des_active; /* Transmit ring updated flag */
  531. u32 reserved_02[3];
  532. u32 ecntrl; /* Ethernet control register */
  533. u32 reserved_03[6];
  534. u32 mii_data; /* MII data register */
  535. u32 mii_speed; /* MII speed register */
  536. u32 reserved_04[7];
  537. u32 mib_control; /* MIB control/status register */
  538. u32 reserved_05[7];
  539. u32 r_cntrl; /* Receive control register */
  540. u32 r_hash; /* Receive hash */
  541. u32 reserved_06[14];
  542. u32 x_cntrl; /* Transmit control register */
  543. u32 reserved_07[7];
  544. u32 paddr1; /* Physical address low */
  545. u32 paddr2; /* Physical address high + type field */
  546. u32 op_pause; /* Opcode + pause duration */
  547. u32 reserved_08[10];
  548. u32 iaddr1; /* Upper 32 bits of individual hash table */
  549. u32 iaddr2; /* Lower 32 bits of individual hash table */
  550. u32 gaddr1; /* Upper 32 bits of group hash table */
  551. u32 gaddr2; /* Lower 32 bits of group hash table */
  552. u32 reserved_09[7];
  553. u32 x_wmrk; /* Transmit FIFO watermark */
  554. u32 reserved_10;
  555. u32 r_bound; /* End of RAM */
  556. u32 r_fstart; /* Receive FIFO start address */
  557. u32 reserved_11[11];
  558. u32 r_des_start; /* Beginning of receive descriptor ring */
  559. u32 x_des_start; /* Pointer to beginning of transmit descriptor ring */
  560. u32 r_buff_size; /* Receive buffer size */
  561. u32 reserved_12[26];
  562. u32 dma_control; /* DMA control for IP bus, AMBA IF + DMA revision */
  563. u32 reserved_13[2];
  564. u32 mib[128]; /* MIB Block Counters */
  565. u32 fifo[256]; /* used by FEC, can only be accessed by DMA */
  566. } fec512x_t;
  567. /*
  568. * ULPI
  569. */
  570. typedef struct ulpi512x {
  571. u8 fixme[0x600];
  572. } ulpi512x_t;
  573. /*
  574. * UTMI
  575. */
  576. typedef struct utmi512x {
  577. u8 fixme[0x3000];
  578. } utmi512x_t;
  579. /*
  580. * PCI DMA
  581. */
  582. typedef struct pcidma512x {
  583. u8 fixme[0x300];
  584. } pcidma512x_t;
  585. /*
  586. * IO Control
  587. */
  588. typedef struct ioctrl512x {
  589. u32 io_control_mem; /* MEM pad ctrl reg */
  590. u32 io_control_gp; /* GP pad ctrl reg */
  591. u32 io_control_lpc_clk; /* LPC_CLK pad ctrl reg */
  592. u32 io_control_lpc_oe; /* LPC_OE pad ctrl reg */
  593. u32 io_control_lpc_rw; /* LPC_R/W pad ctrl reg */
  594. u32 io_control_lpc_ack; /* LPC_ACK pad ctrl reg */
  595. u32 io_control_lpc_cs0; /* LPC_CS0 pad ctrl reg */
  596. u32 io_control_nfc_ce0; /* NFC_CE0 pad ctrl reg */
  597. u32 io_control_lpc_cs1; /* LPC_CS1 pad ctrl reg */
  598. u32 io_control_lpc_cs2; /* LPC_CS2 pad ctrl reg */
  599. u32 io_control_lpc_ax03; /* LPC_AX03 pad ctrl reg */
  600. u32 io_control_emb_ax02; /* EMB_AX02 pad ctrl reg */
  601. u32 io_control_emb_ax01; /* EMB_AX01 pad ctrl reg */
  602. u32 io_control_emb_ax00; /* EMB_AX00 pad ctrl reg */
  603. u32 io_control_emb_ad31; /* EMB_AD31 pad ctrl reg */
  604. u32 io_control_emb_ad30; /* EMB_AD30 pad ctrl reg */
  605. u32 io_control_emb_ad29; /* EMB_AD29 pad ctrl reg */
  606. u32 io_control_emb_ad28; /* EMB_AD28 pad ctrl reg */
  607. u32 io_control_emb_ad27; /* EMB_AD27 pad ctrl reg */
  608. u32 io_control_emb_ad26; /* EMB_AD26 pad ctrl reg */
  609. u32 io_control_emb_ad25; /* EMB_AD25 pad ctrl reg */
  610. u32 io_control_emb_ad24; /* EMB_AD24 pad ctrl reg */
  611. u32 io_control_emb_ad23; /* EMB_AD23 pad ctrl reg */
  612. u32 io_control_emb_ad22; /* EMB_AD22 pad ctrl reg */
  613. u32 io_control_emb_ad21; /* EMB_AD21 pad ctrl reg */
  614. u32 io_control_emb_ad20; /* EMB_AD20 pad ctrl reg */
  615. u32 io_control_emb_ad19; /* EMB_AD19 pad ctrl reg */
  616. u32 io_control_emb_ad18; /* EMB_AD18 pad ctrl reg */
  617. u32 io_control_emb_ad17; /* EMB_AD17 pad ctrl reg */
  618. u32 io_control_emb_ad16; /* EMB_AD16 pad ctrl reg */
  619. u32 io_control_emb_ad15; /* EMB_AD15 pad ctrl reg */
  620. u32 io_control_emb_ad14; /* EMB_AD14 pad ctrl reg */
  621. u32 io_control_emb_ad13; /* EMB_AD13 pad ctrl reg */
  622. u32 io_control_emb_ad12; /* EMB_AD12 pad ctrl reg */
  623. u32 io_control_emb_ad11; /* EMB_AD11 pad ctrl reg */
  624. u32 io_control_emb_ad10; /* EMB_AD10 pad ctrl reg */
  625. u32 io_control_emb_ad09; /* EMB_AD09 pad ctrl reg */
  626. u32 io_control_emb_ad08; /* EMB_AD08 pad ctrl reg */
  627. u32 io_control_emb_ad07; /* EMB_AD07 pad ctrl reg */
  628. u32 io_control_emb_ad06; /* EMB_AD06 pad ctrl reg */
  629. u32 io_control_emb_ad05; /* EMB_AD05 pad ctrl reg */
  630. u32 io_control_emb_ad04; /* EMB_AD04 pad ctrl reg */
  631. u32 io_control_emb_ad03; /* EMB_AD03 pad ctrl reg */
  632. u32 io_control_emb_ad02; /* EMB_AD02 pad ctrl reg */
  633. u32 io_control_emb_ad01; /* EMB_AD01 pad ctrl reg */
  634. u32 io_control_emb_ad00; /* EMB_AD00 pad ctrl reg */
  635. u32 io_control_pata_ce1; /* PATA_CE1 pad ctrl reg */
  636. u32 io_control_pata_ce2; /* PATA_CE2 pad ctrl reg */
  637. u32 io_control_pata_isolate; /* PATA_ISOLATE pad ctrl reg */
  638. u32 io_control_pata_ior; /* PATA_IOR pad ctrl reg */
  639. u32 io_control_pata_iow; /* PATA_IOW pad ctrl reg */
  640. u32 io_control_pata_iochrdy; /* PATA_IOCHRDY pad ctrl reg */
  641. u32 io_control_pata_intrq; /* PATA_INTRQ pad ctrl reg */
  642. u32 io_control_pata_drq; /* PATA_DRQ pad ctrl reg */
  643. u32 io_control_pata_dack; /* PATA_DACK pad ctrl reg */
  644. u32 io_control_nfc_wp; /* NFC_WP pad ctrl reg */
  645. u32 io_control_nfc_rb; /* NFC_RB pad ctrl reg */
  646. u32 io_control_nfc_ale; /* NFC_ALE pad ctrl reg */
  647. u32 io_control_nfc_cle; /* NFC_CLE pad ctrl reg */
  648. u32 io_control_nfc_we; /* NFC_WE pad ctrl reg */
  649. u32 io_control_nfc_re; /* NFC_RE pad ctrl reg */
  650. u32 io_control_pci_ad31; /* PCI_AD31 pad ctrl reg */
  651. u32 io_control_pci_ad30; /* PCI_AD30 pad ctrl reg */
  652. u32 io_control_pci_ad29; /* PCI_AD29 pad ctrl reg */
  653. u32 io_control_pci_ad28; /* PCI_AD28 pad ctrl reg */
  654. u32 io_control_pci_ad27; /* PCI_AD27 pad ctrl reg */
  655. u32 io_control_pci_ad26; /* PCI_AD26 pad ctrl reg */
  656. u32 io_control_pci_ad25; /* PCI_AD25 pad ctrl reg */
  657. u32 io_control_pci_ad24; /* PCI_AD24 pad ctrl reg */
  658. u32 io_control_pci_ad23; /* PCI_AD23 pad ctrl reg */
  659. u32 io_control_pci_ad22; /* PCI_AD22 pad ctrl reg */
  660. u32 io_control_pci_ad21; /* PCI_AD21 pad ctrl reg */
  661. u32 io_control_pci_ad20; /* PCI_AD20 pad ctrl reg */
  662. u32 io_control_pci_ad19; /* PCI_AD19 pad ctrl reg */
  663. u32 io_control_pci_ad18; /* PCI_AD18 pad ctrl reg */
  664. u32 io_control_pci_ad17; /* PCI_AD17 pad ctrl reg */
  665. u32 io_control_pci_ad16; /* PCI_AD16 pad ctrl reg */
  666. u32 io_control_pci_ad15; /* PCI_AD15 pad ctrl reg */
  667. u32 io_control_pci_ad14; /* PCI_AD14 pad ctrl reg */
  668. u32 io_control_pci_ad13; /* PCI_AD13 pad ctrl reg */
  669. u32 io_control_pci_ad12; /* PCI_AD12 pad ctrl reg */
  670. u32 io_control_pci_ad11; /* PCI_AD11 pad ctrl reg */
  671. u32 io_control_pci_ad10; /* PCI_AD10 pad ctrl reg */
  672. u32 io_control_pci_ad09; /* PCI_AD09 pad ctrl reg */
  673. u32 io_control_pci_ad08; /* PCI_AD08 pad ctrl reg */
  674. u32 io_control_pci_ad07; /* PCI_AD07 pad ctrl reg */
  675. u32 io_control_pci_ad06; /* PCI_AD06 pad ctrl reg */
  676. u32 io_control_pci_ad05; /* PCI_AD05 pad ctrl reg */
  677. u32 io_control_pci_ad04; /* PCI_AD04 pad ctrl reg */
  678. u32 io_control_pci_ad03; /* PCI_AD03 pad ctrl reg */
  679. u32 io_control_pci_ad02; /* PCI_AD02 pad ctrl reg */
  680. u32 io_control_pci_ad01; /* PCI_AD01 pad ctrl reg */
  681. u32 io_control_pci_ad00; /* PCI_AD00 pad ctrl reg */
  682. u32 io_control_pci_cbe0; /* PCI_CBE0 pad ctrl reg */
  683. u32 io_control_pci_cbe1; /* PCI_CBE1 pad ctrl reg */
  684. u32 io_control_pci_cbe2; /* PCI_CBE2 pad ctrl reg */
  685. u32 io_control_pci_cbe3; /* PCI_CBE3 pad ctrl reg */
  686. u32 io_control_pci_grant2; /* PCI_GRANT2 pad ctrl reg */
  687. u32 io_control_pci_req2; /* PCI_REQ2 pad ctrl reg */
  688. u32 io_control_pci_grant1; /* PCI_GRANT1 pad ctrl reg */
  689. u32 io_control_pci_req1; /* PCI_REQ1 pad ctrl reg */
  690. u32 io_control_pci_grant0; /* PCI_GRANT0 pad ctrl reg */
  691. u32 io_control_pci_req0; /* PCI_REQ0 pad ctrl reg */
  692. u32 io_control_pci_inta; /* PCI_INTA pad ctrl reg */
  693. u32 io_control_pci_clk; /* PCI_CLK pad ctrl reg */
  694. u32 io_control_pci_rst; /* PCI_RST- pad ctrl reg */
  695. u32 io_control_pci_frame; /* PCI_FRAME pad ctrl reg */
  696. u32 io_control_pci_idsel; /* PCI_IDSEL pad ctrl reg */
  697. u32 io_control_pci_devsel; /* PCI_DEVSEL pad ctrl reg */
  698. u32 io_control_pci_irdy; /* PCI_IRDY pad ctrl reg */
  699. u32 io_control_pci_trdy; /* PCI_TRDY pad ctrl reg */
  700. u32 io_control_pci_stop; /* PCI_STOP pad ctrl reg */
  701. u32 io_control_pci_par; /* PCI_PAR pad ctrl reg */
  702. u32 io_control_pci_perr; /* PCI_PERR pad ctrl reg */
  703. u32 io_control_pci_serr; /* PCI_SERR pad ctrl reg */
  704. u32 io_control_spdif_txclk; /* SPDIF_TXCLK pad ctrl reg */
  705. u32 io_control_spdif_tx; /* SPDIF_TX pad ctrl reg */
  706. u32 io_control_spdif_rx; /* SPDIF_RX pad ctrl reg */
  707. u32 io_control_i2c0_scl; /* I2C0_SCL pad ctrl reg */
  708. u32 io_control_i2c0_sda; /* I2C0_SDA pad ctrl reg */
  709. u32 io_control_i2c1_scl; /* I2C1_SCL pad ctrl reg */
  710. u32 io_control_i2c1_sda; /* I2C1_SDA pad ctrl reg */
  711. u32 io_control_i2c2_scl; /* I2C2_SCL pad ctrl reg */
  712. u32 io_control_i2c2_sda; /* I2C2_SDA pad ctrl reg */
  713. u32 io_control_irq0; /* IRQ0 pad ctrl reg */
  714. u32 io_control_irq1; /* IRQ1 pad ctrl reg */
  715. u32 io_control_can1_tx; /* CAN1_TX pad ctrl reg */
  716. u32 io_control_can2_tx; /* CAN2_TX pad ctrl reg */
  717. u32 io_control_j1850_tx; /* J1850_TX pad ctrl reg */
  718. u32 io_control_j1850_rx; /* J1850_RX pad ctrl reg */
  719. u32 io_control_psc_mclk_in; /* PSC_MCLK_IN pad ctrl reg */
  720. u32 io_control_psc0_0; /* PSC0_0 pad ctrl reg */
  721. u32 io_control_psc0_1; /* PSC0_1 pad ctrl reg */
  722. u32 io_control_psc0_2; /* PSC0_2 pad ctrl reg */
  723. u32 io_control_psc0_3; /* PSC0_3 pad ctrl reg */
  724. u32 io_control_psc0_4; /* PSC0_4 pad ctrl reg */
  725. u32 io_control_psc1_0; /* PSC1_0 pad ctrl reg */
  726. u32 io_control_psc1_1; /* PSC1_1 pad ctrl reg */
  727. u32 io_control_psc1_2; /* PSC1_2 pad ctrl reg */
  728. u32 io_control_psc1_3; /* PSC1_3 pad ctrl reg */
  729. u32 io_control_psc1_4; /* PSC1_4 pad ctrl reg */
  730. u32 io_control_psc2_0; /* PSC2_0 pad ctrl reg */
  731. u32 io_control_psc2_1; /* PSC2_1 pad ctrl reg */
  732. u32 io_control_psc2_2; /* PSC2_2 pad ctrl reg */
  733. u32 io_control_psc2_3; /* PSC2_3 pad ctrl reg */
  734. u32 io_control_psc2_4; /* PSC2_4 pad ctrl reg */
  735. u32 io_control_psc3_0; /* PSC3_0 pad ctrl reg */
  736. u32 io_control_psc3_1; /* PSC3_1 pad ctrl reg */
  737. u32 io_control_psc3_2; /* PSC3_2 pad ctrl reg */
  738. u32 io_control_psc3_3; /* PSC3_3 pad ctrl reg */
  739. u32 io_control_psc3_4; /* PSC3_4 pad ctrl reg */
  740. u32 io_control_psc4_0; /* PSC4_0 pad ctrl reg */
  741. u32 io_control_psc4_1; /* PSC4_1 pad ctrl reg */
  742. u32 io_control_psc4_2; /* PSC4_2 pad ctrl reg */
  743. u32 io_control_psc4_3; /* PSC4_3 pad ctrl reg */
  744. u32 io_control_psc4_4; /* PSC4_4 pad ctrl reg */
  745. u32 io_control_psc5_0; /* PSC5_0 pad ctrl reg */
  746. u32 io_control_psc5_1; /* PSC5_1 pad ctrl reg */
  747. u32 io_control_psc5_2; /* PSC5_2 pad ctrl reg */
  748. u32 io_control_psc5_3; /* PSC5_3 pad ctrl reg */
  749. u32 io_control_psc5_4; /* PSC5_4 pad ctrl reg */
  750. u32 io_control_psc6_0; /* PSC6_0 pad ctrl reg */
  751. u32 io_control_psc6_1; /* PSC6_1 pad ctrl reg */
  752. u32 io_control_psc6_2; /* PSC6_2 pad ctrl reg */
  753. u32 io_control_psc6_3; /* PSC6_3 pad ctrl reg */
  754. u32 io_control_psc6_4; /* PSC6_4 pad ctrl reg */
  755. u32 io_control_psc7_0; /* PSC7_0 pad ctrl reg */
  756. u32 io_control_psc7_1; /* PSC7_1 pad ctrl reg */
  757. u32 io_control_psc7_2; /* PSC7_2 pad ctrl reg */
  758. u32 io_control_psc7_3; /* PSC7_3 pad ctrl reg */
  759. u32 io_control_psc7_4; /* PSC7_4 pad ctrl reg */
  760. u32 io_control_psc8_0; /* PSC8_0 pad ctrl reg */
  761. u32 io_control_psc8_1; /* PSC8_1 pad ctrl reg */
  762. u32 io_control_psc8_2; /* PSC8_2 pad ctrl reg */
  763. u32 io_control_psc8_3; /* PSC8_3 pad ctrl reg */
  764. u32 io_control_psc8_4; /* PSC8_4 pad ctrl reg */
  765. u32 io_control_psc9_0; /* PSC9_0 pad ctrl reg */
  766. u32 io_control_psc9_1; /* PSC9_1 pad ctrl reg */
  767. u32 io_control_psc9_2; /* PSC9_2 pad ctrl reg */
  768. u32 io_control_psc9_3; /* PSC9_3 pad ctrl reg */
  769. u32 io_control_psc9_4; /* PSC9_4 pad ctrl reg */
  770. u32 io_control_psc10_0; /* PSC10_0 pad ctrl reg */
  771. u32 io_control_psc10_1; /* PSC10_1 pad ctrl reg */
  772. u32 io_control_psc10_2; /* PSC10_2 pad ctrl reg */
  773. u32 io_control_psc10_3; /* PSC10_3 pad ctrl reg */
  774. u32 io_control_psc10_4; /* PSC10_4 pad ctrl reg */
  775. u32 io_control_psc11_0; /* PSC11_0 pad ctrl reg */
  776. u32 io_control_psc11_1; /* PSC11_1 pad ctrl reg */
  777. u32 io_control_psc11_2; /* PSC11_2 pad ctrl reg */
  778. u32 io_control_psc11_3; /* PSC11_3 pad ctrl reg */
  779. u32 io_control_psc11_4; /* PSC11_4 pad ctrl reg */
  780. u32 io_control_ckstp_out; /* CKSTP_OUT pad ctrl reg */
  781. u32 io_control_usb_phy_drvvbus; /* USB2_DRVVBUS pad ctrl reg */
  782. u8 reserved[0x0cfc]; /* fill to 4096 bytes size */
  783. } ioctrl512x_t;
  784. /* IO pin fields */
  785. #define IO_PIN_FMUX(v) ((v) << 7) /* pin function */
  786. #define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */
  787. #define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */
  788. #define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */
  789. #define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */
  790. #define IO_PIN_DS(v) ((v)) /* slew rate */
  791. typedef struct iopin_t {
  792. int p_offset; /* offset from IOCTL_MEM_OFFSET */
  793. int nr_pins; /* number of pins to set this way */
  794. int bit_or; /* or in the value instead of overwrite */
  795. u_long val; /* value to write or or */
  796. }iopin_t;
  797. void iopin_initialize(iopin_t *,int);
  798. /*
  799. * support to adjust individual parts of the IO pin setup
  800. */
  801. #define IO_PIN_OVER_EACH (1 << 0) /* for compatibility */
  802. #define IO_PIN_OVER_FMUX (1 << 1)
  803. #define IO_PIN_OVER_HOLD (1 << 2)
  804. #define IO_PIN_OVER_PULL (1 << 3)
  805. #define IO_PIN_OVER_STRIG (1 << 4)
  806. #define IO_PIN_OVER_DRVSTR (1 << 5)
  807. void iopin_initialize_bits(iopin_t *, int);
  808. /*
  809. * IIM
  810. */
  811. typedef struct iim512x {
  812. u32 stat; /* IIM status register */
  813. u32 statm; /* IIM status IRQ mask */
  814. u32 err; /* IIM errors register */
  815. u32 emask; /* IIM error IRQ mask */
  816. u32 fctl; /* IIM fuse control register */
  817. u32 ua; /* IIM upper address register */
  818. u32 la; /* IIM lower address register */
  819. u32 sdat; /* IIM explicit sense data */
  820. u8 res0[0x08];
  821. u32 prg_p; /* IIM program protection register */
  822. u8 res1[0x10];
  823. u32 divide; /* IIM divide factor register */
  824. u8 res2[0x7c0];
  825. u32 fbac0; /* IIM fuse bank 0 prot (for Freescale use) */
  826. u32 fb0w0[0x1f]; /* IIM fuse bank 0 data (for Freescale use) */
  827. u8 res3[0x380];
  828. u32 fbac1; /* IIM fuse bank 1 protection */
  829. u32 fb1w1[0x01f]; /* IIM fuse bank 1 data */
  830. u8 res4[0x380];
  831. } iim512x_t;
  832. /*
  833. * LPC
  834. */
  835. typedef struct lpc512x {
  836. u32 cs_cfg[8]; /* Chip Select N Configuration Registers
  837. No dedicated entry for CS Boot as == CS0 */
  838. u32 cs_cr; /* Chip Select Control Register */
  839. u32 cs_sr; /* Chip Select Status Register */
  840. u32 cs_bcr; /* Chip Select Burst Control Register */
  841. u32 cs_dccr; /* Chip Select Deadcycle Control Register */
  842. u32 cs_hccr; /* Chip Select Holdcycle Control Register */
  843. u32 altr; /* Address Latch Timing Register */
  844. u8 res0[0xc8];
  845. u32 sclpc_psr; /* SCLPC Packet Size Register */
  846. u32 sclpc_sar; /* SCLPC Start Address Register */
  847. u32 sclpc_cr; /* SCLPC Control Register */
  848. u32 sclpc_er; /* SCLPC Enable Register */
  849. u32 sclpc_nar; /* SCLPC NextAddress Register */
  850. u32 sclpc_sr; /* SCLPC Status Register */
  851. u32 sclpc_bdr; /* SCLPC Bytes Done Register */
  852. u32 emb_scr; /* EMB Share Counter Register */
  853. u32 emb_pcr; /* EMB Pause Control Register */
  854. u8 res1[0x1c];
  855. u32 lpc_fdwr; /* LPC RX/TX FIFO Data Word Register */
  856. u32 lpc_fsr; /* LPC RX/TX FIFO Status Register */
  857. u32 lpc_cr; /* LPC RX/TX FIFO Control Register */
  858. u32 lpc_ar; /* LPC RX/TX FIFO Alarm Register */
  859. u8 res2[0xb0];
  860. } lpc512x_t;
  861. /*
  862. * PATA
  863. */
  864. typedef struct pata512x {
  865. /* LOCAL Registers */
  866. u32 pata_time1; /* Time register 1: PIO and tx timing parameter */
  867. u32 pata_time2; /* Time register 2: PIO timing parameter */
  868. u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */
  869. u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */
  870. u32 pata_time5; /* Time register 5: UDMA timing parameter */
  871. u32 pata_time6; /* Time register 6: UDMA timing parameter */
  872. u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */
  873. u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */
  874. u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/
  875. u32 pata_ata_control; /* ATA Interface control register */
  876. u32 pata_irq_pending; /* Interrupt pending register (READONLY) */
  877. u32 pata_irq_enable; /* Interrupt enable register */
  878. u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/
  879. u32 pata_fifo_alarm; /* fifo alarm threshold */
  880. u32 res1[0x1A];
  881. /* DRIVE Registers */
  882. u32 pata_drive_data; /* drive data register*/
  883. u32 pata_drive_features;/* drive features register */
  884. u32 pata_drive_sectcnt; /* drive sector count register */
  885. u32 pata_drive_sectnum; /* drive sector number register */
  886. u32 pata_drive_cyllow; /* drive cylinder low register */
  887. u32 pata_drive_cylhigh; /* drive cylinder high register */
  888. u32 pata_drive_dev_head;/* drive device head register */
  889. u32 pata_drive_command; /* write = drive command, read = drive status reg */
  890. u32 res2[0x06];
  891. u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */
  892. u32 res3[0x09];
  893. } pata512x_t;
  894. /*
  895. * PSC
  896. */
  897. typedef struct psc512x {
  898. volatile u8 mode; /* PSC + 0x00 */
  899. volatile u8 res0[3];
  900. union { /* PSC + 0x04 */
  901. volatile u16 status;
  902. volatile u16 clock_select;
  903. } sr_csr;
  904. #define psc_status sr_csr.status
  905. #define psc_clock_select sr_csr.clock_select
  906. volatile u16 res1;
  907. volatile u8 command; /* PSC + 0x08 */
  908. volatile u8 res2[3];
  909. union { /* PSC + 0x0c */
  910. volatile u8 buffer_8;
  911. volatile u16 buffer_16;
  912. volatile u32 buffer_32;
  913. } buffer;
  914. #define psc_buffer_8 buffer.buffer_8
  915. #define psc_buffer_16 buffer.buffer_16
  916. #define psc_buffer_32 buffer.buffer_32
  917. union { /* PSC + 0x10 */
  918. volatile u8 ipcr;
  919. volatile u8 acr;
  920. } ipcr_acr;
  921. #define psc_ipcr ipcr_acr.ipcr
  922. #define psc_acr ipcr_acr.acr
  923. volatile u8 res3[3];
  924. union { /* PSC + 0x14 */
  925. volatile u16 isr;
  926. volatile u16 imr;
  927. } isr_imr;
  928. #define psc_isr isr_imr.isr
  929. #define psc_imr isr_imr.imr
  930. volatile u16 res4;
  931. volatile u8 ctur; /* PSC + 0x18 */
  932. volatile u8 res5[3];
  933. volatile u8 ctlr; /* PSC + 0x1c */
  934. volatile u8 res6[3];
  935. volatile u32 ccr; /* PSC + 0x20 */
  936. volatile u8 res7[12];
  937. volatile u8 ivr; /* PSC + 0x30 */
  938. volatile u8 res8[3];
  939. volatile u8 ip; /* PSC + 0x34 */
  940. volatile u8 res9[3];
  941. volatile u8 op1; /* PSC + 0x38 */
  942. volatile u8 res10[3];
  943. volatile u8 op0; /* PSC + 0x3c */
  944. volatile u8 res11[3];
  945. volatile u32 sicr; /* PSC + 0x40 */
  946. volatile u8 res12[60];
  947. volatile u32 tfcmd; /* PSC + 0x80 */
  948. volatile u32 tfalarm; /* PSC + 0x84 */
  949. volatile u32 tfstat; /* PSC + 0x88 */
  950. volatile u32 tfintstat; /* PSC + 0x8C */
  951. volatile u32 tfintmask; /* PSC + 0x90 */
  952. volatile u32 tfcount; /* PSC + 0x94 */
  953. volatile u16 tfwptr; /* PSC + 0x98 */
  954. volatile u16 tfrptr; /* PSC + 0x9A */
  955. volatile u32 tfsize; /* PSC + 0x9C */
  956. volatile u8 res13[28];
  957. union { /* PSC + 0xBC */
  958. volatile u8 buffer_8;
  959. volatile u16 buffer_16;
  960. volatile u32 buffer_32;
  961. } tfdata_buffer;
  962. #define tfdata_8 tfdata_buffer.buffer_8
  963. #define tfdata_16 tfdata_buffer.buffer_16
  964. #define tfdata_32 tfdata_buffer.buffer_32
  965. volatile u32 rfcmd; /* PSC + 0xC0 */
  966. volatile u32 rfalarm; /* PSC + 0xC4 */
  967. volatile u32 rfstat; /* PSC + 0xC8 */
  968. volatile u32 rfintstat; /* PSC + 0xCC */
  969. volatile u32 rfintmask; /* PSC + 0xD0 */
  970. volatile u32 rfcount; /* PSC + 0xD4 */
  971. volatile u16 rfwptr; /* PSC + 0xD8 */
  972. volatile u16 rfrptr; /* PSC + 0xDA */
  973. volatile u32 rfsize; /* PSC + 0xDC */
  974. volatile u8 res18[28];
  975. union { /* PSC + 0xFC */
  976. volatile u8 buffer_8;
  977. volatile u16 buffer_16;
  978. volatile u32 buffer_32;
  979. } rfdata_buffer;
  980. #define rfdata_8 rfdata_buffer.buffer_8
  981. #define rfdata_16 rfdata_buffer.buffer_16
  982. #define rfdata_32 rfdata_buffer.buffer_32
  983. } psc512x_t;
  984. /* PSC FIFO Command values */
  985. #define PSC_FIFO_RESET_SLICE 0x80
  986. #define PSC_FIFO_ENABLE_SLICE 0x01
  987. /* PSC FIFO Controller Command values */
  988. #define FIFOC_ENABLE_CLOCK_GATE 0x01
  989. #define FIFOC_DISABLE_CLOCK_GATE 0x00
  990. /* PSC FIFO status */
  991. #define PSC_FIFO_EMPTY 0x01
  992. /* PSC Command values */
  993. #define PSC_RX_ENABLE 0x01
  994. #define PSC_RX_DISABLE 0x02
  995. #define PSC_TX_ENABLE 0x04
  996. #define PSC_TX_DISABLE 0x08
  997. #define PSC_SEL_MODE_REG_1 0x10
  998. #define PSC_RST_RX 0x20
  999. #define PSC_RST_TX 0x30
  1000. #define PSC_RST_ERR_STAT 0x40
  1001. #define PSC_RST_BRK_CHG_INT 0x50
  1002. #define PSC_START_BRK 0x60
  1003. #define PSC_STOP_BRK 0x70
  1004. /* PSC status register bits */
  1005. #define PSC_SR_CDE 0x0080
  1006. #define PSC_SR_TXEMP 0x0800
  1007. #define PSC_SR_OE 0x1000
  1008. #define PSC_SR_PE 0x2000
  1009. #define PSC_SR_FE 0x4000
  1010. #define PSC_SR_RB 0x8000
  1011. /* PSC mode fields */
  1012. #define PSC_MODE_5_BITS 0x00
  1013. #define PSC_MODE_6_BITS 0x01
  1014. #define PSC_MODE_7_BITS 0x02
  1015. #define PSC_MODE_8_BITS 0x03
  1016. #define PSC_MODE_PAREVEN 0x00
  1017. #define PSC_MODE_PARODD 0x04
  1018. #define PSC_MODE_PARFORCE 0x08
  1019. #define PSC_MODE_PARNONE 0x10
  1020. #define PSC_MODE_ENTIMEOUT 0x20
  1021. #define PSC_MODE_RXRTS 0x80
  1022. #define PSC_MODE_1_STOPBIT 0x07
  1023. /*
  1024. * FIFOC
  1025. */
  1026. typedef struct fifoc512x {
  1027. u32 fifoc_cmd;
  1028. u32 fifoc_int;
  1029. u32 fifoc_dma;
  1030. u32 fifoc_axe;
  1031. u32 fifoc_debug;
  1032. u8 fixme[0xEC];
  1033. } fifoc512x_t;
  1034. /*
  1035. * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs
  1036. *
  1037. * NOTE: individual PSC units are free to use whatever area (and size) of the
  1038. * FIFOC internal memory, so make sure memory areas for FIFO slices used by
  1039. * different PSCs do not overlap!
  1040. *
  1041. * Overall size of FIFOC memory is not documented in the MPC5121e RM, but
  1042. * tests indicate that it is 1024 words total.
  1043. *
  1044. * *_TX_SIZE and *_RX_SIZE is the number of 4-byte words for FIFO slice.
  1045. */
  1046. #define FIFOC_PSC0_TX_SIZE 0x04
  1047. #define FIFOC_PSC0_TX_ADDR 0x0
  1048. #define FIFOC_PSC0_RX_SIZE 0x04
  1049. #define FIFOC_PSC0_RX_ADDR 0x10
  1050. #define FIFOC_PSC1_TX_SIZE 0x04
  1051. #define FIFOC_PSC1_TX_ADDR 0x20
  1052. #define FIFOC_PSC1_RX_SIZE 0x04
  1053. #define FIFOC_PSC1_RX_ADDR 0x30
  1054. #define FIFOC_PSC2_TX_SIZE 0x04
  1055. #define FIFOC_PSC2_TX_ADDR 0x40
  1056. #define FIFOC_PSC2_RX_SIZE 0x04
  1057. #define FIFOC_PSC2_RX_ADDR 0x50
  1058. #define FIFOC_PSC3_TX_SIZE 0x04
  1059. #define FIFOC_PSC3_TX_ADDR 0x60
  1060. #define FIFOC_PSC3_RX_SIZE 0x04
  1061. #define FIFOC_PSC3_RX_ADDR 0x70
  1062. #define FIFOC_PSC4_TX_SIZE 0x04
  1063. #define FIFOC_PSC4_TX_ADDR 0x80
  1064. #define FIFOC_PSC4_RX_SIZE 0x04
  1065. #define FIFOC_PSC4_RX_ADDR 0x90
  1066. #define FIFOC_PSC5_TX_SIZE 0x04
  1067. #define FIFOC_PSC5_TX_ADDR 0xa0
  1068. #define FIFOC_PSC5_RX_SIZE 0x04
  1069. #define FIFOC_PSC5_RX_ADDR 0xb0
  1070. #define FIFOC_PSC6_TX_SIZE 0x04
  1071. #define FIFOC_PSC6_TX_ADDR 0xc0
  1072. #define FIFOC_PSC6_RX_SIZE 0x04
  1073. #define FIFOC_PSC6_RX_ADDR 0xd0
  1074. #define FIFOC_PSC7_TX_SIZE 0x04
  1075. #define FIFOC_PSC7_TX_ADDR 0xe0
  1076. #define FIFOC_PSC7_RX_SIZE 0x04
  1077. #define FIFOC_PSC7_RX_ADDR 0xf0
  1078. #define FIFOC_PSC8_TX_SIZE 0x04
  1079. #define FIFOC_PSC8_TX_ADDR 0x100
  1080. #define FIFOC_PSC8_RX_SIZE 0x04
  1081. #define FIFOC_PSC8_RX_ADDR 0x110
  1082. #define FIFOC_PSC9_TX_SIZE 0x04
  1083. #define FIFOC_PSC9_TX_ADDR 0x120
  1084. #define FIFOC_PSC9_RX_SIZE 0x04
  1085. #define FIFOC_PSC9_RX_ADDR 0x130
  1086. #define FIFOC_PSC10_TX_SIZE 0x04
  1087. #define FIFOC_PSC10_TX_ADDR 0x140
  1088. #define FIFOC_PSC10_RX_SIZE 0x04
  1089. #define FIFOC_PSC10_RX_ADDR 0x150
  1090. #define FIFOC_PSC11_TX_SIZE 0x04
  1091. #define FIFOC_PSC11_TX_ADDR 0x160
  1092. #define FIFOC_PSC11_RX_SIZE 0x04
  1093. #define FIFOC_PSC11_RX_ADDR 0x170
  1094. /*
  1095. * SATA
  1096. */
  1097. typedef struct sata512x {
  1098. u8 fixme[0x2000];
  1099. } sata512x_t;
  1100. typedef struct immap {
  1101. sysconf512x_t sysconf; /* System configuration */
  1102. u8 res0[0x700];
  1103. wdt512x_t wdt; /* Watch Dog Timer (WDT) */
  1104. rtclk512x_t rtc; /* Real Time Clock Module */
  1105. gpt512x_t gpt; /* General Purpose Timer */
  1106. ipic512x_t ipic; /* Integrated Programmable Interrupt Controller */
  1107. arbiter512x_t arbiter; /* CSB Arbiter */
  1108. reset512x_t reset; /* Reset Module */
  1109. clk512x_t clk; /* Clock Module */
  1110. pmc512x_t pmc; /* Power Management Control Module */
  1111. gpio512x_t gpio; /* General purpose I/O module */
  1112. u8 res1[0x100];
  1113. mscan512x_t mscan; /* MSCAN */
  1114. bdlc512x_t bdlc; /* BDLC */
  1115. sdhc512x_t sdhc; /* SDHC */
  1116. spdif512x_t spdif; /* SPDIF */
  1117. i2c512x_t i2c; /* I2C Controllers */
  1118. u8 res2[0x800];
  1119. axe512x_t axe; /* AXE */
  1120. diu512x_t diu; /* Display Interface Unit */
  1121. cfm512x_t cfm; /* Clock Frequency Measurement */
  1122. u8 res3[0x500];
  1123. fec512x_t fec; /* Fast Ethernet Controller */
  1124. ulpi512x_t ulpi; /* USB ULPI */
  1125. u8 res4[0xa00];
  1126. utmi512x_t utmi; /* USB UTMI */
  1127. u8 res5[0x1000];
  1128. pcidma512x_t pci_dma; /* PCI DMA */
  1129. pciconf512x_t pci_conf; /* PCI Configuration */
  1130. u8 res6[0x80];
  1131. ios512x_t ios; /* PCI Sequencer */
  1132. pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */
  1133. u8 res7[0xa00];
  1134. ddr512x_t mddrc; /* Multi-port DDR Memory Controller */
  1135. ioctrl512x_t io_ctrl; /* IO Control */
  1136. iim512x_t iim; /* IC Identification module */
  1137. u8 res8[0x4000];
  1138. lpc512x_t lpc; /* LocalPlus Controller */
  1139. pata512x_t pata; /* Parallel ATA */
  1140. u8 res9[0xd00];
  1141. psc512x_t psc[12]; /* PSCs */
  1142. u8 res10[0x300];
  1143. fifoc512x_t fifoc; /* FIFO Controller */
  1144. u8 res11[0x2000];
  1145. dma512x_t dma; /* DMA */
  1146. u8 res12[0xa800];
  1147. sata512x_t sata; /* Serial ATA */
  1148. u8 res13[0xde000];
  1149. } immap_t;
  1150. /* provide interface to get PATA base address */
  1151. static inline u32 get_pata_base (void)
  1152. {
  1153. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  1154. return (u32)(&im->pata);
  1155. }
  1156. #endif /* __ASSEMBLY__ */
  1157. #define CONFIG_SYS_MPC512x_USB1_OFFSET 0x4000
  1158. #define CONFIG_SYS_MPC512x_USB1_ADDR \
  1159. (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB1_OFFSET)
  1160. #define IIM_BASE_ADDR (CONFIG_SYS_IMMR + offsetof(immap_t, iim))
  1161. #endif /* __IMMAP_512x__ */