usb_ohci.c 41 KB

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  1. /*
  2. * URB OHCI HCD (Host Controller Driver) for USB on the MPC5200.
  3. *
  4. * (C) Copyright 2003-2004
  5. * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
  6. *
  7. * (C) Copyright 2004
  8. * Pierre Aubert, Staubli Faverges <p.aubert@staubli.com>
  9. *
  10. * Note: Much of this code has been derived from Linux 2.4
  11. * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
  12. * (C) Copyright 2000-2002 David Brownell
  13. *
  14. * SPDX-License-Identifier: GPL-2.0+
  15. */
  16. /*
  17. * IMPORTANT NOTES
  18. * 1 - this driver is intended for use with USB Mass Storage Devices
  19. * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
  20. */
  21. #include <common.h>
  22. #ifdef CONFIG_USB_OHCI
  23. #include <malloc.h>
  24. #include <usb.h>
  25. #include "usb_ohci.h"
  26. #include <mpc5xxx.h>
  27. #define OHCI_USE_NPS /* force NoPowerSwitching mode */
  28. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  29. #undef DEBUG
  30. #undef SHOW_INFO
  31. #undef OHCI_FILL_TRACE
  32. /* For initializing controller (mask in an HCFS mode too) */
  33. #define OHCI_CONTROL_INIT \
  34. (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  35. #define readl(a) (*((volatile u32 *)(a)))
  36. #define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
  37. #ifdef DEBUG
  38. #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  39. #else
  40. #define dbg(format, arg...) do {} while(0)
  41. #endif /* DEBUG */
  42. #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  43. #ifdef SHOW_INFO
  44. #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  45. #else
  46. #define info(format, arg...) do {} while(0)
  47. #endif
  48. #define m16_swap(x) swap_16(x)
  49. #define m32_swap(x) swap_32(x)
  50. #define ohci_cpu_to_le16(x) (x)
  51. #define ohci_cpu_to_le32(x) (x)
  52. /* global ohci_t */
  53. static ohci_t gohci;
  54. /* this must be aligned to a 256 byte boundary */
  55. struct ohci_hcca ghcca[1];
  56. /* a pointer to the aligned storage */
  57. struct ohci_hcca *phcca;
  58. /* this allocates EDs for all possible endpoints */
  59. struct ohci_device ohci_dev;
  60. /* urb_priv */
  61. urb_priv_t urb_priv;
  62. /* RHSC flag */
  63. int got_rhsc;
  64. /* device which was disconnected */
  65. struct usb_device *devgone;
  66. /* flag guarding URB transation */
  67. int urb_finished = 0;
  68. /*-------------------------------------------------------------------------*/
  69. /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
  70. * The erratum (#4) description is incorrect. AMD's workaround waits
  71. * till some bits (mostly reserved) are clear; ok for all revs.
  72. */
  73. #define OHCI_QUIRK_AMD756 0xabcd
  74. #define read_roothub(hc, register, mask) ({ \
  75. u32 temp = readl (&hc->regs->roothub.register); \
  76. if (hc->flags & OHCI_QUIRK_AMD756) \
  77. while (temp & mask) \
  78. temp = readl (&hc->regs->roothub.register); \
  79. temp; })
  80. static u32 roothub_a (struct ohci *hc)
  81. { return read_roothub (hc, a, 0xfc0fe000); }
  82. static inline u32 roothub_b (struct ohci *hc)
  83. { return readl (&hc->regs->roothub.b); }
  84. static inline u32 roothub_status (struct ohci *hc)
  85. { return readl (&hc->regs->roothub.status); }
  86. static u32 roothub_portstatus (struct ohci *hc, int i)
  87. { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
  88. /* forward declaration */
  89. static int hc_interrupt (void);
  90. static void
  91. td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
  92. int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
  93. /*-------------------------------------------------------------------------*
  94. * URB support functions
  95. *-------------------------------------------------------------------------*/
  96. /* free HCD-private data associated with this URB */
  97. static void urb_free_priv (urb_priv_t * urb)
  98. {
  99. int i;
  100. int last;
  101. struct td * td;
  102. last = urb->length - 1;
  103. if (last >= 0) {
  104. for (i = 0; i <= last; i++) {
  105. td = urb->td[i];
  106. if (td) {
  107. td->usb_dev = NULL;
  108. urb->td[i] = NULL;
  109. }
  110. }
  111. }
  112. }
  113. /*-------------------------------------------------------------------------*/
  114. #ifdef DEBUG
  115. static int sohci_get_current_frame_number (struct usb_device * dev);
  116. /* debug| print the main components of an URB
  117. * small: 0) header + data packets 1) just header */
  118. static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
  119. int transfer_len, struct devrequest * setup, char * str, int small)
  120. {
  121. urb_priv_t * purb = &urb_priv;
  122. dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
  123. str,
  124. sohci_get_current_frame_number (dev),
  125. usb_pipedevice (pipe),
  126. usb_pipeendpoint (pipe),
  127. usb_pipeout (pipe)? 'O': 'I',
  128. usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
  129. (usb_pipecontrol (pipe)? "CTRL": "BULK"),
  130. purb->actual_length,
  131. transfer_len, dev->status);
  132. #ifdef OHCI_VERBOSE_DEBUG
  133. if (!small) {
  134. int i, len;
  135. if (usb_pipecontrol (pipe)) {
  136. printf (__FILE__ ": cmd(8):");
  137. for (i = 0; i < 8 ; i++)
  138. printf (" %02x", ((__u8 *) setup) [i]);
  139. printf ("\n");
  140. }
  141. if (transfer_len > 0 && buffer) {
  142. printf (__FILE__ ": data(%d/%d):",
  143. purb->actual_length,
  144. transfer_len);
  145. len = usb_pipeout (pipe)?
  146. transfer_len: purb->actual_length;
  147. for (i = 0; i < 16 && i < len; i++)
  148. printf (" %02x", ((__u8 *) buffer) [i]);
  149. printf ("%s\n", i < len? "...": "");
  150. }
  151. }
  152. #endif
  153. }
  154. /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
  155. void ep_print_int_eds (ohci_t *ohci, char * str) {
  156. int i, j;
  157. __u32 * ed_p;
  158. for (i= 0; i < 32; i++) {
  159. j = 5;
  160. ed_p = &(ohci->hcca->int_table [i]);
  161. if (*ed_p == 0)
  162. continue;
  163. printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
  164. while (*ed_p != 0 && j--) {
  165. ed_t *ed = (ed_t *)ohci_cpu_to_le32(ed_p);
  166. printf (" ed: %4x;", ed->hwINFO);
  167. ed_p = &ed->hwNextED;
  168. }
  169. printf ("\n");
  170. }
  171. }
  172. static void ohci_dump_intr_mask (char *label, __u32 mask)
  173. {
  174. dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
  175. label,
  176. mask,
  177. (mask & OHCI_INTR_MIE) ? " MIE" : "",
  178. (mask & OHCI_INTR_OC) ? " OC" : "",
  179. (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
  180. (mask & OHCI_INTR_FNO) ? " FNO" : "",
  181. (mask & OHCI_INTR_UE) ? " UE" : "",
  182. (mask & OHCI_INTR_RD) ? " RD" : "",
  183. (mask & OHCI_INTR_SF) ? " SF" : "",
  184. (mask & OHCI_INTR_WDH) ? " WDH" : "",
  185. (mask & OHCI_INTR_SO) ? " SO" : ""
  186. );
  187. }
  188. static void maybe_print_eds (char *label, __u32 value)
  189. {
  190. ed_t *edp = (ed_t *)value;
  191. if (value) {
  192. dbg ("%s %08x", label, value);
  193. dbg ("%08x", edp->hwINFO);
  194. dbg ("%08x", edp->hwTailP);
  195. dbg ("%08x", edp->hwHeadP);
  196. dbg ("%08x", edp->hwNextED);
  197. }
  198. }
  199. static char * hcfs2string (int state)
  200. {
  201. switch (state) {
  202. case OHCI_USB_RESET: return "reset";
  203. case OHCI_USB_RESUME: return "resume";
  204. case OHCI_USB_OPER: return "operational";
  205. case OHCI_USB_SUSPEND: return "suspend";
  206. }
  207. return "?";
  208. }
  209. /* dump control and status registers */
  210. static void ohci_dump_status (ohci_t *controller)
  211. {
  212. struct ohci_regs *regs = controller->regs;
  213. __u32 temp;
  214. temp = readl (&regs->revision) & 0xff;
  215. if (temp != 0x10)
  216. dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
  217. temp = readl (&regs->control);
  218. dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
  219. (temp & OHCI_CTRL_RWE) ? " RWE" : "",
  220. (temp & OHCI_CTRL_RWC) ? " RWC" : "",
  221. (temp & OHCI_CTRL_IR) ? " IR" : "",
  222. hcfs2string (temp & OHCI_CTRL_HCFS),
  223. (temp & OHCI_CTRL_BLE) ? " BLE" : "",
  224. (temp & OHCI_CTRL_CLE) ? " CLE" : "",
  225. (temp & OHCI_CTRL_IE) ? " IE" : "",
  226. (temp & OHCI_CTRL_PLE) ? " PLE" : "",
  227. temp & OHCI_CTRL_CBSR
  228. );
  229. temp = readl (&regs->cmdstatus);
  230. dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
  231. (temp & OHCI_SOC) >> 16,
  232. (temp & OHCI_OCR) ? " OCR" : "",
  233. (temp & OHCI_BLF) ? " BLF" : "",
  234. (temp & OHCI_CLF) ? " CLF" : "",
  235. (temp & OHCI_HCR) ? " HCR" : ""
  236. );
  237. ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
  238. ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
  239. maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
  240. maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
  241. maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
  242. maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
  243. maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
  244. maybe_print_eds ("donehead", readl (&regs->donehead));
  245. }
  246. static void ohci_dump_roothub (ohci_t *controller, int verbose)
  247. {
  248. __u32 temp, ndp, i;
  249. temp = roothub_a (controller);
  250. ndp = (temp & RH_A_NDP);
  251. if (verbose) {
  252. dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
  253. ((temp & RH_A_POTPGT) >> 24) & 0xff,
  254. (temp & RH_A_NOCP) ? " NOCP" : "",
  255. (temp & RH_A_OCPM) ? " OCPM" : "",
  256. (temp & RH_A_DT) ? " DT" : "",
  257. (temp & RH_A_NPS) ? " NPS" : "",
  258. (temp & RH_A_PSM) ? " PSM" : "",
  259. ndp
  260. );
  261. temp = roothub_b (controller);
  262. dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
  263. temp,
  264. (temp & RH_B_PPCM) >> 16,
  265. (temp & RH_B_DR)
  266. );
  267. temp = roothub_status (controller);
  268. dbg ("roothub.status: %08x%s%s%s%s%s%s",
  269. temp,
  270. (temp & RH_HS_CRWE) ? " CRWE" : "",
  271. (temp & RH_HS_OCIC) ? " OCIC" : "",
  272. (temp & RH_HS_LPSC) ? " LPSC" : "",
  273. (temp & RH_HS_DRWE) ? " DRWE" : "",
  274. (temp & RH_HS_OCI) ? " OCI" : "",
  275. (temp & RH_HS_LPS) ? " LPS" : ""
  276. );
  277. }
  278. for (i = 0; i < ndp; i++) {
  279. temp = roothub_portstatus (controller, i);
  280. dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
  281. i,
  282. temp,
  283. (temp & RH_PS_PRSC) ? " PRSC" : "",
  284. (temp & RH_PS_OCIC) ? " OCIC" : "",
  285. (temp & RH_PS_PSSC) ? " PSSC" : "",
  286. (temp & RH_PS_PESC) ? " PESC" : "",
  287. (temp & RH_PS_CSC) ? " CSC" : "",
  288. (temp & RH_PS_LSDA) ? " LSDA" : "",
  289. (temp & RH_PS_PPS) ? " PPS" : "",
  290. (temp & RH_PS_PRS) ? " PRS" : "",
  291. (temp & RH_PS_POCI) ? " POCI" : "",
  292. (temp & RH_PS_PSS) ? " PSS" : "",
  293. (temp & RH_PS_PES) ? " PES" : "",
  294. (temp & RH_PS_CCS) ? " CCS" : ""
  295. );
  296. }
  297. }
  298. static void ohci_dump (ohci_t *controller, int verbose)
  299. {
  300. dbg ("OHCI controller usb-%s state", controller->slot_name);
  301. /* dumps some of the state we know about */
  302. ohci_dump_status (controller);
  303. if (verbose)
  304. ep_print_int_eds (controller, "hcca");
  305. dbg ("hcca frame #%04x", controller->hcca->frame_no);
  306. ohci_dump_roothub (controller, 1);
  307. }
  308. #endif /* DEBUG */
  309. /*-------------------------------------------------------------------------*
  310. * Interface functions (URB)
  311. *-------------------------------------------------------------------------*/
  312. /* get a transfer request */
  313. int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
  314. int transfer_len, struct devrequest *setup, int interval)
  315. {
  316. ohci_t *ohci;
  317. ed_t * ed;
  318. urb_priv_t *purb_priv;
  319. int i, size = 0;
  320. ohci = &gohci;
  321. /* when controller's hung, permit only roothub cleanup attempts
  322. * such as powering down ports */
  323. if (ohci->disabled) {
  324. err("sohci_submit_job: EPIPE");
  325. return -1;
  326. }
  327. /* if we have an unfinished URB from previous transaction let's
  328. * fail and scream as quickly as possible so as not to corrupt
  329. * further communication */
  330. if (!urb_finished) {
  331. err("sohci_submit_job: URB NOT FINISHED");
  332. return -1;
  333. }
  334. /* we're about to begin a new transaction here so mark the URB unfinished */
  335. urb_finished = 0;
  336. /* every endpoint has a ed, locate and fill it */
  337. if (!(ed = ep_add_ed (dev, pipe))) {
  338. err("sohci_submit_job: ENOMEM");
  339. return -1;
  340. }
  341. /* for the private part of the URB we need the number of TDs (size) */
  342. switch (usb_pipetype (pipe)) {
  343. case PIPE_BULK: /* one TD for every 4096 Byte */
  344. size = (transfer_len - 1) / 4096 + 1;
  345. break;
  346. case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
  347. size = (transfer_len == 0)? 2:
  348. (transfer_len - 1) / 4096 + 3;
  349. break;
  350. }
  351. if (size >= (N_URB_TD - 1)) {
  352. err("need %d TDs, only have %d", size, N_URB_TD);
  353. return -1;
  354. }
  355. purb_priv = &urb_priv;
  356. purb_priv->pipe = pipe;
  357. /* fill the private part of the URB */
  358. purb_priv->length = size;
  359. purb_priv->ed = ed;
  360. purb_priv->actual_length = 0;
  361. /* allocate the TDs */
  362. /* note that td[0] was allocated in ep_add_ed */
  363. for (i = 0; i < size; i++) {
  364. purb_priv->td[i] = td_alloc (dev);
  365. if (!purb_priv->td[i]) {
  366. purb_priv->length = i;
  367. urb_free_priv (purb_priv);
  368. err("sohci_submit_job: ENOMEM");
  369. return -1;
  370. }
  371. }
  372. if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
  373. urb_free_priv (purb_priv);
  374. err("sohci_submit_job: EINVAL");
  375. return -1;
  376. }
  377. /* link the ed into a chain if is not already */
  378. if (ed->state != ED_OPER)
  379. ep_link (ohci, ed);
  380. /* fill the TDs and link it to the ed */
  381. td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
  382. return 0;
  383. }
  384. /*-------------------------------------------------------------------------*/
  385. #ifdef DEBUG
  386. /* tell us the current USB frame number */
  387. static int sohci_get_current_frame_number (struct usb_device *usb_dev)
  388. {
  389. ohci_t *ohci = &gohci;
  390. return ohci_cpu_to_le16 (ohci->hcca->frame_no);
  391. }
  392. #endif
  393. /*-------------------------------------------------------------------------*
  394. * ED handling functions
  395. *-------------------------------------------------------------------------*/
  396. /* link an ed into one of the HC chains */
  397. static int ep_link (ohci_t *ohci, ed_t *edi)
  398. {
  399. volatile ed_t *ed = edi;
  400. ed->state = ED_OPER;
  401. switch (ed->type) {
  402. case PIPE_CONTROL:
  403. ed->hwNextED = 0;
  404. if (ohci->ed_controltail == NULL) {
  405. writel (ed, &ohci->regs->ed_controlhead);
  406. } else {
  407. ohci->ed_controltail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
  408. }
  409. ed->ed_prev = ohci->ed_controltail;
  410. if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
  411. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  412. ohci->hc_control |= OHCI_CTRL_CLE;
  413. writel (ohci->hc_control, &ohci->regs->control);
  414. }
  415. ohci->ed_controltail = edi;
  416. break;
  417. case PIPE_BULK:
  418. ed->hwNextED = 0;
  419. if (ohci->ed_bulktail == NULL) {
  420. writel (ed, &ohci->regs->ed_bulkhead);
  421. } else {
  422. ohci->ed_bulktail->hwNextED = ohci_cpu_to_le32 ((unsigned long)ed);
  423. }
  424. ed->ed_prev = ohci->ed_bulktail;
  425. if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
  426. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  427. ohci->hc_control |= OHCI_CTRL_BLE;
  428. writel (ohci->hc_control, &ohci->regs->control);
  429. }
  430. ohci->ed_bulktail = edi;
  431. break;
  432. }
  433. return 0;
  434. }
  435. /*-------------------------------------------------------------------------*/
  436. /* unlink an ed from one of the HC chains.
  437. * just the link to the ed is unlinked.
  438. * the link from the ed still points to another operational ed or 0
  439. * so the HC can eventually finish the processing of the unlinked ed */
  440. static int ep_unlink (ohci_t *ohci, ed_t *edi)
  441. {
  442. volatile ed_t *ed = edi;
  443. ed->hwINFO |= ohci_cpu_to_le32 (OHCI_ED_SKIP);
  444. switch (ed->type) {
  445. case PIPE_CONTROL:
  446. if (ed->ed_prev == NULL) {
  447. if (!ed->hwNextED) {
  448. ohci->hc_control &= ~OHCI_CTRL_CLE;
  449. writel (ohci->hc_control, &ohci->regs->control);
  450. }
  451. writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
  452. } else {
  453. ed->ed_prev->hwNextED = ed->hwNextED;
  454. }
  455. if (ohci->ed_controltail == ed) {
  456. ohci->ed_controltail = ed->ed_prev;
  457. } else {
  458. ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  459. }
  460. break;
  461. case PIPE_BULK:
  462. if (ed->ed_prev == NULL) {
  463. if (!ed->hwNextED) {
  464. ohci->hc_control &= ~OHCI_CTRL_BLE;
  465. writel (ohci->hc_control, &ohci->regs->control);
  466. }
  467. writel (ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
  468. } else {
  469. ed->ed_prev->hwNextED = ed->hwNextED;
  470. }
  471. if (ohci->ed_bulktail == ed) {
  472. ohci->ed_bulktail = ed->ed_prev;
  473. } else {
  474. ((ed_t *)ohci_cpu_to_le32 (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  475. }
  476. break;
  477. }
  478. ed->state = ED_UNLINK;
  479. return 0;
  480. }
  481. /*-------------------------------------------------------------------------*/
  482. /* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
  483. * but the USB stack is a little bit stateless so we do it at every transaction
  484. * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
  485. * in all other cases the state is left unchanged
  486. * the ed info fields are setted anyway even though most of them should not change */
  487. static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
  488. {
  489. td_t *td;
  490. ed_t *ed_ret;
  491. volatile ed_t *ed;
  492. ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
  493. (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
  494. if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
  495. err("ep_add_ed: pending delete");
  496. /* pending delete request */
  497. return NULL;
  498. }
  499. if (ed->state == ED_NEW) {
  500. ed->hwINFO = ohci_cpu_to_le32 (OHCI_ED_SKIP); /* skip ed */
  501. /* dummy td; end of td list for ed */
  502. td = td_alloc (usb_dev);
  503. ed->hwTailP = ohci_cpu_to_le32 ((unsigned long)td);
  504. ed->hwHeadP = ed->hwTailP;
  505. ed->state = ED_UNLINK;
  506. ed->type = usb_pipetype (pipe);
  507. ohci_dev.ed_cnt++;
  508. }
  509. ed->hwINFO = ohci_cpu_to_le32 (usb_pipedevice (pipe)
  510. | usb_pipeendpoint (pipe) << 7
  511. | (usb_pipeisoc (pipe)? 0x8000: 0)
  512. | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
  513. | (usb_dev->speed == USB_SPEED_LOW) << 13
  514. | usb_maxpacket (usb_dev, pipe) << 16);
  515. return ed_ret;
  516. }
  517. /*-------------------------------------------------------------------------*
  518. * TD handling functions
  519. *-------------------------------------------------------------------------*/
  520. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  521. static void td_fill (ohci_t *ohci, unsigned int info,
  522. void *data, int len,
  523. struct usb_device *dev, int index, urb_priv_t *urb_priv)
  524. {
  525. volatile td_t *td, *td_pt;
  526. #ifdef OHCI_FILL_TRACE
  527. int i;
  528. #endif
  529. if (index > urb_priv->length) {
  530. err("index > length");
  531. return;
  532. }
  533. /* use this td as the next dummy */
  534. td_pt = urb_priv->td [index];
  535. td_pt->hwNextTD = 0;
  536. /* fill the old dummy TD */
  537. td = urb_priv->td [index] = (td_t *)(ohci_cpu_to_le32 (urb_priv->ed->hwTailP) & ~0xf);
  538. td->ed = urb_priv->ed;
  539. td->next_dl_td = NULL;
  540. td->index = index;
  541. td->data = (__u32)data;
  542. #ifdef OHCI_FILL_TRACE
  543. if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
  544. for (i = 0; i < len; i++)
  545. printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
  546. printf("\n");
  547. }
  548. #endif
  549. if (!len)
  550. data = 0;
  551. td->hwINFO = ohci_cpu_to_le32 (info);
  552. td->hwCBP = ohci_cpu_to_le32 ((unsigned long)data);
  553. if (data)
  554. td->hwBE = ohci_cpu_to_le32 ((unsigned long)(data + len - 1));
  555. else
  556. td->hwBE = 0;
  557. td->hwNextTD = ohci_cpu_to_le32 ((unsigned long)td_pt);
  558. /* append to queue */
  559. td->ed->hwTailP = td->hwNextTD;
  560. }
  561. /*-------------------------------------------------------------------------*/
  562. /* prepare all TDs of a transfer */
  563. static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
  564. int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
  565. {
  566. ohci_t *ohci = &gohci;
  567. int data_len = transfer_len;
  568. void *data;
  569. int cnt = 0;
  570. __u32 info = 0;
  571. unsigned int toggle = 0;
  572. /* OHCI handles the DATA-toggles itself, we just use the
  573. USB-toggle bits for resetting */
  574. if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
  575. toggle = TD_T_TOGGLE;
  576. } else {
  577. toggle = TD_T_DATA0;
  578. usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
  579. }
  580. urb->td_cnt = 0;
  581. if (data_len)
  582. data = buffer;
  583. else
  584. data = 0;
  585. switch (usb_pipetype (pipe)) {
  586. case PIPE_BULK:
  587. info = usb_pipeout (pipe)?
  588. TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
  589. while(data_len > 4096) {
  590. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
  591. data += 4096; data_len -= 4096; cnt++;
  592. }
  593. info = usb_pipeout (pipe)?
  594. TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
  595. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
  596. cnt++;
  597. if (!ohci->sleeping)
  598. writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
  599. break;
  600. case PIPE_CONTROL:
  601. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  602. td_fill (ohci, info, setup, 8, dev, cnt++, urb);
  603. if (data_len > 0) {
  604. info = usb_pipeout (pipe)?
  605. TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
  606. /* NOTE: mishandles transfers >8K, some >4K */
  607. td_fill (ohci, info, data, data_len, dev, cnt++, urb);
  608. }
  609. info = usb_pipeout (pipe)?
  610. TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
  611. td_fill (ohci, info, data, 0, dev, cnt++, urb);
  612. if (!ohci->sleeping)
  613. writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
  614. break;
  615. }
  616. if (urb->length != cnt)
  617. dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
  618. }
  619. /*-------------------------------------------------------------------------*
  620. * Done List handling functions
  621. *-------------------------------------------------------------------------*/
  622. /* calculate the transfer length and update the urb */
  623. static void dl_transfer_length(td_t * td)
  624. {
  625. __u32 tdBE, tdCBP;
  626. urb_priv_t *lurb_priv = &urb_priv;
  627. tdBE = ohci_cpu_to_le32 (td->hwBE);
  628. tdCBP = ohci_cpu_to_le32 (td->hwCBP);
  629. if (!(usb_pipecontrol(lurb_priv->pipe) &&
  630. ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
  631. if (tdBE != 0) {
  632. if (td->hwCBP == 0)
  633. lurb_priv->actual_length += tdBE - td->data + 1;
  634. else
  635. lurb_priv->actual_length += tdCBP - td->data;
  636. }
  637. }
  638. }
  639. /*-------------------------------------------------------------------------*/
  640. /* replies to the request have to be on a FIFO basis so
  641. * we reverse the reversed done-list */
  642. static td_t * dl_reverse_done_list (ohci_t *ohci)
  643. {
  644. __u32 td_list_hc;
  645. td_t *td_rev = NULL;
  646. td_t *td_list = NULL;
  647. urb_priv_t *lurb_priv = NULL;
  648. td_list_hc = ohci_cpu_to_le32 (ohci->hcca->done_head) & 0xfffffff0;
  649. ohci->hcca->done_head = 0;
  650. while (td_list_hc) {
  651. td_list = (td_t *)td_list_hc;
  652. if (TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO))) {
  653. lurb_priv = &urb_priv;
  654. dbg(" USB-error/status: %x : %p",
  655. TD_CC_GET (ohci_cpu_to_le32 (td_list->hwINFO)), td_list);
  656. if (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x1)) {
  657. if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
  658. td_list->ed->hwHeadP =
  659. (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & ohci_cpu_to_le32 (0xfffffff0)) |
  660. (td_list->ed->hwHeadP & ohci_cpu_to_le32 (0x2));
  661. lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
  662. } else
  663. td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
  664. }
  665. td_list->hwNextTD = 0;
  666. }
  667. td_list->next_dl_td = td_rev;
  668. td_rev = td_list;
  669. td_list_hc = ohci_cpu_to_le32 (td_list->hwNextTD) & 0xfffffff0;
  670. }
  671. return td_list;
  672. }
  673. /*-------------------------------------------------------------------------*/
  674. /* td done list */
  675. static int dl_done_list (ohci_t *ohci, td_t *td_list)
  676. {
  677. td_t *td_list_next = NULL;
  678. ed_t *ed;
  679. int cc = 0;
  680. int stat = 0;
  681. /* urb_t *urb; */
  682. urb_priv_t *lurb_priv;
  683. __u32 tdINFO, edHeadP, edTailP;
  684. while (td_list) {
  685. td_list_next = td_list->next_dl_td;
  686. lurb_priv = &urb_priv;
  687. tdINFO = ohci_cpu_to_le32 (td_list->hwINFO);
  688. ed = td_list->ed;
  689. dl_transfer_length(td_list);
  690. /* error code of transfer */
  691. cc = TD_CC_GET (tdINFO);
  692. if (++(lurb_priv->td_cnt) == lurb_priv->length) {
  693. if ((ed->state & (ED_OPER | ED_UNLINK))
  694. && (lurb_priv->state != URB_DEL)) {
  695. dbg("ConditionCode %#x", cc);
  696. stat = cc_to_error[cc];
  697. urb_finished = 1;
  698. }
  699. }
  700. if (ed->state != ED_NEW) {
  701. edHeadP = ohci_cpu_to_le32 (ed->hwHeadP) & 0xfffffff0;
  702. edTailP = ohci_cpu_to_le32 (ed->hwTailP);
  703. /* unlink eds if they are not busy */
  704. if ((edHeadP == edTailP) && (ed->state == ED_OPER))
  705. ep_unlink (ohci, ed);
  706. }
  707. td_list = td_list_next;
  708. }
  709. return stat;
  710. }
  711. /*-------------------------------------------------------------------------*
  712. * Virtual Root Hub
  713. *-------------------------------------------------------------------------*/
  714. #include <usbroothubdes.h>
  715. /* Hub class-specific descriptor is constructed dynamically */
  716. /*-------------------------------------------------------------------------*/
  717. #define OK(x) len = (x); break
  718. #ifdef DEBUG
  719. #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
  720. #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
  721. #else
  722. #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
  723. #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
  724. #endif
  725. #define RD_RH_STAT roothub_status(&gohci)
  726. #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
  727. /* request to virtual root hub */
  728. int rh_check_port_status(ohci_t *controller)
  729. {
  730. __u32 temp, ndp, i;
  731. int res;
  732. res = -1;
  733. temp = roothub_a (controller);
  734. ndp = (temp & RH_A_NDP);
  735. for (i = 0; i < ndp; i++) {
  736. temp = roothub_portstatus (controller, i);
  737. /* check for a device disconnect */
  738. if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
  739. (RH_PS_PESC | RH_PS_CSC)) &&
  740. ((temp & RH_PS_CCS) == 0)) {
  741. res = i;
  742. break;
  743. }
  744. }
  745. return res;
  746. }
  747. static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
  748. void *buffer, int transfer_len, struct devrequest *cmd)
  749. {
  750. void * data = buffer;
  751. int leni = transfer_len;
  752. int len = 0;
  753. int stat = 0;
  754. __u32 datab[4];
  755. __u8 *data_buf = (__u8 *)datab;
  756. __u16 bmRType_bReq;
  757. __u16 wValue;
  758. __u16 wIndex;
  759. __u16 wLength;
  760. #ifdef DEBUG
  761. urb_priv.actual_length = 0;
  762. pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
  763. #endif
  764. if (usb_pipeint(pipe)) {
  765. info("Root-Hub submit IRQ: NOT implemented");
  766. return 0;
  767. }
  768. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  769. wValue = m16_swap (cmd->value);
  770. wIndex = m16_swap (cmd->index);
  771. wLength = m16_swap (cmd->length);
  772. info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
  773. dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
  774. switch (bmRType_bReq) {
  775. /* Request Destination:
  776. without flags: Device,
  777. RH_INTERFACE: interface,
  778. RH_ENDPOINT: endpoint,
  779. RH_CLASS means HUB here,
  780. RH_OTHER | RH_CLASS almost ever means HUB_PORT here
  781. */
  782. case RH_GET_STATUS:
  783. *(__u16 *) data_buf = m16_swap (1); OK (2);
  784. case RH_GET_STATUS | RH_INTERFACE:
  785. *(__u16 *) data_buf = m16_swap (0); OK (2);
  786. case RH_GET_STATUS | RH_ENDPOINT:
  787. *(__u16 *) data_buf = m16_swap (0); OK (2);
  788. case RH_GET_STATUS | RH_CLASS:
  789. *(__u32 *) data_buf = m32_swap (
  790. RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
  791. OK (4);
  792. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  793. *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
  794. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  795. switch (wValue) {
  796. case (RH_ENDPOINT_STALL): OK (0);
  797. }
  798. break;
  799. case RH_CLEAR_FEATURE | RH_CLASS:
  800. switch (wValue) {
  801. case RH_C_HUB_LOCAL_POWER:
  802. OK(0);
  803. case (RH_C_HUB_OVER_CURRENT):
  804. WR_RH_STAT(RH_HS_OCIC); OK (0);
  805. }
  806. break;
  807. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  808. switch (wValue) {
  809. case (RH_PORT_ENABLE):
  810. WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
  811. case (RH_PORT_SUSPEND):
  812. WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
  813. case (RH_PORT_POWER):
  814. WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
  815. case (RH_C_PORT_CONNECTION):
  816. WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
  817. case (RH_C_PORT_ENABLE):
  818. WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
  819. case (RH_C_PORT_SUSPEND):
  820. WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
  821. case (RH_C_PORT_OVER_CURRENT):
  822. WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
  823. case (RH_C_PORT_RESET):
  824. WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
  825. }
  826. break;
  827. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  828. switch (wValue) {
  829. case (RH_PORT_SUSPEND):
  830. WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
  831. case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
  832. if (RD_RH_PORTSTAT & RH_PS_CCS)
  833. WR_RH_PORTSTAT (RH_PS_PRS);
  834. OK (0);
  835. case (RH_PORT_POWER):
  836. WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
  837. case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
  838. if (RD_RH_PORTSTAT & RH_PS_CCS)
  839. WR_RH_PORTSTAT (RH_PS_PES );
  840. OK (0);
  841. }
  842. break;
  843. case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
  844. case RH_GET_DESCRIPTOR:
  845. switch ((wValue & 0xff00) >> 8) {
  846. case (0x01): /* device descriptor */
  847. len = min_t(unsigned int,
  848. leni,
  849. min_t(unsigned int,
  850. sizeof (root_hub_dev_des),
  851. wLength));
  852. data_buf = root_hub_dev_des; OK(len);
  853. case (0x02): /* configuration descriptor */
  854. len = min_t(unsigned int,
  855. leni,
  856. min_t(unsigned int,
  857. sizeof (root_hub_config_des),
  858. wLength));
  859. data_buf = root_hub_config_des; OK(len);
  860. case (0x03): /* string descriptors */
  861. if(wValue==0x0300) {
  862. len = min_t(unsigned int,
  863. leni,
  864. min_t(unsigned int,
  865. sizeof (root_hub_str_index0),
  866. wLength));
  867. data_buf = root_hub_str_index0;
  868. OK(len);
  869. }
  870. if(wValue==0x0301) {
  871. len = min_t(unsigned int,
  872. leni,
  873. min_t(unsigned int,
  874. sizeof (root_hub_str_index1),
  875. wLength));
  876. data_buf = root_hub_str_index1;
  877. OK(len);
  878. }
  879. default:
  880. stat = USB_ST_STALLED;
  881. }
  882. break;
  883. case RH_GET_DESCRIPTOR | RH_CLASS:
  884. {
  885. __u32 temp = roothub_a (&gohci);
  886. data_buf [0] = 9; /* min length; */
  887. data_buf [1] = 0x29;
  888. data_buf [2] = temp & RH_A_NDP;
  889. data_buf [3] = 0;
  890. if (temp & RH_A_PSM) /* per-port power switching? */
  891. data_buf [3] |= 0x1;
  892. if (temp & RH_A_NOCP) /* no overcurrent reporting? */
  893. data_buf [3] |= 0x10;
  894. else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
  895. data_buf [3] |= 0x8;
  896. /* corresponds to data_buf[4-7] */
  897. datab [1] = 0;
  898. data_buf [5] = (temp & RH_A_POTPGT) >> 24;
  899. temp = roothub_b (&gohci);
  900. data_buf [7] = temp & RH_B_DR;
  901. if (data_buf [2] < 7) {
  902. data_buf [8] = 0xff;
  903. } else {
  904. data_buf [0] += 2;
  905. data_buf [8] = (temp & RH_B_DR) >> 8;
  906. data_buf [10] = data_buf [9] = 0xff;
  907. }
  908. len = min_t(unsigned int, leni,
  909. min_t(unsigned int, data_buf [0], wLength));
  910. OK (len);
  911. }
  912. case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
  913. case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
  914. default:
  915. dbg ("unsupported root hub command");
  916. stat = USB_ST_STALLED;
  917. }
  918. #ifdef DEBUG
  919. ohci_dump_roothub (&gohci, 1);
  920. #endif
  921. len = min_t(int, len, leni);
  922. if (data != data_buf)
  923. memcpy (data, data_buf, len);
  924. dev->act_len = len;
  925. dev->status = stat;
  926. #ifdef DEBUG
  927. if (transfer_len)
  928. urb_priv.actual_length = transfer_len;
  929. pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
  930. #endif
  931. return stat;
  932. }
  933. /*-------------------------------------------------------------------------*/
  934. /* common code for handling submit messages - used for all but root hub */
  935. /* accesses. */
  936. int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  937. int transfer_len, struct devrequest *setup, int interval)
  938. {
  939. int stat = 0;
  940. int maxsize = usb_maxpacket(dev, pipe);
  941. int timeout;
  942. /* device pulled? Shortcut the action. */
  943. if (devgone == dev) {
  944. dev->status = USB_ST_CRC_ERR;
  945. return 0;
  946. }
  947. #ifdef DEBUG
  948. urb_priv.actual_length = 0;
  949. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  950. #endif
  951. if (!maxsize) {
  952. err("submit_common_message: pipesize for pipe %lx is zero",
  953. pipe);
  954. return -1;
  955. }
  956. if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
  957. err("sohci_submit_job failed");
  958. return -1;
  959. }
  960. /* allow more time for a BULK device to react - some are slow */
  961. #define BULK_TO 5000 /* timeout in milliseconds */
  962. if (usb_pipebulk(pipe))
  963. timeout = BULK_TO;
  964. else
  965. timeout = 100;
  966. /* wait for it to complete */
  967. for (;;) {
  968. /* check whether the controller is done */
  969. stat = hc_interrupt();
  970. if (stat < 0) {
  971. stat = USB_ST_CRC_ERR;
  972. break;
  973. }
  974. /* NOTE: since we are not interrupt driven in U-Boot and always
  975. * handle only one URB at a time, we cannot assume the
  976. * transaction finished on the first successful return from
  977. * hc_interrupt().. unless the flag for current URB is set,
  978. * meaning that all TD's to/from device got actually
  979. * transferred and processed. If the current URB is not
  980. * finished we need to re-iterate this loop so as
  981. * hc_interrupt() gets called again as there needs to be some
  982. * more TD's to process still */
  983. if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
  984. /* 0xff is returned for an SF-interrupt */
  985. break;
  986. }
  987. if (--timeout) {
  988. mdelay(1);
  989. if (!urb_finished)
  990. dbg("\%");
  991. } else {
  992. err("CTL:TIMEOUT ");
  993. dbg("submit_common_msg: TO status %x\n", stat);
  994. stat = USB_ST_CRC_ERR;
  995. urb_finished = 1;
  996. break;
  997. }
  998. }
  999. #if 0
  1000. /* we got an Root Hub Status Change interrupt */
  1001. if (got_rhsc) {
  1002. #ifdef DEBUG
  1003. ohci_dump_roothub (&gohci, 1);
  1004. #endif
  1005. got_rhsc = 0;
  1006. /* abuse timeout */
  1007. timeout = rh_check_port_status(&gohci);
  1008. if (timeout >= 0) {
  1009. #if 0 /* this does nothing useful, but leave it here in case that changes */
  1010. /* the called routine adds 1 to the passed value */
  1011. usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
  1012. #endif
  1013. /*
  1014. * XXX
  1015. * This is potentially dangerous because it assumes
  1016. * that only one device is ever plugged in!
  1017. */
  1018. devgone = dev;
  1019. }
  1020. }
  1021. #endif
  1022. dev->status = stat;
  1023. dev->act_len = transfer_len;
  1024. #ifdef DEBUG
  1025. pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
  1026. #endif
  1027. /* free TDs in urb_priv */
  1028. urb_free_priv (&urb_priv);
  1029. return 0;
  1030. }
  1031. /* submit routines called from usb.c */
  1032. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1033. int transfer_len)
  1034. {
  1035. info("submit_bulk_msg");
  1036. return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
  1037. }
  1038. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1039. int transfer_len, struct devrequest *setup)
  1040. {
  1041. int maxsize = usb_maxpacket(dev, pipe);
  1042. info("submit_control_msg");
  1043. #ifdef DEBUG
  1044. urb_priv.actual_length = 0;
  1045. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1046. #endif
  1047. if (!maxsize) {
  1048. err("submit_control_message: pipesize for pipe %lx is zero",
  1049. pipe);
  1050. return -1;
  1051. }
  1052. if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
  1053. gohci.rh.dev = dev;
  1054. /* root hub - redirect */
  1055. return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
  1056. setup);
  1057. }
  1058. return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
  1059. }
  1060. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1061. int transfer_len, int interval)
  1062. {
  1063. info("submit_int_msg");
  1064. return -1;
  1065. }
  1066. /*-------------------------------------------------------------------------*
  1067. * HC functions
  1068. *-------------------------------------------------------------------------*/
  1069. /* reset the HC and BUS */
  1070. static int hc_reset (ohci_t *ohci)
  1071. {
  1072. int timeout = 30;
  1073. int smm_timeout = 50; /* 0,5 sec */
  1074. if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
  1075. writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
  1076. info("USB HC TakeOver from SMM");
  1077. while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
  1078. mdelay (10);
  1079. if (--smm_timeout == 0) {
  1080. err("USB HC TakeOver failed!");
  1081. return -1;
  1082. }
  1083. }
  1084. }
  1085. /* Disable HC interrupts */
  1086. writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
  1087. dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
  1088. ohci->slot_name,
  1089. readl (&ohci->regs->control));
  1090. /* Reset USB (needed by some controllers) */
  1091. ohci->hc_control = 0;
  1092. writel (ohci->hc_control, &ohci->regs->control);
  1093. /* HC Reset requires max 10 us delay */
  1094. writel (OHCI_HCR, &ohci->regs->cmdstatus);
  1095. while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  1096. if (--timeout == 0) {
  1097. err("USB HC reset timed out!");
  1098. return -1;
  1099. }
  1100. udelay (1);
  1101. }
  1102. return 0;
  1103. }
  1104. /*-------------------------------------------------------------------------*/
  1105. /* Start an OHCI controller, set the BUS operational
  1106. * enable interrupts
  1107. * connect the virtual root hub */
  1108. static int hc_start (ohci_t * ohci)
  1109. {
  1110. __u32 mask;
  1111. unsigned int fminterval;
  1112. ohci->disabled = 1;
  1113. /* Tell the controller where the control and bulk lists are
  1114. * The lists are empty now. */
  1115. writel (0, &ohci->regs->ed_controlhead);
  1116. writel (0, &ohci->regs->ed_bulkhead);
  1117. writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
  1118. fminterval = 0x2edf;
  1119. writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
  1120. fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
  1121. writel (fminterval, &ohci->regs->fminterval);
  1122. writel (0x628, &ohci->regs->lsthresh);
  1123. /* start controller operations */
  1124. ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
  1125. ohci->disabled = 0;
  1126. writel (ohci->hc_control, &ohci->regs->control);
  1127. /* disable all interrupts */
  1128. mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
  1129. OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
  1130. OHCI_INTR_OC | OHCI_INTR_MIE);
  1131. writel (mask, &ohci->regs->intrdisable);
  1132. /* clear all interrupts */
  1133. mask &= ~OHCI_INTR_MIE;
  1134. writel (mask, &ohci->regs->intrstatus);
  1135. /* Choose the interrupts we care about now - but w/o MIE */
  1136. mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
  1137. writel (mask, &ohci->regs->intrenable);
  1138. #ifdef OHCI_USE_NPS
  1139. /* required for AMD-756 and some Mac platforms */
  1140. writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
  1141. &ohci->regs->roothub.a);
  1142. writel (RH_HS_LPSC, &ohci->regs->roothub.status);
  1143. #endif /* OHCI_USE_NPS */
  1144. /* POTPGT delay is bits 24-31, in 2 ms units. */
  1145. mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
  1146. /* connect the virtual root hub */
  1147. ohci->rh.devnum = 0;
  1148. return 0;
  1149. }
  1150. /*-------------------------------------------------------------------------*/
  1151. /* an interrupt happens */
  1152. static int
  1153. hc_interrupt (void)
  1154. {
  1155. ohci_t *ohci = &gohci;
  1156. struct ohci_regs *regs = ohci->regs;
  1157. int ints;
  1158. int stat = -1;
  1159. if ((ohci->hcca->done_head != 0) &&
  1160. !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) {
  1161. ints = OHCI_INTR_WDH;
  1162. } else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
  1163. ohci->disabled++;
  1164. err ("%s device removed!", ohci->slot_name);
  1165. return -1;
  1166. } else if ((ints &= readl (&regs->intrenable)) == 0) {
  1167. dbg("hc_interrupt: returning..\n");
  1168. return 0xff;
  1169. }
  1170. /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
  1171. if (ints & OHCI_INTR_RHSC) {
  1172. got_rhsc = 1;
  1173. stat = 0xff;
  1174. }
  1175. if (ints & OHCI_INTR_UE) {
  1176. ohci->disabled++;
  1177. err ("OHCI Unrecoverable Error, controller usb-%s disabled",
  1178. ohci->slot_name);
  1179. /* e.g. due to PCI Master/Target Abort */
  1180. #ifdef DEBUG
  1181. ohci_dump (ohci, 1);
  1182. #endif
  1183. /* FIXME: be optimistic, hope that bug won't repeat often. */
  1184. /* Make some non-interrupt context restart the controller. */
  1185. /* Count and limit the retries though; either hardware or */
  1186. /* software errors can go forever... */
  1187. hc_reset (ohci);
  1188. return -1;
  1189. }
  1190. if (ints & OHCI_INTR_WDH) {
  1191. writel (OHCI_INTR_WDH, &regs->intrdisable);
  1192. stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
  1193. writel (OHCI_INTR_WDH, &regs->intrenable);
  1194. }
  1195. if (ints & OHCI_INTR_SO) {
  1196. dbg("USB Schedule overrun\n");
  1197. writel (OHCI_INTR_SO, &regs->intrenable);
  1198. stat = -1;
  1199. }
  1200. /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
  1201. if (ints & OHCI_INTR_SF) {
  1202. unsigned int frame = ohci_cpu_to_le16 (ohci->hcca->frame_no) & 1;
  1203. mdelay(1);
  1204. writel (OHCI_INTR_SF, &regs->intrdisable);
  1205. if (ohci->ed_rm_list[frame] != NULL)
  1206. writel (OHCI_INTR_SF, &regs->intrenable);
  1207. stat = 0xff;
  1208. }
  1209. writel (ints, &regs->intrstatus);
  1210. return stat;
  1211. }
  1212. /*-------------------------------------------------------------------------*/
  1213. /*-------------------------------------------------------------------------*/
  1214. /* De-allocate all resources.. */
  1215. static void hc_release_ohci (ohci_t *ohci)
  1216. {
  1217. dbg ("USB HC release ohci usb-%s", ohci->slot_name);
  1218. if (!ohci->disabled)
  1219. hc_reset (ohci);
  1220. }
  1221. /*-------------------------------------------------------------------------*/
  1222. /*
  1223. * low level initalisation routine, called from usb.c
  1224. */
  1225. static char ohci_inited = 0;
  1226. int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
  1227. {
  1228. /* Set the USB Clock */
  1229. *(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK;
  1230. #ifdef CONFIG_PSC3_USB /* USB is using the alternate configuration */
  1231. /* remove all PSC3 USB bits first before ORing in ours */
  1232. *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00804f00;
  1233. #else
  1234. /* remove all USB bits first before ORing in ours */
  1235. *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000;
  1236. #endif
  1237. /* Activate USB port */
  1238. *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG;
  1239. memset (&gohci, 0, sizeof (ohci_t));
  1240. memset (&urb_priv, 0, sizeof (urb_priv_t));
  1241. /* align the storage */
  1242. if ((__u32)&ghcca[0] & 0xff) {
  1243. err("HCCA not aligned!!");
  1244. return -1;
  1245. }
  1246. phcca = &ghcca[0];
  1247. info("aligned ghcca %p", phcca);
  1248. memset(&ohci_dev, 0, sizeof(struct ohci_device));
  1249. if ((__u32)&ohci_dev.ed[0] & 0x7) {
  1250. err("EDs not aligned!!");
  1251. return -1;
  1252. }
  1253. memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
  1254. if ((__u32)gtd & 0x7) {
  1255. err("TDs not aligned!!");
  1256. return -1;
  1257. }
  1258. ptd = gtd;
  1259. gohci.hcca = phcca;
  1260. memset (phcca, 0, sizeof (struct ohci_hcca));
  1261. gohci.disabled = 1;
  1262. gohci.sleeping = 0;
  1263. gohci.irq = -1;
  1264. gohci.regs = (struct ohci_regs *)MPC5XXX_USB;
  1265. gohci.flags = 0;
  1266. gohci.slot_name = "mpc5200";
  1267. if (hc_reset (&gohci) < 0) {
  1268. hc_release_ohci (&gohci);
  1269. return -1;
  1270. }
  1271. if (hc_start (&gohci) < 0) {
  1272. err ("can't start usb-%s", gohci.slot_name);
  1273. hc_release_ohci (&gohci);
  1274. return -1;
  1275. }
  1276. #ifdef DEBUG
  1277. ohci_dump (&gohci, 1);
  1278. #endif
  1279. ohci_inited = 1;
  1280. urb_finished = 1;
  1281. return 0;
  1282. }
  1283. int usb_lowlevel_stop(int index)
  1284. {
  1285. /* this gets called really early - before the controller has */
  1286. /* even been initialized! */
  1287. if (!ohci_inited)
  1288. return 0;
  1289. /* TODO release any interrupts, etc. */
  1290. /* call hc_release_ohci() here ? */
  1291. hc_reset (&gohci);
  1292. return 0;
  1293. }
  1294. #endif /* CONFIG_USB_OHCI */