ti816x_evm.h 2.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * ti816x_evm.h
  4. *
  5. * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
  6. * Antoine Tenart, <atenart@adeneo-embedded.com>
  7. */
  8. #ifndef __CONFIG_TI816X_EVM_H
  9. #define __CONFIG_TI816X_EVM_H
  10. #include <configs/ti_armv7_omap.h>
  11. #include <asm/arch/omap.h>
  12. #define CONFIG_EXTRA_ENV_SETTINGS \
  13. DEFAULT_LINUX_BOOT_ENV \
  14. "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  15. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  16. #define CONFIG_BOOTCOMMAND \
  17. "mmc rescan;" \
  18. "fatload mmc 0 ${loadaddr} uImage;" \
  19. "bootm ${loadaddr}" \
  20. /* Clock Defines */
  21. #define V_OSCK 24000000 /* Clock output from T2 */
  22. #define V_SCLK (V_OSCK >> 1)
  23. #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
  24. #define CONFIG_SYS_SDRAM_BASE 0x80000000
  25. /**
  26. * Platform/Board specific defs
  27. */
  28. #define CONFIG_SYS_CLK_FREQ 27000000
  29. #define CONFIG_SYS_TIMERBASE 0x4802E000
  30. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  31. /*
  32. * NS16550 Configuration
  33. */
  34. #define CONFIG_SYS_NS16550_SERIAL
  35. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  36. #define CONFIG_SYS_NS16550_CLK (48000000)
  37. #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
  38. /* allow overwriting serial config and ethaddr */
  39. /*
  40. * GPMC NAND block. We support 1 device and the physical address to
  41. * access CS0 at is 0x8000000.
  42. */
  43. #define CONFIG_SYS_NAND_BASE 0x8000000
  44. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  45. /* NAND: SPL related configs */
  46. /* NAND: device related configs */
  47. /* NAND: driver related configs */
  48. #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
  49. 10, 11, 12, 13, 14, 15, 16, 17, \
  50. 18, 19, 20, 21, 22, 23, 24, 25, \
  51. 26, 27, 28, 29, 30, 31, 32, 33, \
  52. 34, 35, 36, 37, 38, 39, 40, 41, \
  53. 42, 43, 44, 45, 46, 47, 48, 49, \
  54. 50, 51, 52, 53, 54, 55, 56, 57, }
  55. #define CONFIG_SYS_NAND_ECCSIZE 512
  56. #define CONFIG_SYS_NAND_ECCBYTES 14
  57. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
  58. /* SPL */
  59. /* Defines for SPL */
  60. #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
  61. CONFIG_SPL_TEXT_BASE)
  62. #define CONFIG_NET_RETRY_COUNT 10
  63. /* Since SPL did pll and ddr initialization for us,
  64. * we don't need to do it twice.
  65. */
  66. /*
  67. * Disable MMC DM for SPL build and can be re-enabled after adding
  68. * DM support in SPL
  69. */
  70. #ifdef CONFIG_SPL_BUILD
  71. #undef CONFIG_DM_MMC
  72. #undef CONFIG_TIMER
  73. #endif
  74. #endif