socfpga_common.h 5.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2012 Altera Corporation <www.altera.com>
  4. */
  5. #ifndef __CONFIG_SOCFPGA_COMMON_H__
  6. #define __CONFIG_SOCFPGA_COMMON_H__
  7. #include <linux/stringify.h>
  8. /*
  9. * High level configuration
  10. */
  11. #define CONFIG_CLOCKS
  12. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  13. /*
  14. * Memory configurations
  15. */
  16. #define PHYS_SDRAM_1 0x0
  17. #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  18. #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
  19. #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
  20. #define CONFIG_SPL_PAD_TO 0x10000
  21. #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  22. #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
  23. #define CONFIG_SPL_PAD_TO 0x40000
  24. /* SPL memory allocation configuration, this is for FAT implementation */
  25. #ifndef CONFIG_SYS_SPL_MALLOC_SIZE
  26. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
  27. #endif
  28. #define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
  29. CONFIG_SYS_SPL_MALLOC_SIZE)
  30. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
  31. CONFIG_SYS_INIT_RAM_SIZE)
  32. #endif
  33. /*
  34. * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
  35. * SRAM as bootcounter storage. Make sure to not put the stack directly
  36. * at this address to not overwrite the bootcounter by checking, if the
  37. * bootcounter address is located in the internal SRAM.
  38. */
  39. #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
  40. (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
  41. CONFIG_SYS_INIT_RAM_SIZE)))
  42. #define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
  43. #else
  44. #define CONFIG_SPL_STACK \
  45. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
  46. #endif
  47. /*
  48. * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
  49. * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
  50. * in U-Boot pre-reloc is higher than in SPL.
  51. */
  52. #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
  53. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
  54. #else
  55. #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
  56. #endif
  57. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  58. /*
  59. * U-Boot general configurations
  60. */
  61. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
  62. /* Print buffer size */
  63. #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
  64. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  65. /* Boot argument buffer size */
  66. /*
  67. * Cache
  68. */
  69. #define CONFIG_SYS_L2_PL310
  70. #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
  71. /*
  72. * Ethernet on SoC (EMAC)
  73. */
  74. #ifdef CONFIG_CMD_NET
  75. #define CONFIG_DW_ALTDESCRIPTOR
  76. #endif
  77. /*
  78. * FPGA Driver
  79. */
  80. #ifdef CONFIG_CMD_FPGA
  81. #define CONFIG_FPGA_COUNT 1
  82. #endif
  83. /*
  84. * L4 OSC1 Timer 0
  85. */
  86. #ifndef CONFIG_TIMER
  87. #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
  88. #define CONFIG_SYS_TIMER_COUNTS_DOWN
  89. #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
  90. #ifndef CONFIG_SYS_TIMER_RATE
  91. #define CONFIG_SYS_TIMER_RATE 25000000
  92. #endif
  93. #endif
  94. /*
  95. * L4 Watchdog
  96. */
  97. #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
  98. #define CONFIG_DW_WDT_CLOCK_KHZ 25000
  99. /*
  100. * MMC Driver
  101. */
  102. #ifdef CONFIG_CMD_MMC
  103. /* FIXME */
  104. /* using smaller max blk cnt to avoid flooding the limited stack we have */
  105. #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
  106. #endif
  107. /*
  108. * NAND Support
  109. */
  110. #ifdef CONFIG_NAND_DENALI
  111. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  112. #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
  113. #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
  114. #endif
  115. /*
  116. * QSPI support
  117. */
  118. /* QSPI reference clock */
  119. #ifndef __ASSEMBLY__
  120. unsigned int cm_get_qspi_controller_clk_hz(void);
  121. #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
  122. #endif
  123. /*
  124. * USB
  125. */
  126. /*
  127. * USB Gadget (DFU, UMS)
  128. */
  129. #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
  130. #define DFU_DEFAULT_POLL_TIMEOUT 300
  131. /* USB IDs */
  132. #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
  133. #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
  134. #endif
  135. /*
  136. * U-Boot environment
  137. */
  138. /* Environment for SDMMC boot */
  139. /* Environment for QSPI boot */
  140. /*
  141. * SPL
  142. *
  143. * SRAM Memory layout for gen 5:
  144. *
  145. * 0xFFFF_0000 ...... Start of SRAM
  146. * 0xFFFF_xxxx ...... Top of stack (grows down)
  147. * 0xFFFF_yyyy ...... Global Data
  148. * 0xFFFF_zzzz ...... Malloc area
  149. * 0xFFFF_FFFF ...... End of SRAM
  150. *
  151. * SRAM Memory layout for Arria 10:
  152. * 0xFFE0_0000 ...... Start of SRAM (bottom)
  153. * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
  154. * 0xFFEy_yyyy ...... Global Data
  155. * 0xFFEz_zzzz ...... Malloc area (grows up to top)
  156. * 0xFFE3_FFFF ...... End of SRAM (top)
  157. */
  158. #ifndef CONFIG_SPL_TEXT_BASE
  159. #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
  160. #endif
  161. /* SPL SDMMC boot support */
  162. #ifdef CONFIG_SPL_MMC
  163. #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  164. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  165. #endif
  166. #else
  167. #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
  168. #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
  169. #endif
  170. #endif
  171. /* SPL QSPI boot support */
  172. /* SPL NAND boot support */
  173. /* Extra Environment */
  174. #ifndef CONFIG_SPL_BUILD
  175. #ifdef CONFIG_CMD_DHCP
  176. #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
  177. #else
  178. #define BOOT_TARGET_DEVICES_DHCP(func)
  179. #endif
  180. #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
  181. #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
  182. #else
  183. #define BOOT_TARGET_DEVICES_PXE(func)
  184. #endif
  185. #ifdef CONFIG_CMD_MMC
  186. #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
  187. #else
  188. #define BOOT_TARGET_DEVICES_MMC(func)
  189. #endif
  190. #define BOOT_TARGET_DEVICES(func) \
  191. BOOT_TARGET_DEVICES_MMC(func) \
  192. BOOT_TARGET_DEVICES_PXE(func) \
  193. BOOT_TARGET_DEVICES_DHCP(func)
  194. #include <config_distro_bootcmd.h>
  195. #ifndef CONFIG_EXTRA_ENV_SETTINGS
  196. #define CONFIG_EXTRA_ENV_SETTINGS \
  197. "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
  198. "bootm_size=0xa000000\0" \
  199. "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
  200. "fdt_addr_r=0x02000000\0" \
  201. "scriptaddr=0x02100000\0" \
  202. "pxefile_addr_r=0x02200000\0" \
  203. "ramdisk_addr_r=0x02300000\0" \
  204. "socfpga_legacy_reset_compat=1\0" \
  205. BOOTENV
  206. #endif
  207. #endif
  208. #endif /* __CONFIG_SOCFPGA_COMMON_H__ */