socfpga_arria5_secu1.h 3.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2017-2020 Hitachi Power Grids
  4. *
  5. */
  6. #ifndef __CONFIG_SOCFPGA_SECU1_H__
  7. #define __CONFIG_SOCFPGA_SECU1_H__
  8. #include <asm/arch/base_addr_ac5.h>
  9. #include <linux/stringify.h>
  10. /* Call misc_init_r */
  11. #define CONFIG_MISC_INIT_R
  12. #define CONFIG_HUSH_INIT_VAR
  13. /* Eternal oscillator */
  14. #define CONFIG_SYS_TIMER_RATE 40000000
  15. /* Memory configurations */
  16. #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512MiB on SECU1 */
  17. /*
  18. * We use bootcounter in i2c nvram of the RTC (0x68)
  19. * The offset fopr the bootcounter is 0x9e, which are
  20. * the last two bytes of the 128 bytes large NVRAM in the
  21. * RTC which begin at address 0x20
  22. */
  23. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  24. /* Booting Linux */
  25. #define CONFIG_BOOTFILE "zImage"
  26. #define CONFIG_BOOTCOMMAND \
  27. "setenv bootcmd '" \
  28. "bridge enable; " \
  29. "if test ${bootnum} = \"b\"; " \
  30. "then run _fpga_loadsafe; " \
  31. "else if test ${bootcount} -eq 4; then echo \"Switching copy...\"; setexpr x $bootnum % 2 && setexpr bootnum $x + 1; saveenv; fi; " \
  32. "run _fpga_loaduser; " \
  33. "fi;" \
  34. "echo \"Booting bank $bootnum\" && run userload && run userboot;" \
  35. "' && " \
  36. "setenv altbootcmd 'setenv bootnum b && saveenv && boot;' && " \
  37. "saveenv && saveenv && boot;"
  38. #define CONFIG_SYS_BOOTM_LEN (64 << 20)
  39. /* Environment settings */
  40. /*
  41. * Autoboot
  42. *
  43. * After 45s of inactivity in the prompt, the board will reset.
  44. * Set 'bootretry' in the environment to -1 to disable this behavior
  45. */
  46. #define CONFIG_BOOT_RETRY_TIME 45
  47. #define CONFIG_RESET_TO_RETRY
  48. /*
  49. * FPGA Remote Update related environment
  50. *
  51. * Note that since those commands access the FPGA, the HPS-to-FPGA
  52. * bridges MUST have been previously enabled (for example
  53. * with 'bridge enable').
  54. */
  55. #define FPGA_RMTU_ENV \
  56. "rmtu_page=0xFF29000C\0" \
  57. "rmtu_reconfig=0xFF290018\0" \
  58. "fpga_safebase=0x0\0" \
  59. "fpga_userbase=0x2000000\0" \
  60. "_fpga_loaduser=echo Loading FPGA USER image..." \
  61. " && mw ${rmtu_page} ${fpga_userbase} && mw ${rmtu_reconfig} 1\0" \
  62. "_fpga_loadsafe=echo Loading FPGA SAFE image..." \
  63. " && mw ${rmtu_page} ${fpga_safebase} && mw ${rmtu_reconfig} 1\0" \
  64. #define CONFIG_KM_NEW_ENV \
  65. "newenv=" \
  66. "nand erase 0x100000 0x40000\0"
  67. #define CONFIG_KM_DEF_ENV_BOOTTARGETS \
  68. "release=" \
  69. "run newenv; reset\0" \
  70. "develop=" \
  71. "tftp 0x200000 scripts/develop-secu.txt && env import -t 0x200000 ${filesize} && saveenv && reset\0"
  72. #define CONFIG_EXTRA_ENV_SETTINGS \
  73. FPGA_RMTU_ENV \
  74. CONFIG_KM_DEF_ENV_BOOTTARGETS \
  75. CONFIG_KM_NEW_ENV \
  76. "socfpga_legacy_reset_compat=1\0" \
  77. "altbootcmd=run bootcmd;\0" \
  78. "bootlimit=6\0" \
  79. "bootnum=1\0" \
  80. "bootretry=" __stringify(CONFIG_BOOT_RETRY_TIME) "\0" \
  81. "fdt_addr=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
  82. "load=tftpboot ${loadaddr} u-boot-with-nand-spl.sfp\0" \
  83. "loadaddr=" __stringify(CONFIG_KM_KERNEL_ADDR) "\0" \
  84. "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
  85. "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
  86. "update=nand erase 0x0 0x00100000 && nand write ${loadaddr} 0x0 ${filesize}\0" \
  87. "userload=ubi part nand.ubi &&" \
  88. "ubi check rootfs$bootnum &&" \
  89. "ubi read $fdt_addr dtb$bootnum &&" \
  90. "ubi read $loadaddr kernel$bootnum\0" \
  91. "userboot=setenv bootargs " CONFIG_BOOTARGS \
  92. " ubi.mtd=1 ubi.block=0,rootfs$bootnum root=/dev/ubiblock0_$ubivolid" \
  93. " ro rootfstype=squashfs init=sbin/preinit;" \
  94. "bootz ${loadaddr} - ${fdt_addr}\0" \
  95. "verify=y\0"
  96. /* The rest of the configuration is shared */
  97. #include <configs/socfpga_common.h>
  98. #undef CONFIG_WATCHDOG_TIMEOUT_MSECS
  99. #define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000
  100. #endif /* __CONFIG_SOCFPGA_SECU1_H__ */