ls2080ardb.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2017, 2019-2021 NXP
  4. * Copyright 2015 Freescale Semiconductor
  5. */
  6. #ifndef __LS2_RDB_H
  7. #define __LS2_RDB_H
  8. #include "ls2080a_common.h"
  9. #ifdef CONFIG_FSL_QSPI
  10. #ifdef CONFIG_TARGET_LS2081ARDB
  11. #define CONFIG_QIXIS_I2C_ACCESS
  12. #endif
  13. #endif
  14. #define I2C_MUX_CH_VOL_MONITOR 0xa
  15. #define I2C_VOL_MONITOR_ADDR 0x38
  16. #define CONFIG_VOL_MONITOR_IR36021_READ
  17. #define CONFIG_VOL_MONITOR_IR36021_SET
  18. #define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv"
  19. #ifndef CONFIG_SPL_BUILD
  20. #define CONFIG_VID
  21. #endif
  22. /* step the IR regulator in 5mV increments */
  23. #define IR_VDD_STEP_DOWN 5
  24. #define IR_VDD_STEP_UP 5
  25. /* The lowest and highest voltage allowed for LS2080ARDB */
  26. #define VDD_MV_MIN 819
  27. #define VDD_MV_MAX 1212
  28. #ifndef __ASSEMBLY__
  29. unsigned long get_board_sys_clk(void);
  30. #endif
  31. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  32. #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
  33. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  34. #define SPD_EEPROM_ADDRESS1 0x51
  35. #define SPD_EEPROM_ADDRESS2 0x52
  36. #define SPD_EEPROM_ADDRESS3 0x53
  37. #define SPD_EEPROM_ADDRESS4 0x54
  38. #define SPD_EEPROM_ADDRESS5 0x55
  39. #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
  40. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  41. #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
  42. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  43. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  44. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  45. #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
  46. #endif
  47. /* SATA */
  48. #define CONFIG_SCSI_AHCI_PLAT
  49. #define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
  50. #define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
  51. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  52. #define CONFIG_SYS_SCSI_MAX_LUN 1
  53. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  54. CONFIG_SYS_SCSI_MAX_LUN)
  55. #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
  56. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  57. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  58. #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
  59. #define CONFIG_SYS_NOR0_CSPR \
  60. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  61. CSPR_PORT_SIZE_16 | \
  62. CSPR_MSEL_NOR | \
  63. CSPR_V)
  64. #define CONFIG_SYS_NOR0_CSPR_EARLY \
  65. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
  66. CSPR_PORT_SIZE_16 | \
  67. CSPR_MSEL_NOR | \
  68. CSPR_V)
  69. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
  70. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  71. FTIM0_NOR_TEADC(0x5) | \
  72. FTIM0_NOR_TEAHC(0x5))
  73. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  74. FTIM1_NOR_TRAD_NOR(0x1a) |\
  75. FTIM1_NOR_TSEQRAD_NOR(0x13))
  76. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  77. FTIM2_NOR_TCH(0x4) | \
  78. FTIM2_NOR_TWPH(0x0E) | \
  79. FTIM2_NOR_TWP(0x1c))
  80. #define CONFIG_SYS_NOR_FTIM3 0x04000000
  81. #define CONFIG_SYS_IFC_CCR 0x01000000
  82. #ifdef CONFIG_MTD_NOR_FLASH
  83. #define CONFIG_SYS_FLASH_QUIET_TEST
  84. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  85. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  86. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  87. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  88. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  89. #define CONFIG_SYS_FLASH_EMPTY_INFO
  90. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
  91. CONFIG_SYS_FLASH_BASE + 0x40000000}
  92. #endif
  93. #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  94. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  95. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  96. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  97. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  98. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  99. | CSPR_V)
  100. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  101. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  102. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  103. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  104. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  105. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  106. | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  107. | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
  108. /* ONFI NAND Flash mode0 Timing Params */
  109. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
  110. FTIM0_NAND_TWP(0x30) | \
  111. FTIM0_NAND_TWCHT(0x0e) | \
  112. FTIM0_NAND_TWH(0x14))
  113. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
  114. FTIM1_NAND_TWBE(0xab) | \
  115. FTIM1_NAND_TRR(0x1c) | \
  116. FTIM1_NAND_TRP(0x30))
  117. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
  118. FTIM2_NAND_TREH(0x14) | \
  119. FTIM2_NAND_TWHRE(0x3c))
  120. #define CONFIG_SYS_NAND_FTIM3 0x0
  121. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  122. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  123. #define CONFIG_MTD_NAND_VERIFY_WRITE
  124. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  125. #define QIXIS_LBMAP_SWITCH 0x06
  126. #define QIXIS_LBMAP_MASK 0x0f
  127. #define QIXIS_LBMAP_SHIFT 0
  128. #define QIXIS_LBMAP_DFLTBANK 0x00
  129. #define QIXIS_LBMAP_ALTBANK 0x04
  130. #define QIXIS_LBMAP_NAND 0x09
  131. #define QIXIS_RST_CTL_RESET 0x31
  132. #define QIXIS_RST_CTL_RESET_EN 0x30
  133. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  134. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  135. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  136. #define QIXIS_RCW_SRC_NAND 0x119
  137. #define QIXIS_RST_FORCE_MEM 0x01
  138. #define CONFIG_SYS_CSPR3_EXT (0x0)
  139. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
  140. | CSPR_PORT_SIZE_8 \
  141. | CSPR_MSEL_GPCM \
  142. | CSPR_V)
  143. #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  144. | CSPR_PORT_SIZE_8 \
  145. | CSPR_MSEL_GPCM \
  146. | CSPR_V)
  147. #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
  148. #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
  149. /* QIXIS Timing parameters for IFC CS3 */
  150. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  151. FTIM0_GPCM_TEADC(0x0e) | \
  152. FTIM0_GPCM_TEAHC(0x0e))
  153. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  154. FTIM1_GPCM_TRAD(0x3f))
  155. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  156. FTIM2_GPCM_TCH(0xf) | \
  157. FTIM2_GPCM_TWP(0x3E))
  158. #define CONFIG_SYS_CS3_FTIM3 0x0
  159. #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
  160. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
  161. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
  162. #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
  163. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  164. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  165. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  166. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  167. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  168. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  169. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  170. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  171. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  172. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  173. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  174. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  175. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  176. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  177. #define CONFIG_SPL_PAD_TO 0x80000
  178. #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
  179. #else
  180. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  181. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
  182. #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
  183. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  184. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  185. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  186. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  187. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  188. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  189. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  190. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  191. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  192. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  193. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  194. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  195. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  196. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  197. #endif
  198. /* Debug Server firmware */
  199. #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
  200. #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
  201. #endif
  202. #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
  203. #ifdef CONFIG_TARGET_LS2081ARDB
  204. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  205. #define QIXIS_QMAP_MASK 0x07
  206. #define QIXIS_QMAP_SHIFT 5
  207. #define QIXIS_LBMAP_DFLTBANK 0x00
  208. #define QIXIS_LBMAP_QSPI 0x00
  209. #define QIXIS_RCW_SRC_QSPI 0x62
  210. #define QIXIS_LBMAP_ALTBANK 0x20
  211. #define QIXIS_RST_CTL_RESET 0x31
  212. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  213. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  214. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  215. #define QIXIS_LBMAP_MASK 0x0f
  216. #define QIXIS_RST_CTL_RESET_EN 0x30
  217. #endif
  218. /*
  219. * I2C
  220. */
  221. #ifdef CONFIG_TARGET_LS2081ARDB
  222. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  223. #endif
  224. #define I2C_MUX_PCA_ADDR 0x75
  225. #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
  226. /* I2C bus multiplexer */
  227. #define I2C_MUX_CH_DEFAULT 0x8
  228. /* SPI */
  229. #if defined(CONFIG_FSL_DSPI)
  230. #define CONFIG_SPI_FLASH_STMICRO
  231. #endif
  232. /*
  233. * RTC configuration
  234. */
  235. #define RTC
  236. #ifdef CONFIG_TARGET_LS2081ARDB
  237. #define CONFIG_SYS_I2C_RTC_ADDR 0x51
  238. #else
  239. #define CONFIG_RTC_DS3231 1
  240. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  241. #endif
  242. /* EEPROM */
  243. #define CONFIG_SYS_I2C_EEPROM_NXID
  244. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  245. #define CONFIG_FSL_MEMAC
  246. #ifdef CONFIG_PCI
  247. #define CONFIG_PCI_SCAN_SHOW
  248. #endif
  249. #define BOOT_TARGET_DEVICES(func) \
  250. func(USB, usb, 0) \
  251. func(MMC, mmc, 0) \
  252. func(SCSI, scsi, 0) \
  253. func(DHCP, dhcp, na)
  254. #include <config_distro_bootcmd.h>
  255. #ifdef CONFIG_TFABOOT
  256. #define QSPI_MC_INIT_CMD \
  257. "sf probe 0:0; " \
  258. "sf read 0x80640000 0x640000 0x80000; " \
  259. "env exists secureboot && " \
  260. "esbc_validate 0x80640000 && " \
  261. "esbc_validate 0x80680000; " \
  262. "sf read 0x80a00000 0xa00000 0x200000; " \
  263. "sf read 0x80e00000 0xe00000 0x100000; " \
  264. "fsl_mc start mc 0x80a00000 0x80e00000 \0"
  265. #define SD_MC_INIT_CMD \
  266. "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
  267. "mmc read 0x80e00000 0x7000 0x800;" \
  268. "env exists secureboot && " \
  269. "mmc read 0x80640000 0x3200 0x20 && " \
  270. "mmc read 0x80680000 0x3400 0x20 && " \
  271. "esbc_validate 0x80640000 && " \
  272. "esbc_validate 0x80680000 ;" \
  273. "fsl_mc start mc 0x80a00000 0x80e00000\0"
  274. #define IFC_MC_INIT_CMD \
  275. "env exists secureboot && " \
  276. "esbc_validate 0x580640000 && " \
  277. "esbc_validate 0x580680000; " \
  278. "fsl_mc start mc 0x580a00000 0x580e00000 \0"
  279. #else
  280. #ifdef CONFIG_QSPI_BOOT
  281. #define MC_INIT_CMD \
  282. "mcinitcmd=sf probe 0:0; " \
  283. "sf read 0x80640000 0x640000 0x80000; " \
  284. "env exists secureboot && " \
  285. "esbc_validate 0x80640000 && " \
  286. "esbc_validate 0x80680000; " \
  287. "sf read 0x80a00000 0xa00000 0x200000; " \
  288. "sf read 0x80e00000 0xe00000 0x100000; " \
  289. "fsl_mc start mc 0x80a00000 0x80e00000 \0"
  290. #elif defined(CONFIG_SD_BOOT)
  291. #define MC_INIT_CMD \
  292. "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
  293. "mmc read 0x80e00000 0x7000 0x800;" \
  294. "env exists secureboot && " \
  295. "mmc read 0x80640000 0x3200 0x20 && " \
  296. "mmc read 0x80680000 0x3400 0x20 && " \
  297. "esbc_validate 0x80640000 && " \
  298. "esbc_validate 0x80680000 ;" \
  299. "fsl_mc start mc 0x80a00000 0x80e00000\0" \
  300. "mcmemsize=0x70000000\0"
  301. #else
  302. #define MC_INIT_CMD \
  303. "mcinitcmd=env exists secureboot && " \
  304. "esbc_validate 0x580640000 && " \
  305. "esbc_validate 0x580680000; " \
  306. "fsl_mc start mc 0x580a00000 0x580e00000 \0"
  307. #endif
  308. #endif
  309. /* Initial environment variables */
  310. #undef CONFIG_EXTRA_ENV_SETTINGS
  311. #ifdef CONFIG_TFABOOT
  312. #define CONFIG_EXTRA_ENV_SETTINGS \
  313. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  314. "ramdisk_addr=0x800000\0" \
  315. "ramdisk_size=0x2000000\0" \
  316. "fdt_high=0xa0000000\0" \
  317. "initrd_high=0xffffffffffffffff\0" \
  318. "fdt_addr=0x64f00000\0" \
  319. "kernel_addr=0x581000000\0" \
  320. "kernel_start=0x1000000\0" \
  321. "kernelheader_start=0x800000\0" \
  322. "scriptaddr=0x80000000\0" \
  323. "scripthdraddr=0x80080000\0" \
  324. "fdtheader_addr_r=0x80100000\0" \
  325. "kernelheader_addr_r=0x80200000\0" \
  326. "kernelheader_addr=0x580600000\0" \
  327. "kernel_addr_r=0x81000000\0" \
  328. "kernelheader_size=0x40000\0" \
  329. "fdt_addr_r=0x90000000\0" \
  330. "load_addr=0xa0000000\0" \
  331. "kernel_size=0x2800000\0" \
  332. "kernel_addr_sd=0x8000\0" \
  333. "kernel_size_sd=0x14000\0" \
  334. "console=ttyAMA0,38400n8\0" \
  335. "mcmemsize=0x70000000\0" \
  336. "sd_bootcmd=echo Trying load from SD ..;" \
  337. "mmcinfo; mmc read $load_addr " \
  338. "$kernel_addr_sd $kernel_size_sd && " \
  339. "bootm $load_addr#$board\0" \
  340. QSPI_MC_INIT_CMD \
  341. BOOTENV \
  342. "boot_scripts=ls2088ardb_boot.scr\0" \
  343. "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
  344. "scan_dev_for_boot_part=" \
  345. "part list ${devtype} ${devnum} devplist; " \
  346. "env exists devplist || setenv devplist 1; " \
  347. "for distro_bootpart in ${devplist}; do " \
  348. "if fstype ${devtype} " \
  349. "${devnum}:${distro_bootpart} " \
  350. "bootfstype; then " \
  351. "run scan_dev_for_boot; " \
  352. "fi; " \
  353. "done\0" \
  354. "boot_a_script=" \
  355. "load ${devtype} ${devnum}:${distro_bootpart} " \
  356. "${scriptaddr} ${prefix}${script}; " \
  357. "env exists secureboot && load ${devtype} " \
  358. "${devnum}:${distro_bootpart} " \
  359. "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  360. "&& esbc_validate ${scripthdraddr};" \
  361. "source ${scriptaddr}\0" \
  362. "qspi_bootcmd=echo Trying load from qspi..;" \
  363. "sf probe && sf read $load_addr " \
  364. "$kernel_start $kernel_size ; env exists secureboot &&" \
  365. "sf read $kernelheader_addr_r $kernelheader_start " \
  366. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  367. " bootm $load_addr#$board\0" \
  368. "nor_bootcmd=echo Trying load from nor..;" \
  369. "cp.b $kernel_addr $load_addr " \
  370. "$kernel_size ; env exists secureboot && " \
  371. "cp.b $kernelheader_addr $kernelheader_addr_r " \
  372. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  373. "bootm $load_addr#$board\0"
  374. #else
  375. #define CONFIG_EXTRA_ENV_SETTINGS \
  376. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  377. "ramdisk_addr=0x800000\0" \
  378. "ramdisk_size=0x2000000\0" \
  379. "fdt_high=0xa0000000\0" \
  380. "initrd_high=0xffffffffffffffff\0" \
  381. "fdt_addr=0x64f00000\0" \
  382. "kernel_addr=0x581000000\0" \
  383. "kernel_start=0x1000000\0" \
  384. "kernelheader_start=0x600000\0" \
  385. "scriptaddr=0x80000000\0" \
  386. "scripthdraddr=0x80080000\0" \
  387. "fdtheader_addr_r=0x80100000\0" \
  388. "kernelheader_addr_r=0x80200000\0" \
  389. "kernelheader_addr=0x580600000\0" \
  390. "kernel_addr_r=0x81000000\0" \
  391. "kernelheader_size=0x40000\0" \
  392. "fdt_addr_r=0x90000000\0" \
  393. "load_addr=0xa0000000\0" \
  394. "kernel_size=0x2800000\0" \
  395. "kernel_addr_sd=0x8000\0" \
  396. "kernel_size_sd=0x14000\0" \
  397. "console=ttyAMA0,38400n8\0" \
  398. "mcmemsize=0x70000000\0" \
  399. "sd_bootcmd=echo Trying load from SD ..;" \
  400. "mmcinfo; mmc read $load_addr " \
  401. "$kernel_addr_sd $kernel_size_sd && " \
  402. "bootm $load_addr#$board\0" \
  403. MC_INIT_CMD \
  404. BOOTENV \
  405. "boot_scripts=ls2088ardb_boot.scr\0" \
  406. "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
  407. "scan_dev_for_boot_part=" \
  408. "part list ${devtype} ${devnum} devplist; " \
  409. "env exists devplist || setenv devplist 1; " \
  410. "for distro_bootpart in ${devplist}; do " \
  411. "if fstype ${devtype} " \
  412. "${devnum}:${distro_bootpart} " \
  413. "bootfstype; then " \
  414. "run scan_dev_for_boot; " \
  415. "fi; " \
  416. "done\0" \
  417. "boot_a_script=" \
  418. "load ${devtype} ${devnum}:${distro_bootpart} " \
  419. "${scriptaddr} ${prefix}${script}; " \
  420. "env exists secureboot && load ${devtype} " \
  421. "${devnum}:${distro_bootpart} " \
  422. "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
  423. "env exists secureboot " \
  424. "&& esbc_validate ${scripthdraddr};" \
  425. "source ${scriptaddr}\0" \
  426. "qspi_bootcmd=echo Trying load from qspi..;" \
  427. "sf probe && sf read $load_addr " \
  428. "$kernel_start $kernel_size ; env exists secureboot &&" \
  429. "sf read $kernelheader_addr_r $kernelheader_start " \
  430. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  431. " bootm $load_addr#$board\0" \
  432. "nor_bootcmd=echo Trying load from nor..;" \
  433. "cp.b $kernel_addr $load_addr " \
  434. "$kernel_size ; env exists secureboot && " \
  435. "cp.b $kernelheader_addr $kernelheader_addr_r " \
  436. "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
  437. "bootm $load_addr#$board\0"
  438. #endif
  439. #ifdef CONFIG_TFABOOT
  440. #define QSPI_NOR_BOOTCOMMAND \
  441. "sf probe 0:0; " \
  442. "sf read 0x806c0000 0x6c0000 0x40000; " \
  443. "env exists mcinitcmd && env exists secureboot "\
  444. "&& esbc_validate 0x806c0000; " \
  445. "sf read 0x80d00000 0xd00000 0x100000; " \
  446. "env exists mcinitcmd && " \
  447. "fsl_mc lazyapply dpl 0x80d00000; " \
  448. "run distro_bootcmd;run qspi_bootcmd; " \
  449. "env exists secureboot && esbc_halt;"
  450. /* Try to boot an on-SD kernel first, then do normal distro boot */
  451. #define SD_BOOTCOMMAND \
  452. "env exists mcinitcmd && env exists secureboot "\
  453. "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
  454. "&& esbc_validate $load_addr; " \
  455. "env exists mcinitcmd && run mcinitcmd " \
  456. "&& mmc read 0x80d00000 0x6800 0x800 " \
  457. "&& fsl_mc lazyapply dpl 0x80d00000; " \
  458. "run distro_bootcmd;run sd_bootcmd; " \
  459. "env exists secureboot && esbc_halt;"
  460. /* Try to boot an on-NOR kernel first, then do normal distro boot */
  461. #define IFC_NOR_BOOTCOMMAND \
  462. "env exists mcinitcmd && env exists secureboot "\
  463. "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
  464. "&& fsl_mc lazyapply dpl 0x580d00000;" \
  465. "run distro_bootcmd;run nor_bootcmd; " \
  466. "env exists secureboot && esbc_halt;"
  467. #else
  468. #undef CONFIG_BOOTCOMMAND
  469. #ifdef CONFIG_QSPI_BOOT
  470. /* Try to boot an on-QSPI kernel first, then do normal distro boot */
  471. #define CONFIG_BOOTCOMMAND \
  472. "sf probe 0:0; " \
  473. "sf read 0x806c0000 0x6c0000 0x40000; " \
  474. "env exists mcinitcmd && env exists secureboot "\
  475. "&& esbc_validate 0x806C0000; " \
  476. "sf read 0x80d00000 0xd00000 0x100000; " \
  477. "env exists mcinitcmd && " \
  478. "fsl_mc lazyapply dpl 0x80d00000; " \
  479. "run distro_bootcmd;run qspi_bootcmd; " \
  480. "env exists secureboot && esbc_halt;"
  481. #elif defined(CONFIG_SD_BOOT)
  482. /* Try to boot an on-SD kernel first, then do normal distro boot */
  483. #define CONFIG_BOOTCOMMAND \
  484. "env exists mcinitcmd && env exists secureboot "\
  485. "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
  486. "&& esbc_validate $load_addr; " \
  487. "env exists mcinitcmd && run mcinitcmd " \
  488. "&& mmc read 0x88000000 0x6800 0x800 " \
  489. "&& fsl_mc lazyapply dpl 0x88000000; " \
  490. "run distro_bootcmd;run sd_bootcmd; " \
  491. "env exists secureboot && esbc_halt;"
  492. #else
  493. /* Try to boot an on-NOR kernel first, then do normal distro boot */
  494. #define CONFIG_BOOTCOMMAND \
  495. "env exists mcinitcmd && env exists secureboot "\
  496. "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
  497. "&& fsl_mc lazyapply dpl 0x580d00000;" \
  498. "run distro_bootcmd;run nor_bootcmd; " \
  499. "env exists secureboot && esbc_halt;"
  500. #endif
  501. #endif
  502. /* MAC/PHY configuration */
  503. #define CORTINA_PHY_ADDR1 0x10
  504. #define CORTINA_PHY_ADDR2 0x11
  505. #define CORTINA_PHY_ADDR3 0x12
  506. #define CORTINA_PHY_ADDR4 0x13
  507. #define AQ_PHY_ADDR1 0x00
  508. #define AQ_PHY_ADDR2 0x01
  509. #define AQ_PHY_ADDR3 0x02
  510. #define AQ_PHY_ADDR4 0x03
  511. #define AQR405_IRQ_MASK 0x36
  512. #define CONFIG_ETHPRIME "DPMAC1@xgmii"
  513. #include <asm/fsl_secure_boot.h>
  514. #endif /* __LS2_RDB_H */