ls1046aqds.h 14 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __LS1046AQDS_H__
  6. #define __LS1046AQDS_H__
  7. #include "ls1046a_common.h"
  8. #ifndef __ASSEMBLY__
  9. unsigned long get_board_sys_clk(void);
  10. #endif
  11. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  12. #define CONFIG_LAYERSCAPE_NS_ACCESS
  13. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  14. /* Physical Memory Map */
  15. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  16. #define SPD_EEPROM_ADDRESS 0x51
  17. #define CONFIG_SYS_SPD_BUS_NUM 0
  18. #ifdef CONFIG_DDR_ECC
  19. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  20. #endif
  21. /* DSPI */
  22. #ifdef CONFIG_FSL_DSPI
  23. #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
  24. #define CONFIG_SPI_FLASH_SST /* cs1 */
  25. #define CONFIG_SPI_FLASH_EON /* cs2 */
  26. #endif
  27. #ifdef CONFIG_SYS_DPAA_FMAN
  28. #define RGMII_PHY1_ADDR 0x1
  29. #define RGMII_PHY2_ADDR 0x2
  30. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  31. #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  32. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  33. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  34. /* PHY address on QSGMII riser card on slot 2 */
  35. #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  36. #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  37. #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  38. #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  39. #endif
  40. /* IFC */
  41. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  42. #define CONFIG_FSL_IFC
  43. /*
  44. * CONFIG_SYS_FLASH_BASE has the final address (core view)
  45. * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  46. * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  47. * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
  48. */
  49. #define CONFIG_SYS_FLASH_BASE 0x60000000
  50. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  51. #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
  52. #ifdef CONFIG_MTD_NOR_FLASH
  53. #define CONFIG_SYS_FLASH_QUIET_TEST
  54. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  55. #endif
  56. #endif
  57. /* LPUART */
  58. #ifdef CONFIG_LPUART
  59. #define CONFIG_LPUART_32B_REG
  60. #define CFG_UART_MUX_MASK 0x6
  61. #define CFG_UART_MUX_SHIFT 1
  62. #define CFG_LPUART_EN 0x2
  63. #endif
  64. /* EEPROM */
  65. #define CONFIG_SYS_I2C_EEPROM_NXID
  66. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  67. /*
  68. * IFC Definitions
  69. */
  70. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  71. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  72. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  73. CSPR_PORT_SIZE_16 | \
  74. CSPR_MSEL_NOR | \
  75. CSPR_V)
  76. #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
  77. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  78. + 0x8000000) | \
  79. CSPR_PORT_SIZE_16 | \
  80. CSPR_MSEL_NOR | \
  81. CSPR_V)
  82. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
  83. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  84. CSOR_NOR_TRHZ_80)
  85. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  86. FTIM0_NOR_TEADC(0x5) | \
  87. FTIM0_NOR_TAVDS(0x6) | \
  88. FTIM0_NOR_TEAHC(0x5))
  89. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  90. FTIM1_NOR_TRAD_NOR(0x1a) | \
  91. FTIM1_NOR_TSEQRAD_NOR(0x13))
  92. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
  93. FTIM2_NOR_TCH(0x8) | \
  94. FTIM2_NOR_TWPH(0xe) | \
  95. FTIM2_NOR_TWP(0x1c))
  96. #define CONFIG_SYS_NOR_FTIM3 0
  97. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  98. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  99. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  100. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  101. #define CONFIG_SYS_FLASH_EMPTY_INFO
  102. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
  103. CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  104. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  105. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  106. /*
  107. * NAND Flash Definitions
  108. */
  109. #define CONFIG_SYS_NAND_BASE 0x7e800000
  110. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  111. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  112. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  113. | CSPR_PORT_SIZE_8 \
  114. | CSPR_MSEL_NAND \
  115. | CSPR_V)
  116. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  117. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  118. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  119. | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
  120. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  121. | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
  122. | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
  123. | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
  124. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
  125. FTIM0_NAND_TWP(0x18) | \
  126. FTIM0_NAND_TWCHT(0x7) | \
  127. FTIM0_NAND_TWH(0xa))
  128. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  129. FTIM1_NAND_TWBE(0x39) | \
  130. FTIM1_NAND_TRR(0xe) | \
  131. FTIM1_NAND_TRP(0x18))
  132. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
  133. FTIM2_NAND_TREH(0xa) | \
  134. FTIM2_NAND_TWHRE(0x1e))
  135. #define CONFIG_SYS_NAND_FTIM3 0x0
  136. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  137. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  138. #define CONFIG_MTD_NAND_VERIFY_WRITE
  139. #endif
  140. #ifdef CONFIG_NAND_BOOT
  141. #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
  142. #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
  143. #endif
  144. #if defined(CONFIG_TFABOOT) || \
  145. defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  146. #define CONFIG_QIXIS_I2C_ACCESS
  147. #endif
  148. /*
  149. * QIXIS Definitions
  150. */
  151. #define CONFIG_FSL_QIXIS
  152. #ifdef CONFIG_FSL_QIXIS
  153. #define QIXIS_BASE 0x7fb00000
  154. #define QIXIS_BASE_PHYS QIXIS_BASE
  155. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  156. #define QIXIS_LBMAP_SWITCH 6
  157. #define QIXIS_LBMAP_MASK 0x0f
  158. #define QIXIS_LBMAP_SHIFT 0
  159. #define QIXIS_LBMAP_DFLTBANK 0x00
  160. #define QIXIS_LBMAP_ALTBANK 0x04
  161. #define QIXIS_LBMAP_NAND 0x09
  162. #define QIXIS_LBMAP_SD 0x00
  163. #define QIXIS_LBMAP_SD_QSPI 0xff
  164. #define QIXIS_LBMAP_QSPI 0xff
  165. #define QIXIS_RCW_SRC_NAND 0x110
  166. #define QIXIS_RCW_SRC_SD 0x040
  167. #define QIXIS_RCW_SRC_QSPI 0x045
  168. #define QIXIS_RST_CTL_RESET 0x41
  169. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  170. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  171. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  172. #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  173. #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
  174. CSPR_PORT_SIZE_8 | \
  175. CSPR_MSEL_GPCM | \
  176. CSPR_V)
  177. #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
  178. #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  179. CSOR_NOR_NOR_MODE_AVD_NOR | \
  180. CSOR_NOR_TRHZ_80)
  181. /*
  182. * QIXIS Timing parameters for IFC GPCM
  183. */
  184. #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
  185. FTIM0_GPCM_TEADC(0x20) | \
  186. FTIM0_GPCM_TEAHC(0x10))
  187. #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
  188. FTIM1_GPCM_TRAD(0x1f))
  189. #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
  190. FTIM2_GPCM_TCH(0x8) | \
  191. FTIM2_GPCM_TWP(0xf0))
  192. #define CONFIG_SYS_FPGA_FTIM3 0x0
  193. #endif
  194. #ifdef CONFIG_TFABOOT
  195. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  196. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  197. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  198. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  199. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  200. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  201. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  202. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  203. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  204. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  205. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  206. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  207. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  208. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  209. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  210. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  211. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  212. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  213. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  214. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  215. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  216. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  217. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  218. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  219. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  220. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  221. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  222. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  223. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  224. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  225. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  226. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  227. #else
  228. #ifdef CONFIG_NAND_BOOT
  229. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  230. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  231. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  232. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  233. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  234. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  235. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  236. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  237. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  238. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  239. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  240. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  241. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  242. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  243. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  244. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  245. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  246. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  247. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  248. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  249. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  250. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  251. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  252. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  253. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  254. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  255. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  256. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  257. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  258. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  259. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  260. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  261. #else
  262. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  263. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  264. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  265. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  266. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  267. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  268. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  269. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  270. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  271. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  272. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  273. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  274. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  275. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  276. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  277. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  278. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  279. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  280. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  281. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  282. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  283. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  284. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  285. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  286. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  287. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  288. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  289. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  290. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  291. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  292. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  293. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  294. #endif
  295. #endif
  296. /*
  297. * I2C bus multiplexer
  298. */
  299. #define I2C_MUX_PCA_ADDR_PRI 0x77
  300. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
  301. #define I2C_RETIMER_ADDR 0x18
  302. #define I2C_MUX_CH_DEFAULT 0x8
  303. #define I2C_MUX_CH_CH7301 0xC
  304. #define I2C_MUX_CH5 0xD
  305. #define I2C_MUX_CH6 0xE
  306. #define I2C_MUX_CH7 0xF
  307. #define I2C_MUX_CH_VOL_MONITOR 0xa
  308. /* Voltage monitor on channel 2*/
  309. #define I2C_VOL_MONITOR_ADDR 0x40
  310. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  311. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  312. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  313. #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv"
  314. #ifndef CONFIG_SPL_BUILD
  315. #define CONFIG_VID
  316. #endif
  317. #define CONFIG_VOL_MONITOR_IR36021_SET
  318. #define CONFIG_VOL_MONITOR_INA220
  319. /* The lowest and highest voltage allowed for LS1046AQDS */
  320. #define VDD_MV_MIN 819
  321. #define VDD_MV_MAX 1212
  322. /*
  323. * Miscellaneous configurable options
  324. */
  325. #define CONFIG_SYS_HZ 1000
  326. #define CONFIG_SYS_INIT_SP_OFFSET \
  327. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  328. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  329. /*
  330. * Environment
  331. */
  332. #undef CONFIG_BOOTCOMMAND
  333. #ifdef CONFIG_TFABOOT
  334. #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
  335. "env exists secureboot && esbc_halt;;"
  336. #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd" \
  337. "env exists secureboot && esbc_halt;;"
  338. #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
  339. "env exists secureboot && esbc_halt;;"
  340. #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
  341. "env exists secureboot && esbc_halt;;"
  342. #else
  343. #if defined(CONFIG_QSPI_BOOT)
  344. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
  345. "env exists secureboot && esbc_halt;;"
  346. #elif defined(CONFIG_NAND_BOOT)
  347. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \
  348. "env exists secureboot && esbc_halt;;"
  349. #elif defined(CONFIG_SD_BOOT)
  350. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
  351. "env exists secureboot && esbc_halt;;"
  352. #else
  353. #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
  354. "env exists secureboot && esbc_halt;;"
  355. #endif
  356. #endif
  357. #include <asm/fsl_secure_boot.h>
  358. #endif /* __LS1046AQDS_H__ */